ADC board card batch test method and system

Abstract

The invention relates to an ADC board card batch test method and system. The method comprises the steps that multiple LPC buses are communicated through an FPGA; based on a preset communication protocol, outputting a plurality of constant current source output signals through the FPGA; the plurality of ADC board cards to be tested respectively sample the corresponding constant current source output signals to obtain a plurality of constant current source sampling signals; and respectively calculating error values of the constant current source output signals and the corresponding constant current source sampling signals so as to complete batch testing of the plurality of ADC board cards to be tested. According to the invention, the automatic cycle test of the ADC board card can be carried out through FPGA control, the test efficiency of the ADC sampling board card can be improved, and time and cost are saved.

Description

Technical Field

[0001] The present invention relates to the technical field of PC peripheral equipment testing, and in particular to a method and system for batch testing ADC boards. Background Art

[0002] In the design of embedded computer systems, ADC sampling boards are commonly used peripheral boards. ADC boards often contain multi-channel ADC sampling. The current test environment for commonly used ADC boards usually requires signal generators, test motherboards, test baseboards and other equipment. Test engineers then manually read the ADC test results on the motherboard to determine whether the board is normal. When faced with batches of boards, it usually takes a long time to test, and the workload is huge. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the related art. To this end, the present invention provides a method and system for batch testing of ADC boards.

[0004] A first aspect of the present invention provides a method for batch testing an ADC board, comprising:

[0005] S1: Connect multiple LPC buses through FPGA;

[0006] S2: Based on the preset communication protocol, multiple constant current source output signals are output through FPGA;

[0007] S3: multiple ADC boards to be tested respectively sample corresponding constant current source output signals to obtain multiple constant current source sampling signals;

[0008] S4: respectively calculating the error values ​​of the constant current source output signal and the corresponding constant current source sampling signal to complete batch testing of multiple ADC boards to be tested.

[0009] According to a method for batch testing ADC boards provided by the present invention, the preset communication protocol in step S2 is the IIC communication protocol.

[0010] According to a method for batch testing ADC boards provided by the present invention, in step S2, each of the constant current source output signals includes multiple constant current sources.

[0011] According to a method for batch testing of ADC boards provided by the present invention, step S2 further comprises:

[0012] S21: The FPGA outputs a digital-to-analog signal based on the preset communication protocol;

[0013] S22: a digital-to-analog converter receives the digital-to-analog signal;

[0014] S23: The digital-to-analog converter generates multiple constant current sources according to the digital-to-analog signal, and obtains and outputs the constant current source output signal.

[0015] A second aspect of the present invention provides an ADC board batch testing system for executing the ADC board batch testing method as described above, comprising:

[0016] FPGA module, VPX module;

[0017] The FPGA module includes a multi-channel switching unit, a DA control unit, a collection unit and a calculation unit;

[0018] The multi-channel switching unit is used to respectively connect multiple LPC buses, and based on the connected multiple LPC buses, are respectively connected to the ADC board to be tested through the VPX module, and the DA control unit is used to output multiple constant current source output signals;

[0019] The acquisition unit is used to acquire multiple constant current source output signals output by the DA control unit, and is also used to respectively acquire constant current source sampling signals obtained by sampling corresponding constant current source signals of multiple ADC boards to be tested, and send the acquired constant current source output signals and constant current source sampling signals to the calculation unit;

[0020] The calculation unit is used to receive the constant current source output signal and the constant current source sampling signal sent by the acquisition unit, and calculate the error value between the constant current source output signal and the constant current source sampling signal corresponding to the ADC board to be tested, so as to complete batch testing of multiple ADC boards to be tested.

[0021] An ADC board batch testing system provided by the present invention also includes:

[0022] Display module;

[0023] The display module is used to display the constant current source output signal and the constant current source sampling signal collected by the collection unit, and the error value calculated by the calculation unit.

[0024] An ADC board batch testing system provided by the present invention also includes:

[0025] Multi-way switch module;

[0026] The multi-way switch module is respectively connected to the multi-way switch unit of the FPGA module and the VPX module. The multi-way switch module is used to receive a control signal from the multi-way switch unit and connect the corresponding LPC bus based on the control signal to connect the FPGA module to the ADC board to be tested.

[0027] An ADC board batch testing system provided by the present invention also includes:

[0028] Digital to analog converters;

[0029] The digital-to-analog converter is connected to the DA control unit and the VPX module of the FPGA module respectively, and is used to receive the digital-to-analog signal of the DA control unit and output a plurality of constant current source output signals including multiple constant current sources based on the digital-to-analog signal.

[0030] According to an ADC board batch testing system provided by the present invention, the FPGA module further includes:

[0031] Clock unit and PLL unit;

[0032] The clock unit is used to obtain a reference time from an external time source, and the PLL unit is used to synchronize the time of any module in the ADC board batch test system based on the reference time obtained by the clock unit.

[0033] An ADC board batch testing system provided by the present invention also includes:

[0034] Power module;

[0035] The power supply module is used to supply power to any module in the ADC board batch test system;

[0036] The power module is a HP4644 power chip.

[0037] The present invention provides an ADC board batch testing method and system, which aims to solve the problem that in the traditional method, when facing batch ADC board testing, test engineers need to connect, test and record the results one by one, which is time-consuming and labor-intensive. The present invention connects multiple LPC buses respectively through FPGA, and can realize parallel testing of multiple ADC boards to be tested, which significantly improves the test efficiency, especially when processing a large number of boards, the time required for testing can be greatly reduced; the present invention automatically outputs constant current source signals through a preset communication protocol, and automatically collects sampling signals of ADC boards, reduces manual intervention through an automated test process, not only improves the accuracy and consistency of the test, but also reduces the risk of human error; in addition, the FPGA centrally controls and manages the output of multiple constant current sources and the collection and processing of ADC sampling signals, so that the entire test system is more integrated and compact, the complexity of the test equipment is reduced, and the deployment and maintenance of the test system are also facilitated; due to the programmability of FPGA, the test method of the present invention can be flexibly configured and adjusted according to different ADC board characteristics and test requirements, which means that the test system can adapt to various types of ADC board tests, and improves the versatility and flexibility of the system; the automated and efficient test method of the present invention reduces the dependence on a large number of test engineers and reduces labor costs. At the same time, due to the simplification of the test process and the improvement of integration, it may also reduce the demand for additional test equipment, thereby further reducing the test cost.

[0038] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 It is a flow chart of a method for batch testing of ADC boards provided by an embodiment of the present invention;

[0041] Figure 2 The present invention provides a schematic diagram of the structure of an ADC board batch testing system.

[0042] Reference numerals:

[0043] 100, FPGA module; 200, VPX module; 300, display module; 400, multi-way switch module; 500, digital-to-analog converter; 600, power module;

[0044] 110, multi-channel switching unit; 120, DA control unit; 130, acquisition unit; 140, calculation unit; 150, clock unit; 160, PLL unit. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme of the present invention will be clearly and completely described below in conjunction with the drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention. The following embodiments are used to illustrate the present invention, but cannot be used to limit the scope of the present invention.

[0046] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiment of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0047] Combine the following Figure 1 to Figure 2 Embodiments of the present invention are described.

[0048] like Figure 1 As shown, the first aspect of the present invention provides a method for batch testing of ADC boards, comprising:

[0049] S1: Multiple LPC buses are connected through FPGA.

[0050] The LPC bus in step S1 is used to connect the FPGA and multiple ADC boards to be tested or other related components. In this step, multiple ADC sampling board pairs to be tested are first inserted into the VPX module, and then a communication connection between the FPGA and the multiple ADC boards to be tested is established to prepare for subsequent signal output and sampling.

[0051] S2: Based on the preset communication protocol, multiple constant current source output signals are output through FPGA.

[0052] Wherein, the preset communication protocol in step S2 is the IIC communication protocol.

[0053] Wherein, in step S2, each of the constant current source output signals includes multiple constant current sources.

[0054] Wherein, step S2 further comprises:

[0055] S21: The FPGA outputs a digital-to-analog signal based on the preset communication protocol;

[0056] S22: a digital-to-analog converter receives the digital-to-analog signal;

[0057] S23: The digital-to-analog converter generates multiple constant current sources according to the digital-to-analog signal, and obtains and outputs the constant current source output signal.

[0058] In steps S21 to S23, FPGA acts as a control unit, firstly generates and outputs a digital analog signal according to the IIC communication protocol, and the signal is used to control the digital-to-analog converter to output a specific analog quantity. FPGA communicates with DAC through the IIC protocol, and after sending a digital signal containing the required analog quantity information, the digital-to-analog converter receives and interprets the digital signal sent by FPGA, and generates a corresponding analog output according to the signal. Finally, by precisely controlling the output of DAC, the required multi-channel constant current source can be obtained to meet the needs of simultaneous testing of multiple ADC boards.

[0059] S3: The multiple ADC boards to be tested respectively sample the corresponding constant current source output signals to obtain multiple constant current source sampling signals.

[0060] Specifically, each ADC board will have one or more input channels, which will be connected to the output end of the constant current source. When the constant current source outputs a stable current signal, the ADC board will sample these current signals at a preset sampling rate (i.e., the number of samples per second). During the sampling process, the circuit inside the ADC board will measure the current signal and convert it into a corresponding digital value. By sampling the output signal of the constant current source, performance indicators such as the conversion accuracy and stability of the ADC board for the actual signal can be obtained.

[0061] S4: respectively calculating the error values ​​of the constant current source output signal and the corresponding constant current source sampling signal to complete batch testing of multiple ADC boards to be tested.

[0062] In step S4, firstly, the actual value or theoretical value of the constant current source output signal is obtained as a reference value, which can be directly measured by a measuring device. Of course, under certain circumstances, the value can also be calculated according to the setting parameters of the constant current source; subsequently, the sampling signal (i.e., digital quantity) of each ADC board is converted back to the corresponding analog quantity, and then compared with the reference value; after obtaining the difference, different types of error values ​​can be calculated as needed, and these error values ​​provide specific quantitative indicators about the performance of the ADC board.

[0063] like Figure 2 As shown, the second aspect of the present invention provides an ADC board batch testing system, comprising:

[0064] FPGA module 100, VPX module 200;

[0065] The FPGA module 100 includes a multi-way switching unit 110, a DA control unit 120, a collection unit 130 and a calculation unit 140;

[0066] The multi-channel switching unit 110 is used to respectively connect multiple LPC buses, and based on the connected multiple LPC buses, are respectively connected to the ADC board to be tested through the VPX module 200, and the DA control unit 120 is used to output multiple constant current source output signals;

[0067] The acquisition unit 130 is used to acquire multiple constant current source output signals output by the DA control unit 120, and is also used to respectively acquire constant current source sampling signals obtained by sampling corresponding constant current source signals of multiple ADC boards to be tested, and send the acquired constant current source output signals and constant current source sampling signals to the calculation unit 140;

[0068] The calculation unit 140 is used to receive the constant current source output signal and the constant current source sampling signal sent by the acquisition unit 130, and calculate the error value between the constant current source output signal and the constant current source sampling signal corresponding to the ADC board to be tested, so as to complete batch testing of multiple ADC boards to be tested.

[0069] Among them, it also includes:

[0070] Display module 300;

[0071] The display module 300 is used to display the constant current source output signal and the constant current source sampling signal collected by the collection unit 130 , and the error value calculated by the calculation unit 140 .

[0072] Among them, it also includes:

[0073] Multi-way switch module 400;

[0074] The multi-way switch module 400 is respectively connected to the multi-way switch unit 110 of the FPGA module 100 and the VPX module 200. The multi-way switch module 400 is used to receive a control signal from the multi-way switch unit 110, and connect the corresponding LPC bus based on the control signal to connect the FPGA module 100 to the ADC board to be tested.

[0075] Among them, it also includes:

[0076] Digital to analog converter 500;

[0077] The digital-to-analog converter 500 is connected to the DA control unit 110 of the FPGA module 100 and the VPX module 200 respectively. The digital-to-analog converter 500 is used to receive the digital-to-analog signal of the DA control unit 110 and output a plurality of constant current source output signals including multiple constant current sources based on the digital-to-analog signal.

[0078] Wherein, the FPGA module 100 further includes:

[0079] A clock unit 150 and a PLL unit 160;

[0080] The clock unit 150 is used to obtain a reference time from an external time source, and the PLL unit 160 is used to synchronize the time of any module in the ADC board batch test system based on the reference time obtained by the clock unit 150 .

[0081] Among them, it also includes:

[0082] Power module 600;

[0083] The power supply module 600 is used to supply power to any module in the ADC board batch test system;

[0084] The power module 600 is a HP4644 power chip.

[0085] Furthermore, the connection relationship of the system provided by the present invention is as follows: the display module is connected to the FPGA module, the power module is connected to the FPGA module, the power module is connected to the digital-to-analog converter (DA conversion module), the power module is connected to the VPX module (VPX module), the power module is connected to the multi-way switch module, the FPGA module is connected to the digital-to-analog converter, the FPGA module is connected to the VPX module, the FPGA module is connected to the multi-way switch module, the digital-to-analog converter is connected to the VPX module, and the multi-way switch module is connected to the VPX module.

[0086] In a specific embodiment, the display module is an LCD display screen, the clock unit is a 33M domestically produced clock chip, the power module is a domestically produced power chip HP4644, the digital-to-analog converter is a DA conversion chip GP8302, the VPX module includes N VPX interface connectors, and the multi-way switch module is a multi-way switch SN74LVC4245.

[0087] In order to better understand the present invention, the ADC board batch testing method provided by the present invention is further described below in combination with the above-mentioned ADC board batch testing system.

[0088] Insert multiple ADC sampling board pairs to be tested into the VPX module. After the system is powered on, the clock module outputs a clock signal to the FPGA module, and the power module outputs power to the FPGA module, the digital-to-analog converter, the VPX module, and the multi-way switch module.

[0089] Press the button of the key module to start. After the FPGA module receives the start signal from the key module, it starts the system test. First, the multi-way switching unit in the FPGA module controls the multi-way switch module to connect the first LPC bus.

[0090] The DA control unit of the FPGA module outputs N DA signals to the digital-to-analog converter according to the IIC communication protocol. The digital-to-analog converter outputs N constant current sources and forwards them to the VPX module. At the same time, the DA output value is sent to the display unit, and the display unit displays the DA output value on the LCD screen according to the LCD screen protocol.

[0091] The ADC sampling board to be tested inserted in the VPX module samples the constant current source signal and stores the sampled value.

[0092] The acquisition unit in the FPGA module issues a read command, and sends the read command to the ADC sampling board through the VPX module to read the sampling value of the ADC sampling board. The acquisition unit sends the sampling value data of the ADC sampling board to the display control unit. The display control unit receives the ADC sampling value and displays the value on the LCD screen according to the protocol. At the same time, the digital value sampled by the ADC is compared with the DA output value, the ADC sampling error value is calculated, and the value is displayed on the display module.

[0093] The multi-way switching unit in the FPGA module controls the multi-way switch module, connects the second LPC bus, and automatically cycles to test the next board until all tests are completed.

[0094] The present invention adopts FPGA as the main controller, automatically applies sampling source signals to the board to be tested, and performs automatic cycle testing through FPGA control, eliminating various test equipment required in the traditional test environment, and can greatly improve the test efficiency of the ADC sampling board, simplify the test, save time, and reduce labor costs.

[0095] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A batch testing method for ADC boards, characterized in that: include: S1: Connect multiple LPC buses through FPGA; S2: Based on the preset communication protocol, multiple constant current source output signals are output through FPGA; S3: multiple ADC boards to be tested respectively sample corresponding constant current source output signals to obtain multiple constant current source sampling signals; S4: respectively calculating the error values ​​of the constant current source output signal and the corresponding constant current source sampling signal to complete batch testing of multiple ADC boards to be tested.

2. A method for batch testing ADC boards according to claim 1, characterized in that: The preset communication protocol in step S2 is the IIC communication protocol.

3. A method for batch testing ADC boards according to claim 1, characterized in that: In step S2, each of the constant current source output signals includes multiple constant current sources.

4. A method for batch testing ADC boards according to claim 1, characterized in that: Step S2 further comprises: S21: The FPGA outputs a digital-to-analog signal based on the preset communication protocol; S22: a digital-to-analog converter receives the digital-to-analog signal; S23: The digital-to-analog converter generates multiple constant current sources according to the digital-to-analog signal, and obtains and outputs the constant current source output signal.

5. An ADC board batch testing system, used to execute an ADC board batch testing method as claimed in claims 1 to 4, characterized in that: include: FPGA module, VPX module; The FPGA module includes a multi-channel switching unit, a DA control unit, a collection unit and a calculation unit; The multi-channel switching unit is used to respectively connect multiple LPC buses, and based on the connected multiple LPC buses, are respectively connected to the ADC board to be tested through the VPX module, and the DA control unit is used to output multiple constant current source output signals; The acquisition unit is used to acquire multiple constant current source output signals output by the DA control unit, and is also used to respectively acquire constant current source sampling signals obtained by sampling corresponding constant current source signals of multiple ADC boards to be tested, and send the acquired constant current source output signals and constant current source sampling signals to the calculation unit; The calculation unit is used to receive the constant current source output signal and the constant current source sampling signal sent by the acquisition unit, and calculate the error value between the constant current source output signal and the constant current source sampling signal corresponding to the ADC board to be tested, so as to complete batch testing of multiple ADC boards to be tested.

6. The ADC board batch testing system according to claim 5, characterized in that: Also includes: Display module; The display module is used to display the constant current source output signal and the constant current source sampling signal collected by the collection unit, and the error value calculated by the calculation unit.

7. The ADC board batch testing system according to claim 5, characterized in that: Also includes: Multi-way switch module; The multi-way switch module is respectively connected to the multi-way switch unit of the FPGA module and the VPX module. The multi-way switch module is used to receive a control signal from the multi-way switch unit and connect the corresponding LPC bus based on the control signal to connect the FPGA module to the ADC board to be tested.

8. The ADC board batch testing system according to claim 5, characterized in that: Also includes: Digital to analog converters; The digital-to-analog converter is connected to the DA control unit and the VPX module of the FPGA module respectively, and is used to receive the digital-to-analog signal of the DA control unit and output a plurality of constant current source output signals including multiple constant current sources based on the digital-to-analog signal.

9. The ADC board batch testing system according to claim 5, characterized in that: The FPGA module also includes: Clock unit and PLL unit; The clock unit is used to obtain a reference time from an external time source, and the PLL unit is used to synchronize the time of any module in the ADC board batch test system based on the reference time obtained by the clock unit.

10. The ADC board batch testing system according to claim 5, characterized in that: Also includes: Power module; The power supply module is used to supply power to any module in the ADC board batch test system; The power module is a HP4644 power chip.

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