Power beam splitter with on-chip integrated metasurface

Abstract

The invention discloses a power beam splitter with an on-chip integrated metasurface, which is characterized in that a polarization-insensitive cylindrical metasurface is prepared on a substrate surface of a back-emitting vertical cavity surface emitting laser (VCSEL) by using a semiconductor planarization process, so that a power beam splitting function is realized. Laser emitted by the VCSEL is split into two beams of light after passing through the super-structure surface, the two beams of light are respectively projected on adjacent diffraction orders, and the energy ratio of the adjacent diffraction orders is adjustable. According to the on-chip integrated power beam splitter, the size of an optical device can be effectively reduced, accurate alignment of the beam splitter and the laser can be achieved, and the correctness of the light beam projection angle is guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronics, and mainly designs a power beam splitter with an on-chip integrated metasurface for a VCSEL light source. Background Art

[0002] Beam splitters are key components used in many optical systems to distribute and combine beam paths. They can split a beam into two or more beams and are widely used in interferometers, spectrometers, optical communications, etc. However, traditional beam splitters are large and bulky, which limits their further application in compact optical systems.

[0003] Metasurfaces have received widespread attention in many application fields, such as holography, polarization optical devices, superlenses, etc. Metasurface is an artificial optical surface composed of two-dimensional subwavelength units, which can flexibly manipulate electromagnetic waves of different dimensions, such as amplitude, phase and polarization. Its ultra-thin thickness and control flexibility make it more suitable for photonic integrated systems than traditional optical devices. In recent years, optical beam splitters based on metasurfaces have been continuously proposed, but there are currently two problems with this type of beam splitter: 1) The current metasurface beam splitters all use a structure in which the light source and the metasurface are separated. The overall optical path is long and is not suitable for photonic integrated systems. 2) Separate metasurface optical beam splitters often require manual alignment, which is prone to large measurement errors. Summary of the invention

[0004] Currently, the manufacturing of miniaturized devices is gradually becoming a mainstream trend, but traditional separated metasurface beam splitters require external light sources for illumination. The optical path is long and not compact enough, and the precise alignment of the light source and the beam splitter cannot be guaranteed.

[0005] The technical solution adopted by the present invention is a power beam splitter with an on-chip integrated metasurface, and a dielectric metasurface is successfully prepared on the back-emitting VCSEL substrate surface using semiconductor standard planar processing technology. The power beam splitter is composed of: P-surface electrode 8, benzocyclobutene (BCB) 7, P-surface distributed Bragg reflector 6, oxide hole 5, N-surface distributed Bragg reflector 4, gallium arsenide substrate 3, N-surface electrode 2, and metasurface 1 from bottom to top. The light emitted from the active area is divided into two beams after passing through the metasurface on the VCSEL substrate, and is projected on the 0, -1 order or -1, -2 order respectively, and the energy ratio of adjacent orders can be adjusted.

[0006] Furthermore, the energy regulation of different diffraction orders can be achieved by removing the total phase gradient limitation of 2π.

[0007] Furthermore, the phase profile function of the metasurface is determined by formula (1):

[0008]

[0009] where θ t , n t Represent the projection angle and the refractive index of the projection medium, θ and n represent the incident angle and the refractive index of the incident medium, λ is the wavelength of the laser, △ is the super unit of the metasurface, and N is the function factor.

[0010] Furthermore, when the projection medium is air, n t =1, θ = 0°, n = the refractive index of GaAs medium is 3.52, the laser wavelength is 980nm, the lattice constant of the superatom is 300nm, the height is 700nm, and 9 superatoms are selected to form a super unit of 2.7μm. The phase coverage of the whole superatom is 2π, and the average transmittance is above 80%.

[0011] Furthermore, a standard semiconductor planar process is used to prepare a back-emitting VCSEL and a cylindrical nanostructure is processed on its substrate. After the laser emitted from the active region passes through the metasurface, the beam will be projected onto adjacent 0, -1 or -1, -2 diffraction orders, and the energy ratio of adjacent diffraction orders is tunable. The specific process steps are as follows:

[0012] (1) Use plasma enhanced chemical vapor deposition (PECVD) to grow a 500nm thick layer of silicon dioxide SiO on the P surface of the epitaxial wafer. 2 Etch stop layer, SiO 2 The growth rate is 15 Å / s.

[0013] (2) The designed layout was used for photolithography. The photoresist selected was AZ5214, and its spin coating thickness was 1.4 μm at 4000 rpm. After photolithography, the photoresist was cured and the SiO2 outside the truncated cone was realized by wet etching. 2 The etching solution used was BOE solution with an etching rate of 50nm / s. 2 The epitaxial wafer with the mask is cleaned and dried using a pre-treatment cleaning method. The uncovered SiO 2 The P-side DBR layer is etched, and the etching depth is the depth from the P-side surface to the peroxide restriction layer, which is greater than 4.8μm and less than 7μm. A step meter is used to confirm whether the etching reaches the predetermined depth.

[0014] (3) Clean the epitaxial wafer after ICP etching and use BOE solution to remove SiO 2 Mask layer, use a step meter to confirm whether its thickness meets the standard.

[0015] (4) The device is oxidized by a wet oxidation process, where nitrogen gas is passed through a 100°C constant temperature water area into a constant temperature chamber set at 400°C at a flow rate of 1 sccm / min. The oxidation rate of the back-emitting VCSEL epitaxial structure used is 0.97 μm / min.

[0016] (5) Clean the oxidized laser epitaxial wafer again and dry it, and grow a 500nm thick SiO layer on the epitaxial wafer using PECVD. 2 Passivation layer to achieve the purpose of side wall electrical insulation.

[0017] (6) The surface is planarized and BCB is spin-coated at a spin coating parameter of 3000 rpm and a thickness of 2 μm. The BCB is dried at a preset step-type curing temperature with a maximum temperature of 250°C.

[0018] (7) Use reactive ion etching (RIE) to etch the BCB on the table to expose the SiO 2 Passivation layer.

[0019] (8) Use the designed layout for photolithography, select ARN-4340 reverse glue as mask, and after photolithography, perform post-baking and use low-power oxygen plasma for glue application to ensure the steepness of the edge of the photolithography pattern. Use BOE solution to coat the SiO2 in the electrode hole. 2 Corrosion clean.

[0020] (9) The designed layout is used for the third photolithography, the inversion characteristics of AZ5214 are used for photolithography, and the Ti / AuP surface electrode is prepared by magnetron sputtering and lift-off process.

[0021] (10) The fourth photolithography was performed using the designed layout 4, and the N-side AuGeNi / Au electrode was prepared by magnetron sputtering and lift-off process. After sputtering the electrode, the chip needs to be subjected to rapid thermal annealing treatment at a temperature of 320°C for 35 seconds.

[0022] (11) A layer of hydrogen silsesquioxane HSQ is spin-coated on the substrate of the VCSEL, and electron beam direct writing is used for exposure to transfer the metasurface pattern to the HSQ. Subsequently, ICP etching is performed to form circular nanopillars and remove the residual HSQ resist.

[0023] It can be seen from the above technical solution that the present invention has the following beneficial effects:

[0024] 1. Integrating a metasurface on the substrate of a back-emitting VCSEL can effectively shorten the length of the optical path and achieve precise alignment, the alignment accuracy of which is unmatched by the manual alignment of traditional split beam splitters.

[0025] 2. The metasurface is integrated outside the VCSEL resonant cavity without affecting the laser's emission characteristics.

[0026] 3. Gallium arsenide nanorods have high energy conversion efficiency at a wavelength of 980nm, and the isotropic nature of the circular nanorods can maintain the original polarization state of the laser. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 In the figure, (a) is the corresponding relationship between the nanocolumn radius and the phase; (b) is the corresponding relationship between the nanocolumn radius and the transmittance.

[0028] Figure 2 Arrangement of a single superunit nanopillar.

[0029] Figure 3 Schematic diagram of the on-chip integrated power splitter structure. DETAILED DESCRIPTION

[0030] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in combination with specific implementation examples and with reference to the accompanying drawings.

[0031] A power beam splitter with an on-chip integrated metasurface. The design of the metasurface is different from the traditional metasurface design based on the generalized Snell's law. The energy regulation of different diffraction orders is achieved by removing the total phase gradient restriction of 2π. The phase profile function of the metasurface is determined by formula (1):

[0032]

[0033] where θ t , n t Represent the projection angle and the refractive index of the projection medium, θ and n represent the incident angle and the refractive index of the incident medium, λ is the wavelength of the laser, △ is the super unit of the metasurface, and N is the function factor.

[0034] In this example, n t The refractive index of air is 1, θ is 0°, n is the refractive index of GaAs medium is 3.52, the laser wavelength is 980nm, the lattice constant of the superatom is 300nm, the height is 700nm, and 9 superatoms are selected to form a super unit of 2.7μm. Figure 1 (a) and (b) show the corresponding relationship between the radius, phase and transmittance of different meta-atoms. The phase of the meta-atom as a whole can cover 2π, and the average transmittance is above 80%. Figure 2 It shows supercells composed of superatoms of different radii. There are four rows from top to bottom, and the function factor N of each supercell is different.

[0035] Subsequently, the dielectric metasurface was successfully fabricated on the back-emitting VCSEL substrate using standard semiconductor planar processing technology. Figure 3 As shown, from bottom to top, they are: P-surface electrode 8, benzocyclobutene (BCB) 7, P-surface distributed Bragg reflector 6, oxide hole 5, N-surface distributed Bragg reflector 4, GaAs substrate 3, N-surface electrode 2, metasurface 1. The light emitted from the active region passes through the metasurface on the VCSEL substrate and is divided into two beams, which are projected on the 0, -1 order or -1, -2 order respectively, and the energy ratio of adjacent orders can be adjusted.

[0036] In an exemplary embodiment of the present invention, a structural design of a chip-integrated power beam splitter is disclosed, a back-emitting VCSEL is prepared using a standard semiconductor planar process, and a cylindrical nanostructure is processed on its substrate. After the laser emitted from the active region passes through the metasurface, the beam will be projected onto adjacent 0, -1 or -1, -2 diffraction orders, and the energy ratio of adjacent diffraction orders is tunable. The specific process steps are as follows:

[0037] (12) A 500 nm thick silicon dioxide (SiO2) etch barrier layer is grown on the P-side of the epitaxial wafer using plasma-enhanced chemical vapor deposition (PECVD) at a growth rate of 15 Å / s.

[0038] (13) The designed layout was used for photolithography. The selected photoresist was AZ5214. At 4000 rpm, its spin coating thickness was about 1.4 μm, which was more suitable for the preparation of the device. After the photolithography, the photoresist was cured and the SiO2 outside the truncated cone was realized by wet etching. 2 The etching solution used was BOE solution with an etching rate of 50nm / s. 2 The epitaxial wafer with the mask is cleaned and dried using the above-mentioned pretreatment cleaning method. The uncovered SiO 2 The P-side DBR layer is etched, and the etching depth is the depth from the P-side surface to the peroxide restriction layer, which is greater than 4.8μm and less than 7μm. A step meter is used to confirm whether the etching reaches the predetermined depth.

[0039] (14) Clean the epitaxial wafer after ICP etching, use BOE solution to etch and remove the SiO2 mask layer, and use a step profiler to confirm whether its thickness meets the standard

[0040] (15) The device was oxidized using a wet oxidation process, where nitrogen gas was passed through a 100°C constant temperature water area into a constant temperature chamber set at 400°C at a flow rate of 1 sccm / min. The oxidation rate of the back-emitting VCSEL epitaxial structure we used was approximately 0.97 μm / min.

[0041] (16) The oxidized laser epitaxial wafer was cleaned again and dried according to the above method, and a layer of SiO with a thickness of 500 nm was grown on the epitaxial wafer using PECVD. 2 Passivation layer to achieve the purpose of electrical insulation of the device sidewalls.

[0042] (17) The device surface is planarized and BCB is spin-coated at a spin coating parameter of 3000 rpm and a thickness of about 2 μm. The BCB is dried at a preset step-type curing temperature with a maximum temperature of 250°C.

[0043] (18) Reactive ion etching (RIE) is used to etch the BCB on the mesa to expose the SiO2 passivation layer.

[0044] (19) The designed layout was used for photolithography, and ARN-4340 reverse glue was selected as a mask. After photolithography, post-baking was performed and low-power oxygen plasma was used for glue coating to ensure the steepness of the edges of the photolithography pattern. BOE solution was used to coat the SiO2 in the electrode holes. 2 Corrosion clean.

[0045] (20) The designed layout was used for the third photolithography, and the inversion characteristics of AZ5214 were used for photolithography. The Ti / Au (50 nm / 300 nm) P-side electrode was prepared using magnetron sputtering and lift-off process.

[0046] (21) The fourth photolithography was performed using the designed layout 4, and the N-side AuGeNi / Au (15nm / 300nm) electrode was prepared by magnetron sputtering and lift-off process. After sputtering the electrode, the chip needs to be subjected to rapid thermal annealing treatment at a temperature of 320°C for 35 seconds.

[0047] (22) A layer of hydrogen silsequioxane (HSQ) is spin-coated on the substrate of the VCSEL, and electron beam direct writing is used for exposure to transfer the metasurface pattern to the HSQ. Subsequently, ICP etching is performed to form circular nanopillars and remove the residual HSQ resist.

[0048] Example

[0049] A power beam splitter with an on-chip integrated metasurface. The dielectric metasurface is directly processed on the back-emitting VCSEL substrate through a semiconductor planarization process. Since the metasurface is directly prepared outside the resonant cavity, it does not damage the performance of the laser. The meta-atoms in the dielectric metasurface can effectively control the wavefront of the emitted laser without affecting the polarization characteristics of the emitted laser, thereby realizing the function of power beam splitting.

[0050] Breaking the 2π phase limitation of traditional metasurface structures, incomplete phase gradients are used to design metasurfaces to achieve the purpose of energy regulation of adjacent diffraction orders.

[0051] Gallium arsenide nanocylinders of different diameters are used for phase control. The high refractive index and high transmittance of gallium arsenide materials are very suitable for laser beam shaping. The isotropy of circular nanocylinders does not change the original polarization state of the laser beam.

[0052] The reflectivity of the bottom Bragg reflector is smaller than that of the top Bragg reflector, so the laser beam can be bottom-emitted and the 3-micron diameter of the oxidation hole ensures the fundamental mode emission of the laser.

[0053] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A power beam splitter with an on-chip integrated metasurface, characterized in that: A dielectric metasurface was successfully prepared on the back-emitting VCSEL substrate surface using standard semiconductor planar processing technology; the power beam splitter is composed of: P-surface electrode 8, benzocyclobutene (BCB) 7, P-surface distributed Bragg reflector 6, oxide hole 5, N-surface distributed Bragg reflector 4, gallium arsenide substrate 3, N-surface electrode 2, metasurface 1; the light emitted from the active area is divided into two beams after passing through the metasurface on the VCSEL substrate, and is projected onto the 0, -1 order or -1, -2 order respectively, and the energy ratio of adjacent orders is tunable.

2. The on-chip integrated metasurface power beam splitter according to claim 1, characterized in that: By removing the 2π total phase gradient limitation, energy regulation of different diffraction orders can be achieved.

3. The on-chip integrated metasurface power beam splitter according to claim 1, characterized in that: The phase profile function of the metasurface is determined by formula (1): where θ t , n t represent the projection angle and the refractive index of the projection medium respectively, θ and n represent the incident angle and the refractive index of the incident medium respectively; λ is the wavelength of the laser, △ is the super unit of the metasurface, and N is the function factor.

4. The on-chip integrated metasurface power beam splitter according to claim 1, characterized in that: When the projection medium is air, n t is 1, θ is 0°, n is the refractive index of GaAs medium is 3.52, the laser wavelength is 980nm, the lattice constant of the superatom is 300nm, the height is 700nm, and 9 superatoms are selected to form a super unit of 2.7μm; The phase coverage of the meta-atom as a whole is 2π, and the average transmittance is above 80%.

5. The on-chip integrated metasurface power beam splitter according to claim 1, characterized in that: The back-emitting VCSEL is prepared by using standard semiconductor planar process and cylindrical nanostructures are processed on its substrate. After the laser emitted from the active area passes through the metasurface, the beam will be projected onto adjacent 0, -1 or -1, -2 diffraction orders, and the energy ratio of adjacent diffraction orders is tunable. The specific process steps are as follows: (1) using plasma enhanced chemical vapor deposition (PECVD) to grow a 500 nm thick silicon dioxide (SiO2) etching barrier layer on the P surface of the epitaxial wafer, with a growth rate of SiO2 of 15 angstroms per second; (2) using the designed layout for photolithography, the selected photoresist is AZ5214, and the spin coating thickness is 1.4 μm at 4000 rpm; after curing the photoresist after photolithography, the SiO2 outside the frustum is removed by wet etching, and the etching liquid used is BOE solution with an etching rate of 50 nm / s; the epitaxial wafer with the large-table SiO2 mask is cleaned and dried by a pretreatment cleaning method; The P-side DBR layer not covered with SiO2 is etched by inductively coupled plasma etching ICP. The etching depth is the depth from the P-side surface to the peroxide restriction layer. The depth is greater than 4.8 μm and less than 7 μm. A step profiler is used to confirm whether the etching reaches the predetermined depth. (3) Clean the epitaxial wafer after ICP etching, use BOE solution to etch and remove the SiO2 mask layer, and use a step profiler to confirm whether its thickness meets the standard; (4) The device was oxidized by a wet oxidation process, where nitrogen gas was passed through a 100°C constant temperature water area into a constant temperature chamber set at 400°C at a flow rate of 1 sccm / min; the oxidation rate of the back-emitting VCSEL epitaxial structure used was 0.97 μm / min; (5) The oxidized laser epitaxial wafer is cleaned again and dried, and a 500 nm thick SiO2 passivation layer is grown on the epitaxial wafer using PECVD to achieve the purpose of sidewall electrical insulation; (6) The surface was planarized and BCB was spin-coated at a spin coating parameter of 3000 rpm and a thickness of 2 μm. The BCB was dried at a preset step-type curing temperature with a maximum temperature of 250° C. (7) using reactive ion etching (RIE) technology to etch the BCB on the table to expose the SiO2 passivation layer; (8) Using the designed layout for photolithography, ARN-4340 reverse glue is selected as a mask. After photolithography, post-baking is performed and low-power oxygen plasma is used for glue application to ensure the steepness of the edge of the photolithography pattern; BOE solution is used to etch away SiO2 in the electrode hole; (9) Using the designed layout to perform the third photolithography, using the inversion characteristics of AZ5214 for photolithography, and using magnetron sputtering and lift-off process to form Ti / AuP surface electrode preparation; (10) The fourth photolithography was performed using the designed layout 4, and the N-side AuGeNi / Au electrode was prepared by magnetron sputtering and lift-off process; after sputtering the electrode, the chip was subjected to rapid thermal annealing treatment at a temperature of 320°C for 35 seconds; (11) A layer of hydrogen silsesquioxane (HSQ) is spin-coated on the substrate of the VCSEL, and electron beam direct writing is used for exposure to transfer the metasurface pattern to the HSQ. Subsequently, ICP etching is performed to form circular nanocolumns and remove the residual HSQ resist.

6. The on-chip integrated metasurface power beam splitter according to claim 1, characterized in that: The dielectric metasurface is directly processed on the back-emitting VCSEL substrate through a semiconductor planarization process. The metasurface is directly prepared outside the resonant cavity without destroying the performance of the laser. The metaatoms in the dielectric metasurface effectively control the wavefront of the emitted laser without affecting the polarization characteristics of the emitted laser, thereby realizing the function of power splitting.

7. The on-chip integrated metasurface power beam splitter according to claim 1, characterized in that: Breaking the 2π phase limitation of the metasurface structure, using incomplete phase gradient to design the metasurface to achieve energy regulation of adjacent diffraction orders.

8. The on-chip integrated metasurface power beam splitter according to claim 1, characterized in that: Gallium arsenide nanocylinders of different diameters are used for phase control. The high refractive index and high transmittance of gallium arsenide materials are very suitable for laser beam shaping. The isotropy of circular nanocylinders does not change the original polarization state of the laser beam.

9. The on-chip integrated metasurface power beam splitter according to claim 1, characterized in that: The reflectivity of the Bragg reflector at the bottom of the back-emitting VCSEL is lower than that of the Bragg reflector at the top, so the laser beam can be bottom-emitted and the 3-micron oxidation hole diameter ensures the fundamental mode emission of the laser.

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