LDO circuit with dynamic load compensation

Abstract

The invention discloses an LDO (Low Dropout Regulator) circuit with a dynamic load compensation function, which relates to the technical field of power management, and is characterized by comprising an error amplifier, a power tube M1, a feedback circuit and a dynamic load compensation circuit, the power tube M1 is a P-type field effect transistor; the feedback circuit detects the output voltage and feeds the output voltage back to the error amplifier; and the dynamic load compensation circuit is connected with the drain electrode of the power tube M1 and is used for sensing the change of the output voltage VOUT and adjusting the driving current I0 output by the drain electrode of the power tube M1 according to the change of the output voltage VOUT. According to the LDO circuit, the output current of the power tube is dynamically adjusted through the dynamic load compensation circuit, then the output voltage is adjusted, the dynamic load compensation circuit during transient response simulation can effectively reduce the response recovery time of the output voltage during transient change of the current load, and therefore the LDO circuit can stably and efficiently operate.

Description

Technical Field

[0001] The present invention relates to the technical field of power management, and more particularly to an LDO circuit with dynamic load compensation. Background Art

[0002] In modern electronic systems, stable and high-quality power supply is essential for the normal operation of various circuits. As a commonly used power management chip, low-dropout linear regulator (LDO) is widely used in many fields, such as mobile devices, communication equipment, microprocessors in consumer electronics, analog circuits, and RF circuits.

[0003] With the continuous enhancement of electronic equipment functions and continuous improvement of performance, circuits have put forward higher requirements for the transient response performance of power supplies. Traditional LDO circuits have obvious shortcomings when facing rapid changes in load current. When the load current suddenly increases, due to the inherent characteristics of the internal circuit of the LDO, the output voltage often has a large undershoot. This is because at the moment of load current transient, the power transmission capacity of the LDO cannot match the new load requirements in time, causing the output voltage to drop instantly. For example, when the mobile phone processor switches instantly from low-power mode to high-load operation mode, the traditional LDO power supply may cause the processor's power supply voltage to drop instantly, thereby affecting the performance of the processor, and may even cause the system to temporarily freeze or erroneous operation.

[0004] On the contrary, when the load current decreases sharply, the output voltage is prone to overshoot. This voltage instability can damage sensitive electronic components and affect the reliability and life of the circuit. In some high-precision analog circuits or RF circuits, even a small voltage fluctuation may cause signal distortion, increased noise and other problems, seriously affecting the performance of the entire system.

[0005] In addition, the compensation circuit design of traditional LDO is usually based on specific load conditions and frequency ranges, and has poor adaptability to complex and changeable practical application scenarios. When the load current changes rapidly, its compensation mechanism cannot be adjusted quickly and effectively, further exacerbating the transient response problem. Moreover, as electronic devices move towards miniaturization and low power consumption, LDO circuits need to solve transient response problems without increasing excessive power consumption and chip area to meet the stringent requirements of increasingly complex electronic systems for power stability. In the operation of modern electronic devices, a stable power supply is essential. Low-dropout linear regulators (LDOs) came into being and play a key role in the field of power management. Summary of the invention

[0006] The purpose of the present invention is to provide an LDO circuit with dynamic load compensation to solve the problems of insufficient transient response performance, output voltage fluctuation, and limitation of compensation circuit design in the prior art.

[0007] The above technical objectives of the present invention are achieved through the following technical solutions: an LDO circuit with dynamic load compensation, comprising an error amplifier, a power tube M1, a feedback circuit and a dynamic load compensation circuit;

[0008] The power tube M1 is a P-type field effect transistor; the feedback circuit detects the output voltage and feeds the output voltage back to the error amplifier; the dynamic load compensation circuit is connected to the drain of the power tube M1, and is used to sense the change of the output voltage VOUT, and adjust the drive current I0 output by the drain of the power tube M1 according to the change of the output voltage VOUT, so as to increase the change speed of the output voltage VOUT.

[0009] The present invention is further configured as follows: the dynamic load compensation circuit includes an induction circuit and a preloading circuit;

[0010] The induction circuit is used to sense the current of the power tube M1;

[0011] The preloading circuit forms a preloading current according to the sensed current of the power tube M1 , and adjusts the preloading current according to the change of the output voltage VOUT, thereby adjusting the driving current.

[0012] The present invention is further configured as follows: the sensing circuit includes a power tube M2, the power tube M2 is a P-type field effect transistor, the gate of the power tube M2 is connected to the gate of the power tube M1, and the channel lengths of the power tubes M1 and M2 are the same, which is L; and the width W of the power tube M1 is K1 times the width W of the power tube M2, the width-to-length ratio of the NMOS tube M6 is K2 times the width-to-length ratio of the NMOS tube M5, and the width-to-length ratio of the NMOS tube M4 is K3 times the width-to-length ratio of the NMOS tube M3, wherein K1, K2, and K3>10, the source of the power tube M2 is used to input the power supply voltage VDD, and the drain of the power tube M2 is connected to the preloading circuit.

[0013] The present invention is further configured as follows: the preloading circuit includes NMOS tubes M3, M4, M5, M6 and capacitor C1, wherein:

[0014] The drain of the NMOS tube M5 is connected to the drain of the power tube M2, and the source of the NMOS tube M5 is connected to the drain of the NMOS tube M3;

[0015] The drain of the NMOS tube M6 is connected to the drain of the power tube M1, the source of the NMOS tube M6 is connected to the drain of the NMOS tube M4, and the gate of the NMOS tube M6 is connected to the gate of the NMOS tube M5, wherein the gate of the NMOS tube M6 and the gate of the NMOS tube M5 are connected to the VB point, which is the bias control point.

[0016] The present invention is further configured such that when the load Loading decreases, the output voltage VOUT increases, whereby the voltage difference is coupled to the gates of the NMOS tubes M3 and M4 via the capacitor C1, so that the gate voltage of the NMOS tube M4 increases, and the current flowing through the NMOS tube M4 increases, thereby reducing the output voltage VOUT.

[0017] The present invention is further configured such that when the load Loading increases, the output voltage VOUT decreases, whereby the voltage difference is coupled to the gates of the NMOS tubes M3 and M4 via the capacitor C1, so that the gate voltage of the NMOS tube M4 decreases and the current flowing through the NMOS tube M4 decreases, thereby increasing the output voltage VOUT.

[0018] Another object of the present invention is to provide an electronic device using the above-mentioned dynamic load compensation LDO circuit, wherein the electronic device includes at least a microprocessor, an analog circuit or a radio frequency circuit, and the LDO circuit provides a stable power supply for the electronic device.

[0019] By adopting the above technical solution, the LDO circuit of the present invention can accurately sense and respond to small changes in the output voltage VOUT through a dynamic load compensation circuit. This precise voltage regulation capability is essential for maintaining the stable operation of sensitive circuits in electronic devices, especially in applications that are extremely sensitive to voltage fluctuations, such as high-precision analog circuits and radio frequency circuits. The present invention can significantly reduce signal distortion and noise and improve overall system performance by reducing voltage fluctuations. When the load current changes rapidly, such as when the processor switches from a low-power mode to a high-load operating mode, the LDO circuit of the present invention can quickly adjust the output voltage to reduce voltage undershoot or overshoot. This fast transient response capability is essential for ensuring the stability and reliability of high-performance electronic devices when the load changes suddenly, and can avoid system freezes or erroneous operations caused by voltage transients.

[0020] Compared with the traditional LDO, the dynamic load compensation circuit of the present invention is not limited to specific load conditions and frequency ranges, but can adapt to complex and changeable practical application scenarios. This wide adaptability enables the LDO circuit to provide stable power output under different working conditions, enhancing the versatility and flexibility of the circuit. The present invention solves the transient response problem without increasing excessive power consumption and chip area. This is a significant advantage for mobile devices and other electronic devices that have strict requirements on power consumption and space. By optimizing the circuit design, it is possible to extend battery life and reduce device size while maintaining high performance.

[0021] The present invention reduces the damage to sensitive electronic components caused by output voltage fluctuations, and the LDO circuit of the present invention helps to extend the service life of the circuit. This improvement in reliability is particularly important in applications that require long-term stable operation, such as industrial control systems and medical equipment. The LDO circuit of the present invention can respond to load changes in real time and maintain a stable output voltage by dynamically adjusting the load current.

[0022] In summary, the present invention has the following beneficial effects:

[0023] 1. The LDO circuit of the present invention can monitor and respond to changes in load current in real time by integrating a dynamic load compensation function. This ability to dynamically adjust the load current significantly reduces voltage fluctuations caused by changes in load current, thereby ensuring the stability of the output voltage. In particular, when the load current undergoes transient changes, the present invention can quickly restore the output voltage to a stable state, reducing the time for the voltage recovery response, thereby improving the stability and reliability of the circuit. This is particularly important for high-performance electronic devices, as they often need to quickly switch between different operating modes without sacrificing the stability of the power supply.

[0024] 2. The present invention takes into full consideration the trend of miniaturization and low power consumption of electronic devices in design. By optimizing the circuit design, the present invention effectively solves the transient response problem without increasing excessive power consumption and chip area. This design not only helps to reduce the energy consumption of electronic devices, but also allows the LDO circuit to be integrated into a more compact space, meeting the strict requirements of modern electronic devices for size and energy consumption.

[0025] 3. The present invention reduces the risk of damage to these components due to voltage stress by reducing the fluctuation of the output voltage, thereby extending the service life of the circuit. This is especially important for electronic devices that need to operate stably for a long time, such as servers, industrial control systems and medical equipment, which have extremely high requirements for power supply stability and strict standards for the reliability and life of the equipment.

[0026] 4. The LDO circuit of the present invention not only improves the efficiency of power management by reducing voltage fluctuations, but also reduces damage to sensitive electronic components, thereby improving the performance of the entire electronic system. In high-precision analog circuits or radio frequency circuits, even small voltage fluctuations may cause signal distortion or increased noise. The present invention reduces these problems by maintaining a stable output voltage, improving the quality of the signal and the overall performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a circuit diagram of a dynamic load compensation LDO in Embodiment 1 of the present invention;

[0028] Figure 2is a detailed LDO circuit diagram with a dynamic load compensation circuit in Embodiment 1 of the present invention;

[0029] Figure 3 This is a circuit diagram of an alternative solution of the LDO with dynamic load compensation in Embodiment 2 of the present invention. DETAILED DESCRIPTION

[0030] The following is combined with Figure 1-3 The present invention is described in further detail.

[0031] Embodiment 1: An LDO circuit with dynamic load compensation, as shown in the attached Figure 1 The circuit shown includes an error amplifier, a power tube M1, a feedback circuit and a dynamic load compensation circuit, wherein the power tube M1 is a P-type field effect transistor.

[0032] In the dynamic load compensation LDO circuit of the present invention, the feedback network is responsible for real-time monitoring of the output voltage VOUT of the circuit and accurately feeding it back to the error amplifier. After receiving the feedback signal, the error amplifier will compare it with a preset reference voltage VREF. The reference voltage VREF is a stable reference value that represents the ideal output voltage level. The error amplifier amplifies the error signal between the output voltage from the resistor feedback network and the constant input voltage provided by the bandgap reference. The error signal directly controls the on-voltage of the power tube M1. If the output voltage VOUT deviates from the reference voltage VREF, the error signal will adjust the on-voltage of the power tube M1 to fine-tune the output voltage to return it to the ideal reference level. This process forms a negative feedback regulation loop to keep the ratio between the output voltage and the input reference voltage unchanged, ensuring the stability of the output voltage VOUT.

[0033] The calculation of the output voltage VOUT is relatively simple: it is equal to the input voltage VDD minus the conduction voltage of the power tube M1. Therefore, by accurately controlling the conduction voltage of the power tube M1, the output voltage VOUT of the LDO can be effectively controlled. In the entire negative feedback regulation loop, the two input voltages of the error amplifier: the acquisition voltage VFB (i.e. the feedback output voltage) and the reference voltage VREF must remain the same. Through analysis, it can be seen that the output voltage is determined by the resistance ratio of the two resistors (R1 and R2), and the output voltage is:

[0034]

[0035] Among them, the negative input terminal (-) of the error amplifier is used to input the reference voltage VREF; the gate of the power tube M1 is connected to the output terminal VG of the error amplifier, the source of the power tube M1 is used to input the power supply voltage VDD, the drain of the power tube M1 is connected to the load Loading, and the load Loading is driven by the output voltage VOUT; the feedback circuit is connected to the drain of the power tube M1 and the positive input terminal (+) of the error amplifier.

[0036] Ideally, the LDO output voltage VOUT should be proportional to the load current I load However, in actual situations, the output voltage will be affected by the load current due to the equivalent resistance Ron of the power tube M1. The relationship between the output voltage and the load current can be expressed by the following formula:

[0037] VOUT = V IN -I load ·R on

[0038] Where V IN is the input voltage, I load is the load current; Ron is the equivalent series resistance of the power tube M1.

[0039] The equivalent resistance Ron of the power tube M1 will affect the output voltage, especially when the load current changes:

[0040]

[0041] μ p is the hole mobility, C OX is the oxide capacitance per unit area, is the width-to-length ratio of the power tube M1, V gate1 is the gate voltage of power tube M1, V th is the threshold voltage of the power tube M1.

[0042] In a low-dropout linear regulator (LDO) circuit, the impact of load current fluctuations on output voltage stability is a key issue. When the load current increases, the output voltage VOUT will drop due to the limited on-resistance Ron of the power tube M1, and this phenomenon is particularly evident under high load conditions. In order to effectively reduce the impact of load current changes on the output voltage, the present invention proposes a dynamic load compensation circuit, which is directly connected to the drain of the power tube M1, and its main function is to monitor the slight changes in the output voltage VOUT in real time. Once the fluctuation of the output voltage is detected, the dynamic load compensation circuit will respond quickly and compensate for the change in load current by adjusting the drive current I0 output by the drain of the power tube M1. This adjustment can increase the speed of change of the output voltage VOUT, thereby quickly stabilizing the output voltage and reducing voltage fluctuations. In this way, the dynamic load compensation circuit can effectively offset the output voltage drop caused by the load current change and maintain the stability and reliability of the power supply output. This design not only improves the performance of the LDO circuit, but also ensures that the electronic equipment can maintain a stable power supply when facing load changes, which is of great significance for improving the stability of the entire system and extending the life of the equipment.

[0043] The above dynamic load compensation circuit includes a sensing circuit and a preloading circuit, as shown in the attached Figure 2 The sensing circuit is used to sense the current of the power tube M1. The preloading circuit forms a preloading current according to the sensed current of the power tube M1, and adjusts the preloading current according to the change of the output voltage VOUT, thereby adjusting the driving current to increase the change speed of the output voltage VOUT.

[0044] In the dynamic load compensation LDO circuit of the present invention, the key component of the sensing circuit is the power tube M2, which is a P-type field effect transistor (PMOS). The gate of the power tube M2 is connected to the gate of the power tube M1, which means that they have the same voltage signal, so that the power tube M2 can sense the current change through the power tube M1. The source of the power tube M2 receives the input power supply voltage VDD, and its drain is connected to the preloading circuit, and the power tube M2 transmits the sensed current change to the preloading circuit.

[0045] The preload circuit is composed of N-type field effect transistors (NMOS) M3, M4, M5, M6 and capacitor C1. The drain of NMOS tube M5 is directly connected to the drain of power tube M2, and its source is connected to the drain of NMOS tube M3, forming a current transfer path. The drain of NMOS tube M6 is connected to the drain of power tube M1 to sense the actual load current, its source is connected to the drain of NMOS tube M4, and the gate is connected to the gate of NMOS tube M5. This configuration means that the gate voltage of M6 will change with the gate voltage of M5. The gate of NMOS tube M6 and the gate of NMOS tube M5 are both connected to the VB point, which is a bias control point used to adjust the gate voltage of M5 and M6, thereby accurately controlling the induced current.

[0046] With this design, when the current of power tube M1 changes, power tube M2 can sense these changes and transmit these changes through NMOS tubes M3 and M4 in the preload circuit. Since the gates of M5 and M6 are connected, the current transfer ratio between them can be precisely controlled by the bias voltage at the VB point, which enables M2 to sense the current of M1 more accurately. This precise sensing capability is crucial for dynamic load compensation circuits because it is necessary to ensure that the circuit can respond quickly when the load changes and adjust the output voltage VOUT accordingly to maintain power supply stability.

[0047] NMOS tubes M3 and M4 form a current mirror, which is used to replicate the inductive current of power tube M2, thereby realizing dynamic adjustment of load current. When the load current decreases, the output voltage VOUT will increase, and capacitor C1 will couple this voltage difference to the gates of NMOS tubes M3 and M4, causing the gate voltage of M4 to increase, thereby increasing the current flowing through M4 to reduce the output voltage VOUT. Conversely, when the load current increases, the output voltage VOUT will decrease, and capacitor C1 will couple this voltage difference to the gates of NMOS tubes M3 and M4, causing the gate voltage of M4 to decrease, reducing the current flowing through M4 to increase the output voltage VOUT. This mechanism enables the LDO circuit to automatically adjust to adapt to changes in load and maintain voltage stability.

[0048] During operation, since the gates of the power tubes M1 and M2 are connected, and the sources of the power tubes M1 and M2 are connected to the power supply voltage VDD, the power tube M2 can sense the current of the power tube M1. The channel lengths of the power tubes M1 and M2 are the same, which is L, and the width of the power tube M1 is K1 times that of the power tube M2 (K1>10). The same length of L enables the induced current to accurately replicate the power tube M2, so that the current I of the power tube M1 M1 I is the current of power tube M2 M2 K1 times, that is

[0049] I M1 =I M2 K1

[0050] The current I on the power tube M2 M2 Flows to NMOS tube M5 so that the current on M5 is also I M2 Right now

[0051] I M5 =I M2 =I M1 / K1

[0052] The gates of NMOS tubes M5 and M6 are controlled by the bias control point VB. The width-to-length ratio of NMOS tube M6 is K2 (K2>10) times that of NMOS tube M5, that is, the current of NMOS tube M6 is:

[0053] I M6 =K2·I M5

[0054] The current I on the NMOS tube M5 M5 flows to the NMOS tube M3, making the current I M3 =I M5 =I M2 =I M1 / K1

[0055] Because the width-to-length ratio of the NMOS tube M4 is K3 times that of the NMOS tube M3 (K3>10), the current is converted into a preloaded load current by the NMOS tubes M3 and M4 according to the width-to-length ratio. That is, the NMOS tube M4 mirrors the current of the NMOS tube M3, so that the current of the NMOS tube M4 is K3 times the current of the NMOS tube M3, which is equal to:

[0056] I M4 =I M3 K3

[0057] In the dynamic load compensation LDO circuit of the present invention, capacitor C1 plays a crucial role. It quickly adjusts the gate voltage of NMOS tubes M3 and M4 by coupling the change of output voltage VOUT, thereby achieving a rapid response to load changes. When the load Loading decreases, that is, the load current in the circuit decreases, this will cause the output voltage VOUT to increase relatively. At this time, capacitor C1 senses this voltage change and couples this change to the gates of NMOS tubes M3 and M4. Since the gate voltage of M4 increases accordingly, the current flowing through NMOS tube M4 increases accordingly. This increased current appears as an additional load on the output voltage VOUT, effectively absorbing excessive energy, thereby helping to reduce the excessively high output voltage VOUT and achieving a rapid response to stabilize the voltage.

[0058] On the contrary, when the load increases, that is, when the load current in the circuit increases, the output voltage VOUT will decrease relatively. Similarly, capacitor C1 senses this change and couples the voltage difference to the gates of NMOS tubes M3 and M4. At this time, the gate voltage of NMOS tube M4 decreases, resulting in a decrease in the current flowing through M4. This reduced current appears as a reduced load on the output voltage VOUT, thereby providing the necessary energy supplement to help increase the reduced output voltage VOUT, and once again achieve a fast response to stabilize the voltage. Capacitor C1 is used to couple changes in the output voltage and accelerate the response to load changes:

[0059] T=Rgate3,4·C1

[0060] Where R gate3,4 is the gate resistance of NMOS tubes M3 and M4, and T is the time constant. The time constant τ determines the speed at which the capacitor responds to load changes.

[0061] Through the above method, the load current can be adjusted accordingly according to the change of the output drive voltage. On the one hand, when the load voltage changes, real-time response can be performed to increase or decrease the load current to avoid affecting the performance of the load. On the other hand, since the load current is changed in real time according to the change of the induced voltage, the change speed of the drive voltage is further improved to achieve rapid response.

[0062] Embodiment 2: The MOS tube mentioned in Embodiment 1 of the present invention can also be a triode transistor, and its specific circuit diagram is shown in the attached Figure 3 As shown, Q1 and Q2 are PNP type triode transistors, Q3, Q4, Q5, Q6 are NPN type triode transistors, and their working principles are similar to those described in Example 1.

[0063] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. An LDO circuit with dynamic load compensation, characterized in that: It includes an error amplifier, a power tube M1, a feedback circuit and a dynamic load compensation circuit; The power tube M1 is a P-type field effect transistor; the feedback circuit detects the output voltage and feeds the output voltage back to the error amplifier; the dynamic load compensation circuit is connected to the drain of the power tube M1 to sense the change of the output voltage VOUT and adjust the drive current I0 output by the drain of the power tube M1 according to the change of the output voltage VOUT.

2. The LDO circuit according to claim 1, characterized in that: The dynamic load compensation circuit includes an induction circuit and a preloading circuit; The induction circuit is used to sense the current of the power tube M1; The preloading circuit forms a preloading current according to the sensed current of the power tube M1 , and adjusts the preloading current according to the change of the output voltage VOUT, thereby adjusting the driving current.

3. The LDO circuit according to claim 2, characterized in that: The sensing circuit includes a power tube M2, which is a P-type field effect transistor. The gate of the power tube M2 is connected to the gate of the power tube M1, and the channel lengths of the power tubes M1 and M2 are the same, which is L; and the width W of the power tube M1 is K1 times the width W of the power tube M2, the width-to-length ratio of the NMOS tube M6 is K2 times the width-to-length ratio of the NMOS tube M5, and the width-to-length ratio of the NMOS tube M4 is K3 times the width-to-length ratio of the NMOS tube M3, wherein K1, K2, and K3>10, the source of the power tube M2 is used to input the power supply voltage VDD, and the drain of the power tube M2 is connected to the preloading circuit.

4. The LDO circuit according to claim 2, characterized in that: The preloading circuit includes NMOS tubes M3, M4, M5, M6 and capacitor C1, wherein: The drain of the NMOS tube M5 is connected to the drain of the power tube M2, and the source of the NMOS tube M5 is connected to the drain of the NMOS tube M3; The drain of the NMOS tube M6 is connected to the drain of the power tube M1, the source of the NMOS tube M6 is connected to the drain of the NMOS tube M4, and the gate of the NMOS tube M6 is connected to the gate of the NMOS tube M5, wherein the gate of the NMOS tube M6 and the gate of the NMOS tube M5 are connected to the VB point, which is the bias control point.

5. The LDO circuit according to claim 4 is characterized in that: When the load Loading decreases, the output voltage VOUT increases, and thus the voltage difference is coupled to the gates of the NMOS tubes M3 and M4 via the capacitor C1, so that the gate voltage of the NMOS tube M4 increases, and the current flowing through the NMOS tube M4 increases, so as to reduce the output voltage VOUT.

6. The LDO circuit according to claim 4 is characterized in that: When the load Loading increases, the output voltage VOUT decreases, and thus the voltage difference is coupled to the gates of the NMOS tubes M3 and M4 via the capacitor C1, so that the gate voltage of the NMOS tube M4 decreases and the current flowing through the NMOS tube M4 decreases, thereby increasing the output voltage VOUT.

7. An electronic device using the dynamic load compensation LDO circuit according to any one of claims 1 to 6, characterized in that: The electronic device at least includes a microprocessor, an analog circuit or a radio frequency circuit, and the LDO circuit provides a stable power supply for the electronic device.

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