Multi-dimensional tensor protocol calculation method and device, equipment, storage medium and product

Abstract

The embodiment of the invention discloses a multi-dimensional tensor protocol calculation method and device, equipment, a storage medium and a product. The method comprises the following steps: determining m reduction dimensions and (n-m) non-reduction dimensions of an n-dimensional tensor; a protocol calculation instruction is generated, K thread blocks are started on the artificial intelligence chip after the protocol calculation instruction is executed, and the K thread blocks conduct protocol calculation on m protocol dimensions in a parallel mode; the number of threads contained in each thread block is associated with the number of elements contained in m protocol dimensions, K is associated with the number of elements contained in (n-m) non-protocol dimensions, and each thread in each thread block reads respective protocol data in a parallel mode; the protocol calculation instruction is sent to the artificial intelligence chip, and the artificial intelligence chip executes the protocol calculation instruction. According to the method, protocol calculation can be carried out on any dimension of the multi-dimensional tensor, the universality is improved, the calculation time is shortened, and the calculation efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the field of intelligent computing technology, and more specifically, to a reduction calculation method, device, equipment, storage medium and product for multi-dimensional tensors. Background Art

[0002] With the booming development of artificial intelligence and high-performance computing, people's demand for computer computing power has also grown exponentially. At the same time, the growth rate of computing power has also greatly promoted the development of artificial intelligence and high-performance computing. In the field of artificial intelligence and high-performance computing, protocol computing is a commonly used computing mode, and the computing speed of protocol computing directly affects the overall computing power output of the system.

[0003] However, at present, it is necessary to develop separate calculation methods for tensors of different dimensions, which have many disadvantages such as poor versatility, long time consumption and high cost, and it is difficult to meet the current rapidly growing computing power needs. Summary of the invention

[0004] The present invention proposes a multi-dimensional tensor reduction calculation method, device, equipment, storage medium and product, which are applicable to various dimensions and help to improve versatility.

[0005] The technical solution of the embodiment of the present invention is as follows:

[0006] A method for calculating multidimensional tensor reduction, the method being applicable to a processor, the method comprising:

[0007] Determine m reduced dimensions and nm unreduced dimensions of an n-dimensional tensor, where m and n are positive integers at least 2, and m is less than or equal to n;

[0008] Generate a reduction calculation instruction, which starts K thread blocks on the artificial intelligence chip after being executed, and the K thread blocks perform reduction calculations on the K reduction calculation areas in the n-dimensional tensor corresponding to the K thread blocks in parallel on the m reduction dimensions; wherein the number of threads contained in each thread block is associated with the number of elements contained in the m reduction dimensions, the K is associated with the number of elements contained in the nm non-reduction dimensions, and each thread in each thread block reads its own reduction data from the reduction calculation area corresponding to the thread block in parallel;

[0009] The reduction computing instruction is sent to the artificial intelligence chip so that the artificial intelligence chip executes the reduction computing instruction, wherein the reduction computing result of the n-dimensional tensor is determined based on the K reduction computing results of the K thread blocks.

[0010] In one embodiment, it includes:

[0011] Determine a first step length of the n-dimensional tensor, a second step length of the m reduced dimensions, and a third step length of the nm unreduced dimensions;

[0012] Before sending the reduced calculation instruction to the artificial intelligence chip, the method includes:

[0013] The first step length, the second step length and the third step length are carried in the reduced calculation instruction.

[0014] In one embodiment, determining the first step length of the n-dimensional tensor includes: for each dimension from the second dimension to the n-th dimension in the n-dimensional tensor, based on the step length of the previous dimension of each dimension and the number of elements of the previous dimension, determining the step length of each dimension from the second dimension to the n-th dimension, wherein the step length of the first dimension in the n-dimensional tensor is 1; combining the step length of the first dimension in the n-dimensional tensor and the step length of each dimension from the second dimension to the n-th dimension in the n-dimensional tensor into the first step length;

[0015] The determining of the second step length of the m reduced dimensions comprises: for each dimension from the second dimension to the m-th dimension of the m reduced dimensions, based on the step length of the previous dimension of each dimension and the number of elements of the previous dimension, determining the step length of each dimension from the second dimension to the m-th dimension, wherein the step length of the first dimension of the m reduced dimensions is 1; combining the step length of the first dimension of the m reduced dimensions and the step length of each dimension from the second dimension to the m-th dimension into the second step length;

[0016] The determining of the third step size of the nm non-reduced dimensions includes: for each dimension from the second dimension to the nm-th dimension among the nm non-reduced dimensions, based on the step size of the previous dimension of each dimension and the number of elements of the previous dimension, determining the step size of each dimension from the second dimension to the nm-th dimension, wherein the step size of the first dimension among the nm non-reduced dimensions is 1; combining the step size of the first dimension among the nm non-reduced dimensions and the step size of each dimension from the second dimension to the nm-th dimension into the third step size.

[0017] In one embodiment, the number of threads included in each thread block is associated with the number of elements included in the m reduction dimensions, including: the number of threads included in each thread block is equal to the product of the number of elements included in each of the m reduction dimensions;

[0018] The K is associated with the number of elements included in the nm non-reduced dimensions, including: the K is equal to the product of the number of elements included in each of the nm non-reduced dimensions.

[0019] A multi-dimensional tensor reduction calculation method, the method is applicable to an artificial intelligence chip, the method comprising:

[0020] Receiving a reduction calculation instruction for an n-dimensional tensor, wherein the n-dimensional tensor includes m reduced dimensions and nm unreduced dimensions, wherein m and n are positive integers of at least 2, and m is less than or equal to n;

[0021] Execute the reduction calculation instruction to start K thread blocks, the K thread blocks perform reduction calculations on the K reduction calculation regions corresponding to the K thread blocks in the n-dimensional tensor in the m reduction dimensions in parallel; wherein the number of threads included in each thread block is associated with the number of elements included in the m reduction dimensions, the K is associated with the number of elements included in the nm non-reduction dimensions, and each thread in each thread block reads its own reduction data from the reduction calculation region corresponding to the thread block in parallel;

[0022] Based on the K reduced calculation results of the K thread blocks, a reduced calculation result of the n-dimensional tensor is determined.

[0023] In one embodiment, the reduction calculation instruction includes a first step length of the n-dimensional tensor, a second step length of the m reduced dimensions, and a third step length of the nm unreduced dimensions;

[0024] The K thread blocks performing reduction calculations on the K reduction calculation regions corresponding to the K thread blocks in the n-dimensional tensor in the m reduction dimensions in a parallel manner includes:

[0025] Determine, based on an identifier of each thread block in the K thread blocks and the third step length, a first coordinate of a reduced computing region of each thread block in a non-reduced dimension;

[0026] Determine, based on the identifier of each thread in each thread block and the second step length, a second coordinate of the reduced data of each thread in each thread block on the reduced dimension;

[0027] combining the first coordinate and the second coordinate to determine a third coordinate of the reduced data of each thread in each thread block in n dimensions;

[0028] Based on the third coordinate and the first step length, read the specification data of each thread in each thread block from the memory storing the n-dimensional tensor;

[0029] Based on the specification data of each thread in each thread block, a specification calculation result of each thread block is determined.

[0030] In one embodiment, the n-dimensional tensor is multimedia data containing n features, and the method includes:

[0031] Determining m reduced features from the n features;

[0032] The m reduction features are determined as the m reduction dimensions.

[0033] In one embodiment, at least one of the following is included:

[0034] Constructing training data based on the multimedia data that executes the reduced computing instructions, and training the artificial intelligence model based on the training data;

[0035] Constructing inference data based on the multimedia data that executes the reduced computing instructions, and inputting the inference data into a trained artificial intelligence model to obtain an inference result;

[0036] The multimedia data of the reduced computing instructions are visualized.

[0037] A multi-dimensional tensor reduction computing device, the device is suitable for a processor, and the device comprises:

[0038] A determination module, configured to determine m reduced dimensions and nm unreduced dimensions of an n-dimensional tensor, wherein m and n are positive integers of at least 2, and m is less than or equal to n;

[0039] A generation module, for generating a reduction calculation instruction, wherein after the reduction calculation instruction is executed, K thread blocks are started on the artificial intelligence chip, and the K thread blocks perform reduction calculations on the K reduction calculation areas corresponding to the K thread blocks in the n-dimensional tensor in the m reduction dimensions in parallel; wherein the number of threads contained in each thread block is associated with the number of elements contained in the m reduction dimensions, the K is associated with the number of elements contained in the nm non-reduction dimensions, and each thread in each thread block reads its own reduction data from the reduction calculation area corresponding to the thread block in parallel;

[0040] A sending module is used to send the reduction calculation instruction to the artificial intelligence chip so that the artificial intelligence chip executes the reduction calculation instruction, wherein the reduction calculation result of the n-dimensional tensor is determined based on the K reduction calculation results of the K thread blocks.

[0041] A multi-dimensional tensor reduction computing device, the device is suitable for an artificial intelligence chip, and the device comprises:

[0042] A receiving module, configured to receive a reduction calculation instruction for an n-dimensional tensor, wherein the n-dimensional tensor includes m reduced dimensions and nm unreduced dimensions, wherein m and n are positive integers of at least 2, and m is less than or equal to n;

[0043] An execution module, configured to execute the reduction calculation instruction to start K thread blocks, wherein the K thread blocks perform reduction calculations on the K reduction calculation regions corresponding to the K thread blocks in the n-dimensional tensor in the m reduction dimensions in parallel; wherein the number of threads included in each thread block is associated with the number of elements included in the m reduction dimensions, the K is associated with the number of elements included in the nm non-reduction dimensions, and each thread in each thread block reads its own reduction data from the reduction calculation region corresponding to the thread block in parallel;

[0044] A determination module is used to determine the reduced calculation result of the n-dimensional tensor based on the K reduced calculation results of the K thread blocks.

[0045] An electronic device, comprising:

[0046] Memory;

[0047] processor;

[0048] The memory stores an application program executable by the processor, which is used to enable the processor to execute any of the multi-dimensional tensor reduction calculation methods described above.

[0049] A computer-readable storage medium having computer-readable instructions stored thereon, wherein when the computer-readable instructions are executed by a processor, the processor executes any of the multi-dimensional tensor reduction calculation methods described above.

[0050] A program product includes a computer program, which, when executed by a processor, implements any of the multi-dimensional tensor reduction calculation methods described above.

[0051] It can be seen from the above technical scheme that in the implementation of the present invention, m reduced dimensions and nm non-reduced dimensions of the n-dimensional tensor are determined; a reduction calculation instruction is generated, and after the reduction calculation instruction is executed, K thread blocks are started on the artificial intelligence chip, and the K thread blocks perform reduction calculations on the K reduced calculation areas in parallel on the m reduced dimensions; the number of threads contained in each thread block is associated with the number of elements contained in the m reduced dimensions, and K is associated with the number of elements contained in the nm non-reduced dimensions, and each thread in each thread block reads its own reduced data in parallel; the reduction calculation instruction is sent to the artificial intelligence chip, and the artificial intelligence chip executes the reduction calculation instruction. It can be seen that any number of reduced dimensions in a multidimensional tensor containing any number of dimensions can be reduced. There is no need to design a special reduction algorithm for each specific dimension of the tensor, which improves versatility. Moreover, the implementation of the present invention does not require preprocessing of the tensor (such as scaling, normalization, padding and sparseness, etc.), which saves calculation time and improves calculation efficiency. In addition, based on the numerical first step length, second step length, and third step length, each thread in each thread block can accurately access its own reduced data, which facilitates the K thread blocks to perform reduced calculations in parallel, further improving the calculation efficiency. In addition, the embodiments of the present invention can be applied to various data such as multimedia data and various scenarios such as model training, model reasoning, or visualization, with flexible and wide applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 It is a first flow chart of the reduction calculation method of the multi-dimensional tensor according to the embodiment of the present invention.

[0053] Figure 2 FIG. 4 is a schematic diagram of a process of determining a step length according to an embodiment of the present invention.

[0054] Figure 3 The present invention is a flowchart of determining a reduction calculation result by using a plurality of parallel thread blocks according to an embodiment of the present invention.

[0055] Figure 4 This is a second flow chart of the multi-dimensional tensor reduction calculation method according to an embodiment of the present invention.

[0056] Figure 5 Schematic diagram of an exemplary one-dimensional arrangement of a three-dimensional tensor according to an embodiment of the present invention.

[0057] Figure 6 It is a schematic diagram of the reduction calculation process of a 3D tensor according to an embodiment of the present invention.

[0058] Figure 7 It is a schematic diagram of the calculation result of the 3D tensor reduction according to the embodiment of the present invention.

[0059] Figure 8 It is an exemplary schematic diagram of a one-dimensional arrangement of the reduced calculation results of a three-dimensional tensor according to an embodiment of the present invention.

[0060] Fig. 9 It is a first structural diagram of a multi-dimensional tensor reduction computing device according to an embodiment of the present invention.

[0061] Fig.10 It is a second structural diagram of the multi-dimensional tensor reduction calculation device according to an embodiment of the present invention.

[0062] Fig.11 is an exemplary structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0063] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings.

[0064] For the sake of brevity and intuitiveness in description, the scheme of the present invention is explained below by describing several representative implementations. A large number of details in the implementations are only used to help understand the scheme of the present invention. However, it is obvious that the technical scheme of the present invention may not be limited to these details when implemented. In order to avoid unnecessarily obscuring the scheme of the present invention, some implementations are not described in detail, but only a framework is given. Hereinafter, "including" means "including but not limited to", and "according to..." means "at least according to..., but not limited to only according to...". Due to the language habits of Chinese, when the number of a component is not specifically specified below, it means that the component can be one or more, or can be understood as at least one.

[0065] Reduction computing is a method to reduce data size and improve computing efficiency, mainly by reducing the dimension of data. In reduction computing, binary operators are usually used to operate on multiple data to generate a reduction result. Such operations usually include summation, minimum value, maximum value, logical AND, logical OR, etc.

[0066] Figure 1 It is a first flow chart of the reduction calculation method of the multi-dimensional tensor according to the embodiment of the present invention. Figure 1The method shown can be performed by a processor coupled to an artificial intelligence chip. Among them: the artificial intelligence chip is a module specifically used to process a large number of computing tasks in artificial intelligence applications. For example, the artificial intelligence chip may include a graphics processing unit (Graphics Processing Unit, GPU), a general-purpose graphics processing unit (General-purpose Computing on Graphics Processing Unit, GPGPU), a field programmable gate array (Field Programmable Gate Array, FPGA) or an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), etc. The processor coupled to the artificial intelligence chip may include a central processing unit (CPU), a microcontroller unit (Microcontroller Unit, MCU) or a micro control unit (for example, MPU), etc. Figure 1 As shown, the method includes:

[0067] Step 101: Determine m reduced dimensions and nm unreduced dimensions of an n-dimensional tensor, where m and n are positive integers of at least 2, and m is less than or equal to n.

[0068] Here, m reduced dimensions are determined from the n-dimensional tensor (e.g., determined based on user instructions). The remaining dimensions in the n-dimensional tensor are non-reduced dimensions, so there are a total of nm non-reduced dimensions.

[0069] Step 102: Generate a reduction computing instruction. After the reduction computing instruction is executed, K thread blocks are started on the artificial intelligence chip. The K thread blocks perform reduction computing on the K reduction computing areas corresponding to the K thread blocks in the n-dimensional tensor in m reduction dimensions in parallel. The number of threads contained in each thread block is associated with the number of elements contained in the m reduction dimensions, K is associated with the number of elements contained in the nm non-reduction dimensions, and each thread in each thread block reads its own reduction data from the reduction computing area corresponding to the thread block in parallel.

[0070] The elements contained in a dimension refer to the basic units or components constituting the dimension. In one embodiment, the number of threads contained in each thread block is associated with the number of elements contained in the m reduced dimensions, including: the number of threads contained in each thread block is equal to the product of the number of elements contained in each of the m reduced dimensions; K is associated with the number of elements contained in the nm non-reduced dimensions, including: K is equal to the product of the number of elements contained in each of the nm non-reduced dimensions.

[0071] For example: Assume that the n-dimensional tensor A[a1,a2,a3,ai …,a n ], a i is the number of elements in the i-th dimension, and the value range of i is [1,n]. Therefore, a1 is the number of elements in the first dimension, a2 is the number of elements in the second dimension, and so on. n is the number of elements in the nth dimension. Assuming that the second dimension and the nth dimension are the reduction dimensions, the number of thread blocks that execute the reduction calculation in parallel is K = a1×a3×a4…×a n-1 Moreover, the number of threads contained in each thread block is equal to a2×a n .

[0072] The following uses specific numerical values ​​as an example to illustrate the value of K and the number of threads included in each thread block.

[0073] Assume a four-dimensional tensor A[2,3,4,5], and need to reduce the first dimension (number of elements is 2) and the third dimension (number of elements is 4). Therefore, the number of thread blocks K is the product of the number of elements in the second dimension (a non-reduced dimension) and the number of elements in the fourth dimension (another non-reduced dimension), that is, K = 3 × 5 = 15, and the number of threads contained in each thread block is the product of the number of elements in the first dimension (a reduced dimension) and the number of elements in the third dimension (another reduced dimension), which is equal to 2 × 4. In other words, each thread block contains 8 threads.

[0074] In one embodiment, the method includes: determining the first step length of the n-dimensional tensor, the second step length of the m-reduced dimensions, and the third step length of the nm-unreduced dimensions; before sending the reduction calculation instruction to the artificial intelligence chip, the method includes: carrying the first step length, the second step length, and the third step length in the reduction calculation instruction. Therefore, based on the first step length, the second step length, and the third step length, each thread in each thread block can accurately access its own reduction data, which facilitates the K thread blocks to perform reduction calculations in parallel, further improving the calculation efficiency.

[0075] In one embodiment, determining the first step size of an n-dimensional tensor includes: for each dimension from the second dimension to the n-th dimension in the n-dimensional tensor, based on the step size of the previous dimension of each dimension and the number of elements of the previous dimension, determining the step size of each dimension from the second dimension to the n-th dimension, wherein the step size of the first dimension in the n-dimensional tensor is 1; combining the step size of the first dimension in the n-dimensional tensor and the step size of each dimension from the second dimension to the n-th dimension in the n-dimensional tensor into the first step size.

[0076] In one embodiment, determining the second step size of m reduced dimensions includes: for each dimension from the second dimension to the m-th dimension among the m reduced dimensions, based on the step size of the previous dimension of each dimension and the number of elements of the previous dimension, determining the step size of each dimension from the second dimension to the m-th dimension, wherein the step size of the first dimension among the m reduced dimensions is 1; combining the step size of the first dimension among the m reduced dimensions and the step size of each dimension from the second dimension to the m-th dimension into a second step size.

[0077] In one embodiment, determining the third step size of the nm non-reduced dimensions includes: for each dimension from the second dimension to the nm-th dimension among the nm non-reduced dimensions, based on the step size of the previous dimension of each dimension and the number of elements of the previous dimension, determining the step size of each dimension from the second dimension to the nm-th dimension, wherein the step size of the first dimension among the nm non-reduced dimensions is 1; combining the step size of the first dimension among the nm non-reduced dimensions and the step size of each dimension from the second dimension to the nm-th dimension into a third step size.

[0078] Figure 2 FIG. 4 is a schematic diagram of a process of determining a step length according to an embodiment of the present invention. Figure 2 The method shown can be applied to determine the first step length, the second step length and the third step length. Figure 2 As shown, the method includes:

[0079] Step 201: For the tensor whose stride is to be determined (assuming the total number of dimensions is P), i represents the current dimension number in the tensor, i.e., i=[1,2...P]. Determine that the stride of the first dimension (i=1) is 1, i.e., stride1 is equal to 1.

[0080] Step 202: Set i to 2.

[0081] Step 203: Determine whether i is less than or equal to P. If so, execute step 204 and subsequent steps; otherwise, execute step 206.

[0082] Step 204: Combine the step size of the (i-1)th dimension and the number of elements in the (i-1)th dimension (Dimension (i-1) ) is determined as the step size of the i-th dimension.

[0083] Step 205: increment i by 1, and return to execute step 203.

[0084] Step 206: Output the stride of each dimension to obtain the stride of the tensor. That is, the stride of the first dimension (stride1), the stride of the second dimension (stride2), the stride of the third dimension (stride3), and so on, the stride of the Pth dimension (stride p) is combined into the stride of the tensor.

[0085] For example, suppose there is a four-dimensional tensor A[2,3,4,5], and its first dimension (the number of elements is 2) and third dimension (the number of elements is 4) need to be reduced.

[0086] based on Figure 2 The process shown can determine:

[0087] (1) The first step length of the four-dimensional tensor A is: [1,2,6,24]. Among them: the step length of the first dimension of the four-dimensional tensor A is 1; the step length of the second dimension of the four-dimensional tensor A is 2 (1×2); the step length of the third dimension of the four-dimensional tensor A is 6 (2×3); the step length of the fourth dimension of the four-dimensional tensor A is 24 (6×4).

[0088] (2) The second step length of the two reduced dimensions (the first dimension of the four-dimensional tensor A and the third dimension of the four-dimensional tensor A) is: [1,2]. Among them: the step length of the first dimension in the tensor containing only the reduced dimensions (that is, the first dimension in the four-dimensional tensor A) is 1; the step length of the second dimension in the tensor containing only the reduced dimensions (that is, the third dimension in the four-dimensional tensor A) is 2 (1×2).

[0089] (3) The third step length of the two unreduced dimensions (the second dimension of the four-dimensional tensor A and the fourth dimension of the four-dimensional tensor A) is: [1,3]. Among them: the step length of the first dimension in the tensor containing only unreduced dimensions (that is, the second dimension in the four-dimensional tensor A) is 1; the step length of the second dimension in the tensor containing only reduced dimensions (that is, the fourth dimension in the four-dimensional tensor A) is 3 (1×3).

[0090] Figure 3 FIG. 1 is a flow chart of determining a reduction calculation result using multiple parallel thread blocks according to an embodiment of the present invention. Figure 3 As shown, K thread blocks perform reduction calculations on K reduction calculation regions corresponding to the K thread blocks in the n-dimensional tensor in m reduction dimensions in parallel, including:

[0091] Step 301: Based on the identifier of each thread block in the K thread blocks and the third step length, determine the first coordinate of the reduced computing region of each thread block in the non-reduced dimension.

[0092] Here, based on the identifier of each thread block and the third step length, the first coordinate of the reduced calculation area of ​​the thread block in the non-reduced dimension is determined. For example, first, the identifier of the thread block is divided by the outermost layer in the third step length (for example: for the third step length [1,3], the outermost layer is 3 and the innermost layer is 1), and the first quotient and the first remainder are determined. The first quotient is the outermost layer of the first coordinate. Then, the first remainder is divided by the second outermost layer in the third step length to determine the second quotient and the second remainder. The second quotient is the second outermost layer of the first coordinate. Then, continue to divide the second remainder by the inner layer of the second outermost layer (if any), and so on, until each layer in the third step length is calculated, and the first coordinate can be obtained based on the outermost layer, the second outermost layer, and so on of the first coordinate.

[0093] Step 302: Based on the identifier of each thread in each thread block and the second step length, determine the second coordinate of the reduced data of each thread in each thread block on the reduced dimension.

[0094] Here, based on the identifier of each thread in each thread block and the second step length, the second coordinate of the reduced data of each thread in each thread block on the reduced dimension is determined. For example, first, the thread identifier is divided by the outermost layer in the second step length to determine the third quotient and the third remainder, and the third quotient is the outermost layer of the second coordinate. Then, the third remainder is divided by the second outermost layer in the second step length to determine the fourth quotient and the fourth remainder, and the fourth quotient is the second outermost layer of the second coordinate. Then, continue to divide the fourth remainder by the inner layer of the second outermost layer (if any), and so on, until each layer in the second step length is calculated, and the second coordinate can be obtained based on the outermost layer, the second outermost layer, and other layers of the obtained second coordinate.

[0095] Step 303: Combine the first coordinate and the second coordinate to determine the third coordinate of the reduced data of each thread in each thread block in n dimensions.

[0096] Here, the first coordinate and the second coordinate are combined to determine the third coordinate of the reduced data of each thread in each thread block in n dimensions, wherein the combined position of the first coordinate in the third coordinate is the same as the position of the unreduced dimension in the multidimensional data, and the combined position of the second coordinate in the third coordinate is the same as the position of the reduced dimension in the multidimensional data.

[0097] Step 304: Based on the third coordinate and the first step length, read the protocol data of each thread in each thread block from the memory storing the n-dimensional tensor; based on the protocol data of each thread in each thread block, determine the protocol calculation result of each thread block.

[0098] The first step length includes the step length of each dimension of the n-dimensional tensor. First, the product between the coordinate value of each dimension in the third coordinate and the step length of the dimension is calculated. Then, these products are summed to obtain the storage location of the thread's specification data in the memory storing the n-dimensional tensor. Next, the thread's specification data is read from the storage location, and the specification data in the same thread block is reduced to obtain the specification calculation result of each thread block.

[0099] Step 305: Send a reduction calculation instruction to the artificial intelligence chip so that the artificial intelligence chip executes the reduction calculation instruction, wherein the reduction calculation result of the n-dimensional tensor is determined based on the K reduction calculation results of the K thread blocks.

[0100] By combining the K reduced calculation results of the K thread blocks (for example, based on the identification order of the thread blocks), a reduced calculation result of an n-dimensional tensor can be obtained.

[0101] Therefore, any number of reduced dimensions in a multidimensional tensor containing any number of dimensions can be reduced, without the need to design a special algorithm for each specific dimension, thereby improving versatility. Moreover, the embodiments of the present invention do not require preprocessing of the multidimensional tensor, thereby saving calculation time and improving calculation efficiency.

[0102] Figure 4 This is a second flow chart of the multi-dimensional tensor reduction calculation method according to an embodiment of the present invention. Figure 4 The method shown can be performed by an artificial intelligence chip coupled to a processor. Figure 4 As shown, the method includes:

[0103] Step 401: Receive a reduction calculation instruction for an n-dimensional tensor from a processor, where the n-dimensional tensor includes m reduced dimensions and nm unreduced dimensions, where m and n are positive integers of at least 2, and m is less than or equal to n.

[0104] Step 402: Execute the reduction calculation instruction to start K thread blocks, and the K thread blocks perform reduction calculations on K reduction calculation regions in the n-dimensional tensor corresponding to the K thread blocks in parallel on m reduction dimensions; wherein the number of threads contained in each thread block is associated with the number of elements contained in the m reduction dimensions, K is associated with the number of elements contained in the nm non-reduction dimensions, and each thread in each thread block reads its own reduction data from the reduction calculation region corresponding to the thread block in parallel.

[0105] Step 403: Based on the K reduced calculation results of the K thread blocks, determine the reduced calculation result of the n-dimensional tensor.

[0106] In one embodiment, the reduction calculation instruction includes a first step length of an n-dimensional tensor, a second step length of m reduction dimensions, and a third step length of nm non-reduction dimensions; K thread blocks perform reduction calculations on K reduction calculation regions in the n-dimensional tensor corresponding to the K thread blocks in parallel on the m reduction dimensions, including: determining a first coordinate of the reduction calculation region of each thread block on the non-reduction dimension based on an identifier and a third step length of each thread block in the K thread blocks; determining a second coordinate of the reduction data of each thread in each thread block on the reduction dimension based on an identifier and a second step length of each thread in each thread block; combining the first coordinate and the second coordinate to determine a third coordinate of the reduction data of each thread in each thread block on the n dimension; reading the reduction data of each thread in each thread block from a memory storing the n-dimensional tensor based on the third coordinate and the first step length; determining a reduction calculation result of each thread block based on the reduction data of each thread in each thread block.

[0107] The reduction computing scheme of the embodiment of the present invention can be applied in multiple scenarios. In the field of artificial intelligence, reduction computing is often used in tasks such as image processing, natural language processing, and machine learning. For example, in image processing, reduction computing can be used to perform image feature extraction and pattern recognition; in natural language processing, reduction computing can be used for the aggregation and analysis of text data; in machine learning, reduction computing can be used for training and prediction of large-scale data, and so on.

[0108] Specifically, the application scenarios of reduction computing in artificial intelligence can include:

[0109] (a) Image processing: In image recognition and object detection tasks, reduction computing can help to segment image data and extract features, thereby improving recognition accuracy and processing speed.

[0110] (b) Natural Language Processing: In text data analysis and sentiment analysis, reduction computing can summarize and classify text data to help extract key information and patterns.

[0111] (c) Machine Learning: In large-scale data training, reduced computing can be used for data preprocessing and aggregation to improve training efficiency and accuracy.

[0112] The following takes the implementation of n-dimensional tensors as multimedia data (e.g., two-dimensional image data, three-dimensional image data, four-dimensional image data (e.g., CT images), user attribute data containing a large number of user features, etc.) as an example to exemplify the specific application scenarios of the embodiments of the present invention.

[0113] In one embodiment, the n-dimensional tensor is multimedia data containing n features. Figure 1 , Figure 3 or Figure 4 The method includes: determining m reduced features from n features; and determining the m reduced features as m reduced dimensions.

[0114] In one embodiment, Figure 1 , Figure 3 or Figure 4 The method may include at least one of the following:

[0115] (1) constructing training data based on multimedia data that executes the specified computing instructions, and training the artificial intelligence model based on the training data;

[0116] (2) constructing inference data based on the multimedia data of the execution specification computing instructions, and inputting the inference data into the trained artificial intelligence model to obtain the inference results;

[0117] (3) Visualize multimedia data that executes the reduced computing instructions. By visualizing the multimedia data after dimensionality reduction, it is easier to intuitively understand the multimedia data.

[0118] The above exemplary description of the specific application scenarios of the reduction calculation of the embodiment of the present invention is appreciated by those skilled in the art that such description is only exemplary and is not intended to limit the protection scope of the embodiment of the present invention. For example, the above reduction calculation method can be performed on image data to reduce the dimension of the image data (such as the number of pixels, the number of color channels or the length of the feature vector, etc.), thereby simplifying the image representation.

[0119] The following uses a 3-dimensional tensor as an example to exemplarily describe an implementation of the present invention.

[0120] Figure 5 FIG. 1 is an exemplary schematic diagram of a one-dimensional arrangement of a three-dimensional tensor according to an embodiment of the present invention. Figure 5 , a schematic diagram showing the one-dimensional arrangement of the 3-dimensional tensor A[2,3,4] (that is, the storage method of the 3-dimensional tensor A[2,3,4] in the memory) and the corresponding schematic diagram of the multi-dimensional coordinates of the 3-dimensional tensor A[2,3,4] are shown.

[0121] The first step length stride of the 3D tensor A[2,3,4] ori =[1,2,6]. Assume that the third dimension of the 3D tensor A needs to be reduced, so the second step length of the reduced dimension is stride red = [1], the third step length stride of the non-reduced dimension rev =[1,2].

[0122] The first step length, the second step length, and the third step length are carried in the reduction calculation instruction, and the reduction calculation instruction is sent to the artificial intelligence chip. The product of the number of elements contained in the non-reduction dimension (2×3) is 6, and the number of elements contained in the reduction dimension is 4, so the reduction calculation instruction indicates to start 6 thread blocks (each thread block contains 4 threads) to perform reduction calculation on the 3D tensor A in parallel.

[0123] The artificial intelligence chip executes the reduced computing instruction. The six thread blocks each have their own identifier (for example, a value range of 0 to 5), and the four threads in each thread block each have their own identifier (for example, a value range of 0 to 3).

[0124] Based on the identifier of each thread block and the identifier of each thread, the three-dimensional coordinates of the specification data that each thread expects to read can be calculated.

[0125] The thread block ID is 4 as an example for description.

[0126] First, divide the thread block identity by (" / " operator) the third step length stride rev =[1,2]'s outermost layer (2), the quotient of the first division is 2, and the remainder is 0. Then use the remainder (0) to divide (" / " operator) the third step length stride rev The inner layer of the outermost layer (1) of the second division is 0. Based on the quotients of these two divisions, the first coordinate of the thread block identified as 4 in the unreduced dimension is determined: (0, 2).

[0127] Then, based on the identifier and the second stride of each thread in the thread block with identifier 4, red =[1]), determine the second coordinate of the reduced data of each thread in the thread block identified as 4 on the reduced dimension.

[0128] Take the thread ID 2 as an example: divide the thread ID (2) by the second step length stride red =[1]'s outermost layer (1), and obtains the second coordinate: (2). The second coordinate: (2) is combined with the first coordinate: (0,2) (the combination order is the same as the dimension order of the 3D tensor A) to obtain the three-dimensional coordinate: (0,2,2). Then, thread 2 in thread block 4, based on the three-dimensional coordinate: (0,2,2) and the first step length (stride ori = [1,2,6]), calculate the storage location of the protocol data that thread 2 needs to read in memory (refer to Figure 5, i.e., number 16 in the one-dimensional arrangement, for example, a specific value "17" is read from the storage location numbered 16). Similarly, the other threads in the thread block identified as 4 read out their respective protocol data. In the thread block identified as 4, the protocol data read out by the four threads are summed, and the sum is the protocol calculation result of the thread block identified as 4.

[0129] In a similar manner, the reduced calculation results of other thread blocks may be determined.

[0130] Next, the reduced calculation results of these six thread blocks are combined into the reduced calculation result of the three-dimensional tensor A[2,3,4].

[0131] Figure 6 Schematic diagram of the reduction calculation process of a 3D tensor according to an embodiment of the present invention. Figure 6 In the figure, the dotted box shows the reduced calculation area of ​​the thread block (along the third dimension), wherein the reduced calculation area of ​​the first thread block (marked as 0) (including reduced data 2, reduced data 8, reduced data 14 and reduced data 20) and the reduced calculation area of ​​the fifth thread block (marked as 4) (including reduced data 5, reduced data 11, reduced data 17 and reduced data 23) are exemplarily illustrated. Each thread block contains 4 threads, which are respectively used to read their own reduced data. For example, thread 0 of the fifth thread block reads reduced data 5, thread 1 of the fifth thread block reads reduced data 11, thread 2 of the fifth thread block reads reduced data 17, and thread 3 of the fifth thread block reads reduced data 23. By summing these reduced data, a sum value 60 (i.e., the reduced calculation result of the fifth thread block) can be obtained.

[0132] Similarly, the reduced calculation results of other thread blocks are calculated and combined to obtain the reduced calculation results of the 3D tensor. Figure 7 It is a schematic diagram of the calculation result of the 3D tensor reduction according to the embodiment of the present invention. Figure 8 It is an exemplary schematic diagram of a one-dimensional arrangement of the reduced calculation results of a three-dimensional tensor according to an embodiment of the present invention.

[0133] The following takes a 4-dimensional tensor as an example to exemplarily describe the implementation mode of the present invention. Assume that the first and third dimensions of the 4-dimensional tensor A[2,3,4,5] need to be reduced.

[0134] First, the controller (e.g., CPU) is based on Figure 2 The process shown calculates the first step length stride of the 4-dimensional tensor A ori =[1,2,6,24]; stride of the second step of the reduced dimension red = [1,2] and the third step length stride of the non-reduced dimension rev=[1,3].

[0135] Then, the controller sends the first step length, the second step length, and the third step length to the artificial intelligence chip. On the artificial intelligence chip, 15 thread blocks (labeled 0 to 14) are initiated to complete the reduction calculation task of the 4-dimensional tensor A in parallel.

[0136] The reduced calculation of the thread block with thread block ID 7 is taken as an example for description.

[0137] First, divide the thread block identifier (7) by the third step length stride rev The outermost layer (3) of the first division gives the quotient 2 and the remainder 1. Then divide the remainder by the third step length stride rev The inner layer of the outermost layer (1) of the second division is 0. Based on the quotients of these two divisions, the first coordinate (Coord dev ):(1,2).

[0138] Then, the eight threads in the thread block with ID 7 calculate the second coordinates (Coord red ), respectively combine the first coordinate and the second coordinate of each thread to determine the third coordinate of the reduced data of each thread in each thread block in n dimensions. Each thread reads its own reduced data (storage location is offset) from the memory storing the n-dimensional tensor based on its own third coordinate and the first step length; based on the reduced data of each thread in each thread block, determine the reduced calculation result of each thread block (for example, sum, minimum value, maximum value, logical AND, logical OR).

[0139] Table 1 is a schematic diagram of the reduced calculation in the thread block labeled 7.

[0140] Thread ID <![CDATA[Coord red ]]> offset 0 [0,0] 0*1+1*2+0*6+2*24＝50 1 [1,0] 1*1+1*2+0*6+2*24＝51 2 [0,1] 0*1+1*2+1*6+2*24＝56 3 [1,1] 1*1+1*2+1*6+2*24＝57 4 [0,2] 0*1+1*2+2*6+2*24＝62 5 [1,2] 1*1+1*2+2*6+2*24＝63 6 [0,3] 0*1+1*2+3*6+2*24＝68 7 [1,3] 1*1+1*2+3*6+2*24＝69

[0141] Table 1

[0142] In a similar manner, the reduced calculation results of other thread blocks can be determined. Then, the reduced calculation results of these 15 thread blocks are combined into the reduced calculation result of the 4-dimensional tensor A[2,3,4,5].

[0143] Fig. 9 FIG. 1 is a first structural diagram of a multi-dimensional tensor reduction computing device according to an embodiment of the present invention. The device is suitable for a processor (for example, the device can be integrated into a processor). Fig. 9As shown, the device includes: a determination module, used to determine m reduced dimensions and nm non-reduced dimensions of an n-dimensional tensor, wherein m and n are positive integers of at least 2, and m is less than or equal to n; a generation module, used to generate a reduction calculation instruction, which starts K thread blocks on an artificial intelligence chip after being executed, and the K thread blocks perform reduction calculations on K reduced calculation areas in the n-dimensional tensor corresponding to the K thread blocks in parallel on the m reduced dimensions; wherein the number of threads contained in each thread block is associated with the number of elements contained in the m reduced dimensions, K is associated with the number of elements contained in the nm non-reduced dimensions, and each thread in each thread block reads its own reduction data from the reduced calculation area corresponding to the thread block in parallel; a sending module, used to send the reduction calculation instruction to the artificial intelligence chip so that the artificial intelligence chip executes the reduction calculation instruction, wherein the reduction calculation result of the n-dimensional tensor is determined based on the K reduction calculation results of the K thread blocks.

[0144] In one embodiment, a determination module is used to determine the first step length of an n-dimensional tensor, the second step length of m reduced dimensions, and the third step length of nm unreduced dimensions; a sending module is used to carry the first step length, the second step length, and the third step length in a reduced calculation instruction before sending the reduced calculation instruction to an artificial intelligence chip.

[0145] In one embodiment, determining the first step length of an n-dimensional tensor includes: for each dimension from the second dimension to the n-th dimension in the n-dimensional tensor, based on the step length of the previous dimension of each dimension and the number of elements in the previous dimension, determining the step length of each dimension from the second dimension to the n-th dimension, wherein the step length of the first dimension in the n-dimensional tensor is 1; combining the step length of the first dimension in the n-dimensional tensor and the step length of each dimension from the second dimension to the n-th dimension in the n-dimensional tensor into the first step length; determining the second step length of m reduced dimensions includes: for each dimension from the second dimension to the m-th dimension in the m reduced dimensions, based on the step length of the previous dimension of each dimension and the number of elements in the previous dimension, determining the step length of each dimension from the second dimension to the m-th dimension The step length of each dimension in the m reduced dimensions is 1; the step length of the first dimension in the m reduced dimensions and the step length of each dimension from the second dimension to the m-th dimension are combined into a second step length; determining the third step length of the nm non-reduced dimensions includes: for each dimension from the second dimension to the nm-th dimension in the nm non-reduced dimensions, based on the step length of the previous dimension of each dimension and the number of elements of the previous dimension, determining the step length of each dimension from the second dimension to the nm-th dimension, wherein the step length of the first dimension in the nm non-reduced dimensions is 1; the step length of the first dimension in the nm non-reduced dimensions and the step length of each dimension from the second dimension to the nm-th dimension are combined into a third step length.

[0146] In one embodiment, the number of threads contained in each thread block is associated with the number of elements contained in the m reduced dimensions, including: the number of threads contained in each thread block is equal to the product of the number of elements contained in each of the m reduced dimensions; K is associated with the number of elements contained in the nm non-reduced dimensions, including: K is equal to the product of the number of elements contained in each of the nm non-reduced dimensions.

[0147] Fig.10 FIG. 2 is a second structural diagram of a multi-dimensional tensor reduction computing device according to an embodiment of the present invention. The device is suitable for an artificial intelligence chip (for example, the device can be integrated into an artificial intelligence chip). Fig.10 As shown, the device includes: a receiving module, which is used to receive a reduction calculation instruction of an n-dimensional tensor, wherein the n-dimensional tensor includes m reduction dimensions and nm non-reduction dimensions, wherein m and n are positive integers of at least 2, and m is less than or equal to n; an execution module, which is used to execute the reduction calculation instruction to start K thread blocks, wherein the K thread blocks perform reduction calculations on K reduction calculation areas in the n-dimensional tensor corresponding to the K thread blocks in parallel on the m reduction dimensions; wherein the number of threads contained in each thread block is associated with the number of elements contained in the m reduction dimensions, K is associated with the number of elements contained in the nm non-reduction dimensions, and each thread in each thread block reads its own reduction data from the reduction calculation area corresponding to the thread block in parallel; and a determination module, which is used to determine the reduction calculation result of the n-dimensional tensor based on the K reduction calculation results of the K thread blocks.

[0148] In one embodiment, the reduction calculation instruction includes a first step length of an n-dimensional tensor, a second step length of m reduction dimensions, and a third step length of nm non-reduction dimensions; K thread blocks perform reduction calculations on K reduction calculation regions in the n-dimensional tensor corresponding to the K thread blocks in parallel on the m reduction dimensions, including: determining a first coordinate of the reduction calculation region of each thread block on the non-reduction dimension based on an identifier and a third step length of each thread block in the K thread blocks; determining a second coordinate of the reduction data of each thread in each thread block on the reduction dimension based on an identifier and a second step length of each thread in each thread block; combining the first coordinate and the second coordinate to determine a third coordinate of the reduction data of each thread in each thread block on the n dimension; reading the reduction data of each thread in each thread block from a memory storing the n-dimensional tensor based on the third coordinate and the first step length; determining a reduction calculation result of each thread block based on the reduction data of each thread in each thread block.

[0149] In one embodiment, the n-dimensional tensor is multimedia data containing n features, and the determination module is used to determine m reduced features from the n features; and determine the m reduced features as m reduced dimensions.

[0150] In one embodiment, an application module ( Fig.10 (not shown) and is used to perform at least one of the following: constructing training data based on multimedia data that executes reduced computing instructions, and training an artificial intelligence model based on the training data; constructing inference data based on multimedia data that executes reduced computing instructions, and inputting the inference data into a trained artificial intelligence model to obtain an inference result; and visualizing multimedia data that executes reduced computing instructions.

[0151] In summary, in the implementation of the present invention, m reduced dimensions and nm non-reduced dimensions of an n-dimensional tensor are determined; a reduction calculation instruction is generated, and after the reduction calculation instruction is executed, K thread blocks are started on the artificial intelligence chip, and the K thread blocks perform reduction calculations on the K reduced calculation areas in parallel on the m reduced dimensions; the number of threads contained in each thread block is associated with the number of elements contained in the m reduced dimensions, and K is associated with the number of elements contained in the nm non-reduced dimensions, and each thread in each thread block reads its own reduced data in parallel; the reduction calculation instruction is sent to the artificial intelligence chip, and the artificial intelligence chip executes the reduction calculation instruction. It can be seen that any number of reduced dimensions in a multidimensional tensor containing any number of dimensions can be reduced. There is no need to design a special reduction algorithm for each specific dimension of the tensor, which improves versatility. Moreover, the implementation of the present invention does not require preprocessing of the tensor (such as scaling, normalization, padding and sparseness, etc.), which saves calculation time and improves calculation efficiency. In addition, based on the numerical first step length, second step length, and third step length, each thread in each thread block can accurately access its own reduced data, which facilitates the K thread blocks to perform reduced calculations in parallel, further improving the calculation efficiency. In addition, the embodiments of the present invention can be applied to various data such as multimedia data and various scenarios such as model training, model reasoning, and visualization, with flexible and wide applicability.

[0152] The embodiment of the present invention further provides an electronic device having a processor-memory architecture. Fig.11 FIG. 1 is an exemplary structural diagram of an electronic device according to an embodiment of the present invention. Fig.11As shown, the electronic device includes a processor 801, a memory 802, and a computer program stored in the memory 802 and executable on the processor 801. When the computer program is executed by the processor 801, any of the above multi-dimensional tensor reduction calculation methods is implemented. Among them, the memory 802 can be specifically implemented as a variety of storage media such as an electrically erasable programmable read-only memory (EEPROM), a flash memory (Flash memory), and a programmable program read-only memory (PROM). The processor 801 can be implemented as including one or more central processing units or one or more field programmable gate arrays, wherein the field programmable gate array integrates one or more central processing unit cores. Specifically, the central processing unit or the central processing unit core can be implemented as a CPU, a GPU, a GPGPU, an MCU or a DSP, and the like.

[0153] It should be noted that not all steps and modules in the above processes and structure diagrams are necessary, and some steps or modules can be ignored according to actual needs. The execution order of each step is not fixed and can be adjusted as needed. The division of each module is only for the convenience of describing the functional division adopted. In actual implementation, a module can be implemented by multiple modules, and the functions of multiple modules can also be implemented by the same module. These modules can be located in the same device or in different devices.

[0154] The hardware modules in each embodiment can be implemented mechanically or electronically. For example, a hardware module may include specially designed permanent circuits or logic devices (such as dedicated processors, such as FPGA or ASIC) to perform specific operations. For example, specific operations can be performed in various types of chips (for example, artificial intelligence chips). The hardware module may also include programmable logic devices or circuits (such as general-purpose processors or other programmable processors) temporarily configured by software to perform specific operations. As for whether to implement the hardware module by mechanical means, or by using a dedicated permanent circuit, or by using a temporarily configured circuit (such as configured by software), it can be decided based on cost and time considerations.

[0155] The present invention also provides a machine-readable storage medium, storing instructions for making a machine perform a method as described in the present application. Specifically, a system or device equipped with a storage medium can be provided, on which a software program code for realizing the function of any of the embodiments in the above-mentioned embodiments is stored, and the computer (or CPU or MPU) of the system or device reads out and executes the program code stored in the storage medium. In addition, the operating system etc. operated on the computer can also be completed part or all of the actual operation by instructions based on the program code. The program code read out from the storage medium can also be written to the memory provided in the expansion board inserted into the computer or to the memory provided in the expansion unit connected to the computer, and then the CPU etc. installed on the expansion board or the expansion unit are made to perform part and all of the actual operation based on the instructions of the program code, so as to realize the function of any of the embodiments in the above-mentioned embodiments. The storage medium implementation for providing the program code includes a floppy disk, a hard disk, a magneto-optical disk, an optical disk (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), a magnetic tape, a non-volatile memory card and a ROM. Alternatively, the program code can be downloaded from a server computer or a cloud by a communication network.

[0156] In this article, "schematic" means "serving as an example, instance or explanation", and any diagram or implementation method described as "schematic" in this article should not be interpreted as a more preferred or more advantageous technical solution. In order to make the drawings concise, only the parts related to the present invention are schematically shown in each figure, and do not represent the actual structure of the product. In addition, in order to make the drawings concise and easy to understand, in some figures, only one of the parts with the same structure or function is schematically drawn, or only one of them is marked. In this article, "one" does not mean that the number of the relevant parts of the present invention is limited to "only one", and "one" does not mean that the number of the relevant parts of the present invention is "more than one". In this article, "upper", "lower", "front", "back", "left", "right", "inside", "outside", etc. are only used to indicate the relative position relationship between the relevant parts, rather than to limit the absolute position of these relevant parts.

[0157] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for calculating multidimensional tensor reduction, characterized in that: The method is applicable to a processor, and the method comprises: Determine m reduced dimensions and nm unreduced dimensions of an n-dimensional tensor, where m and n are positive integers at least 2, and m is less than or equal to n; Generate a reduction calculation instruction, which starts K thread blocks on the artificial intelligence chip after being executed, and the K thread blocks perform reduction calculations on the K reduction calculation areas in the n-dimensional tensor corresponding to the K thread blocks in parallel on the m reduction dimensions; wherein the number of threads contained in each thread block is associated with the number of elements contained in the m reduction dimensions, the K is associated with the number of elements contained in the nm non-reduction dimensions, and each thread in each thread block reads its own reduction data from the reduction calculation area corresponding to the thread block in parallel; The reduction computing instruction is sent to the artificial intelligence chip so that the artificial intelligence chip executes the reduction computing instruction, wherein the reduction computing result of the n-dimensional tensor is determined based on the K reduction computing results of the K thread blocks.

2. The method according to claim 1, characterized in that include: Determine a first step length of the n-dimensional tensor, a second step length of the m reduced dimensions, and a third step length of the nm unreduced dimensions; Before sending the reduced calculation instruction to the artificial intelligence chip, the method includes: The first step length, the second step length and the third step length are carried in the reduced calculation instruction.

3. The method according to claim 2, characterized in that The determining of the first step length of the n-dimensional tensor comprises: for each dimension from the second dimension to the n-th dimension in the n-dimensional tensor, based on the step length of the previous dimension of each dimension and the number of elements of the previous dimension, determining the step length of each dimension from the second dimension to the n-th dimension, wherein the step length of the first dimension in the n-dimensional tensor is 1; combining the step length of the first dimension in the n-dimensional tensor and the step length of each dimension from the second dimension to the n-th dimension in the n-dimensional tensor into the first step length; The determining of the second step length of the m reduced dimensions comprises: for each dimension from the second dimension to the m-th dimension of the m reduced dimensions, based on the step length of the previous dimension of each dimension and the number of elements of the previous dimension, determining the step length of each dimension from the second dimension to the m-th dimension, wherein the step length of the first dimension of the m reduced dimensions is 1; combining the step length of the first dimension of the m reduced dimensions and the step length of each dimension from the second dimension to the m-th dimension into the second step length; The determining of the third step size of the nm non-reduced dimensions includes: for each dimension from the second dimension to the nm-th dimension among the nm non-reduced dimensions, based on the step size of the previous dimension of each dimension and the number of elements of the previous dimension, determining the step size of each dimension from the second dimension to the nm-th dimension, wherein the step size of the first dimension among the nm non-reduced dimensions is 1; combining the step size of the first dimension among the nm non-reduced dimensions and the step size of each dimension from the second dimension to the nm-th dimension into the third step size.

4. The method according to claim 1, characterized in that: The number of threads included in each thread block is associated with the number of elements included in the m reduction dimensions, including: the number of threads included in each thread block is equal to the product of the number of elements included in each of the m reduction dimensions; The K is associated with the number of elements included in the nm non-reduced dimensions, including: the K is equal to the product of the number of elements included in each of the nm non-reduced dimensions.

5. A method for calculating multidimensional tensor reduction, characterized in that: The method is applicable to an artificial intelligence chip, and the method comprises: Receiving a reduction calculation instruction for an n-dimensional tensor, wherein the n-dimensional tensor includes m reduced dimensions and nm unreduced dimensions, wherein m and n are positive integers of at least 2, and m is less than or equal to n; Execute the reduction calculation instruction to start K thread blocks, the K thread blocks perform reduction calculations on the K reduction calculation regions corresponding to the K thread blocks in the n-dimensional tensor in the m reduction dimensions in parallel; wherein the number of threads included in each thread block is associated with the number of elements included in the m reduction dimensions, the K is associated with the number of elements included in the nm non-reduction dimensions, and each thread in each thread block reads its own reduction data from the reduction calculation region corresponding to the thread block in parallel; Based on the K reduced calculation results of the K thread blocks, a reduced calculation result of the n-dimensional tensor is determined.

6. The method according to claim 5, characterized in that The reduced calculation instruction includes a first step length of the n-dimensional tensor, a second step length of the m reduced dimensions, and a third step length of the nm non-reduced dimensions; The K thread blocks performing reduction calculations on the K reduction calculation regions corresponding to the K thread blocks in the n-dimensional tensor in the m reduction dimensions in a parallel manner includes: Determine, based on an identifier of each thread block in the K thread blocks and the third step length, a first coordinate of a reduced computing region of each thread block in a non-reduced dimension; Determine, based on the identifier of each thread in each thread block and the second step length, a second coordinate of the reduced data of each thread in each thread block on the reduced dimension; combining the first coordinate and the second coordinate to determine a third coordinate of the reduced data of each thread in each thread block in n dimensions; Based on the third coordinate and the first step length, read the specification data of each thread in each thread block from the memory storing the n-dimensional tensor; Based on the specification data of each thread in each thread block, a specification calculation result of each thread block is determined.

7. The method according to claim 5, characterized in that The n-dimensional tensor is multimedia data containing n features, and the method includes: Determining m reduced features from the n features; The m reduction features are determined as the m reduction dimensions.

8. The method according to claim 7, characterized in that Include at least one of the following: Constructing training data based on the multimedia data that executes the reduced computing instructions, and training the artificial intelligence model based on the training data; Constructing inference data based on the multimedia data that executes the reduced computing instructions, and inputting the inference data into a trained artificial intelligence model to obtain an inference result; The multimedia data of the reduced computing instructions are visualized.

9. A multi-dimensional tensor reduction computing device, characterized in that: The device is suitable for a processor, and the device comprises: A determination module, configured to determine m reduced dimensions and nm unreduced dimensions of an n-dimensional tensor, wherein m and n are positive integers of at least 2, and m is less than or equal to n; A generation module, for generating a reduction calculation instruction, wherein after the reduction calculation instruction is executed, K thread blocks are started on the artificial intelligence chip, and the K thread blocks perform reduction calculations on the K reduction calculation areas corresponding to the K thread blocks in the n-dimensional tensor in the m reduction dimensions in parallel; wherein the number of threads contained in each thread block is associated with the number of elements contained in the m reduction dimensions, the K is associated with the number of elements contained in the nm non-reduction dimensions, and each thread in each thread block reads its own reduction data from the reduction calculation area corresponding to the thread block in parallel; A sending module is used to send the reduction calculation instruction to the artificial intelligence chip so that the artificial intelligence chip executes the reduction calculation instruction, wherein the reduction calculation result of the n-dimensional tensor is determined based on the K reduction calculation results of the K thread blocks.

10. A multi-dimensional tensor reduction computing device, characterized in that: The device is suitable for an artificial intelligence chip, and the device comprises: A receiving module, configured to receive a reduction calculation instruction for an n-dimensional tensor, wherein the n-dimensional tensor includes m reduced dimensions and nm unreduced dimensions, wherein m and n are positive integers of at least 2, and m is less than or equal to n; An execution module, configured to execute the reduction calculation instruction to start K thread blocks, wherein the K thread blocks perform reduction calculations on the K reduction calculation regions corresponding to the K thread blocks in the n-dimensional tensor in the m reduction dimensions in parallel; wherein the number of threads included in each thread block is associated with the number of elements included in the m reduction dimensions, the K is associated with the number of elements included in the nm non-reduction dimensions, and each thread in each thread block reads its own reduction data from the reduction calculation region corresponding to the thread block in parallel; A determination module is used to determine the reduced calculation result of the n-dimensional tensor based on the K reduced calculation results of the K thread blocks.

11. An electronic device, characterized in that: include: Memory; processor; The memory stores an application program executable by the processor, which is used to enable the processor to execute the reduction calculation method for a multidimensional tensor as described in any one of claims 1-4 or the reduction calculation method for a multidimensional tensor as described in any one of claims 5-8.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-readable instructions, which, when executed by a processor, cause the processor to execute the reduction calculation method for a multidimensional tensor as described in any one of claims 1 to 4 or the reduction calculation method for a multidimensional tensor as described in any one of claims 5 to 8.

13. A program product comprising a computer program, characterized in that When the computer program is executed by a processor, the computer program implements the method for reducing the multidimensional tensor according to any one of claims 1 to 4 or the method for reducing the multidimensional tensor according to any one of claims 5 to 8.

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