On-chip firmware security protection method, device, equipment and medium

Abstract

The invention provides an on-chip firmware safety protection method and device, equipment and a medium, and the method comprises the steps: generating a target protection mode corresponding to a protection demand level according to the protection demand level of a to-be-processed chip; wherein the target protection mode comprises a plurality of sub-protection modes of different levels; when a target operation on the to-be-processed chip is detected, using the target protection mode to detect the target operation; and when the target operation sequentially passes the verification of each sub-protection mode in the target protection mode, executing the target operation on the to-be-processed chip. According to the embodiment of the invention, by adding protection to the to-be-processed chip, the processing operation needs to be verified before the processing operation is carried out on the to-be-processed chip, and the processing operation can be carried out on the to-be-processed chip only when the verification is passed, so that chip damage caused by abnormal operation is avoided.

Description

Technical Field

[0001] The present application relates to the field of chip protection technology, and in particular to a method, device, equipment and medium for on-chip firmware security protection. Background Art

[0002] Currently, non-volatile memories inside chips are almost all designed and implemented through direct programming (writing) operations and erasing operations. For the erasing and programming (writing) operations, the programming operation directly writes to the address, and the erasing operation is implemented by writing the corresponding erase command.

[0003] Non-volatile memory, such as FLASH or OTP, is an internal storage unit of the chip. The information stored is mainly the customer's program or important chip calibration information. If there are no corresponding protection measures in the chip design, the stored information is likely to be rewritten due to misoperation or system abnormality during chip debugging or application. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a method, device, equipment and medium for on-chip firmware security protection to overcome the problems in the prior art.

[0005] In a first aspect, an embodiment of the present application provides a method for on-chip firmware security protection, the method comprising:

[0006] According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels;

[0007] When a target operation on the chip to be processed is detected, detecting the target operation using the target protection mode;

[0008] When the target operation passes the verification of each sub-protection mode in the target protection mode in sequence, the target operation is performed on the chip to be processed.

[0009] In some technical solutions of the present application, the chip to be processed includes a first protection area; the protection requirement level of the chip to be processed is a low-level protection requirement;

[0010] According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including:

[0011] According to the low-level protection requirements of the chip to be processed, a first-level protection mode, a second-level protection mode and a third-level protection mode are generated in the first protection area; wherein the first-level protection mode is register access protection, the second-level protection mode is the overall operation enable protection of the register, and the third-level protection mode is the sub-operation enable protection of the register.

[0012] In some technical solutions of the present application, the chip to be processed includes a first protection area; the register of the chip to be processed includes a plurality of sub-areas, and the protection requirement level of the chip to be processed is a medium protection requirement;

[0013] According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including:

[0014] According to the intermediate-level protection requirements of the chip to be processed, a first-level protection mode, a second-level protection mode, a third-level protection mode and a fourth-level protection mode are generated in the first protection area; wherein the first-level protection mode is register access protection, the second-level protection mode is the overall operation enable protection of the register, the third-level protection mode is the sub-operation enable protection of the register, and the fourth-level protection mode is the sub-area locking protection.

[0015] In some technical solutions of the present application, the chip to be processed includes a first protection area and a second protection area; the protection requirement level of the chip to be processed is a high-level protection requirement;

[0016] According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including:

[0017] According to the high-level protection requirements of the chip to be processed, a first-level protection mode, a second-level protection mode and a third-level protection mode are generated in the first protection area; a fifth-level protection mode is generated in the second protection area; wherein the first-level protection mode is register access protection, the second-level protection mode is the overall operation enable protection of the register, the third-level protection mode is the sub-operation enable protection of the register, and the fifth-level protection mode is the overall area locking protection.

[0018] In some technical solutions of the present application, the chip to be processed includes a first protection area and a second protection area; the protection requirement level of the chip to be processed is a higher level protection requirement;

[0019] According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including:

[0020] According to the higher level protection requirements of the chip to be processed, a first level protection mode, a second level protection mode, a third level protection mode and a fourth level protection mode are generated in the first protection area; a fifth level protection mode is generated in the second protection area; wherein the first level protection mode is register access protection, the second level protection mode is the overall operation enable protection of the register, the third level protection mode is the sub-operation enable protection of the register, the fourth level protection mode is the sub-area locking protection, and the fifth level protection mode is the overall area locking protection.

[0021] In some technical solutions of the present application, when the target operation sequentially passes the verification of each sub-protection mode in the target protection mode, executing the target operation on the chip to be processed includes:

[0022] Reading a first identification bit, a second identification bit, a third identification bit, and a fourth identification bit corresponding to the first level protection mode, the second level protection mode, the third level protection mode, and the fourth level protection mode from the first protection area;

[0023] Reading the fifth identification bit of the fifth level protection mode from the second protection area;

[0024] The first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the fifth identification bit are verified in sequence, and when all the identification bits pass the verification, the target operation is performed on the chip to be processed.

[0025] In some technical solutions of the present application, the above method further includes:

[0026] If any one of the first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the fifth identification bit fails the verification, no subsequent verification is performed, and the target operation is not performed on the chip to be processed.

[0027] In a second aspect, an embodiment of the present application provides a device for on-chip firmware security protection, the device comprising:

[0028] A generating module, configured to generate a target protection mode corresponding to the protection requirement level of the chip to be processed according to the protection requirement level of the chip to be processed; wherein the target protection mode includes a plurality of sub-protection modes of different levels;

[0029] A detection module, configured to detect the target operation using the target protection mode when a target operation on the chip to be processed is detected;

[0030] The verification module is used to execute the target operation on the chip to be processed when the target operation passes the verification of each sub-protection mode in the target protection mode in sequence.

[0031] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned on-chip firmware security protection method when executing the computer program.

[0032] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned on-chip firmware security protection method are executed.

[0033] The technical solution provided by the embodiments of the present application may have the following beneficial effects:

[0034] The method of the present application includes generating a target protection mode corresponding to the protection requirement level of the chip to be processed according to the protection requirement level of the chip to be processed; wherein the target protection mode includes a plurality of sub-protection modes of different levels; when a target operation on the chip to be processed is detected, the target operation is detected using the target protection mode; when the target operation passes the verification of each sub-protection mode in the target protection mode in turn, the target operation is performed on the chip to be processed. The embodiment of the present application increases protection for the chip to be processed. Before the processing operation is performed on the chip to be processed, the processing operation needs to be verified. The processing operation can be performed on the chip to be processed only when it passes the verification, thereby avoiding damage to the chip caused by abnormal operation.

[0035] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0037] Figure 1A schematic flow chart of a method for on-chip firmware security protection provided by an embodiment of the present application is shown;

[0038] Figure 2 A schematic diagram showing a specific read operation and write operation process provided by an embodiment of the present application is shown;

[0039] Figure 3 A schematic diagram of an on-chip firmware security protection device provided by an embodiment of the present application is shown;

[0040] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0042] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0043] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0044] Currently, non-volatile memories inside chips are almost all designed and implemented through direct programming (writing) operations and erasing operations. For the erasing and programming (writing) operations, the programming operation directly writes to the address, and the erasing operation is implemented by writing the corresponding erase command.

[0045] Non-volatile memory, such as FLASH or OTP, is an internal storage unit of the chip. The information stored is mainly the customer's program or important chip calibration information. If there are no corresponding protection measures in the chip design, the stored information is likely to be rewritten due to misoperation or system abnormality during chip debugging or application.

[0046] Based on this, the embodiments of the present application provide a method, apparatus, device and medium for on-chip firmware security protection, which are described below through embodiments.

[0047] Figure 1 A schematic flow chart of a method for on-chip firmware security protection provided by an embodiment of the present application is shown, wherein the method comprises steps S101-S103; specifically:

[0048] S101, generating a target protection mode corresponding to the protection requirement level of the chip to be processed according to the protection requirement level; wherein the target protection mode includes a plurality of sub-protection modes of different levels;

[0049] S102, when a target operation on the chip to be processed is detected, detecting the target operation using the target protection method;

[0050] S103: When the target operation passes the verification of each sub-protection mode in the target protection mode in sequence, execute the target operation on the chip to be processed.

[0051] The embodiment of the present application increases protection for the chip to be processed. Before the processing operation is performed on the chip to be processed, the processing operation needs to be verified. The processing operation can be performed on the chip to be processed only when the verification is passed, thereby avoiding chip damage caused by abnormal operation.

[0052] Some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0053] In the embodiment of the present application, the chip that needs to be processed is called a chip to be processed. By setting a target protection mode for the chip to be processed, the security of the chip to be processed is improved. When setting the target protection mode for the chip to be processed, the embodiment of the present application mainly considers the protection requirement level of the chip to be processed, and the target protection mode set for different protection requirement levels is different. Here, the protection requirement level of the chip to be processed can be determined according to the specific business executed by the chip to be processed. For example, when the chip to be processed executes business A, its protection requirement level is low, and when the chip to be processed executes business B, its protection requirement level is high. In the specific implementation, the embodiment of the present application divides the protection requirement level of the chip to be processed into low-level protection requirements, medium-level protection requirements, high-level protection requirements and higher-level protection requirements. That is, the embodiment of the present application sets a target protection mode for the chip to be processed with a low-level protection requirement, a target protection mode for the chip to be processed with a medium-level protection requirement, a target protection mode for the chip to be processed with a high-level protection requirement, and a target protection mode for the chip to be processed with a higher-level protection requirement.

[0054] The target protection mode in the embodiment of the present application includes a plurality of sub-protection modes of different levels. When setting the target protection mode, the specific differences are reflected in the included sub-protection modes. The sub-protection modes of different levels here include a first-level protection mode, a second-level protection mode, a third-level protection mode, a fourth-level protection mode, and a fifth-level protection mode. Among them, the first-level protection mode, the second-level protection mode, the third-level protection mode, and the fourth-level protection mode are set on the first protection area of ​​the chip to be processed, and the fifth-level protection mode is set on the second protection area of ​​the chip to be processed.

[0055] Specifically, the first level protection mode is register access protection, the second level protection mode is register overall operation enable protection, the third level protection mode is register sub-operation enable protection, the fourth level protection mode is sub-area lock protection, and the fifth level protection mode is overall area lock protection. The first protection area is the FLASH area, and the second protection area is the OTP (One Time Programmable) area. FLASH area: Chip flash memory, also known as non-volatile random access Q memory, is a storage technology embedded in an integrated circuit (IC), mainly used for long-term data storage, and can maintain content even when the power is turned off. OTP (One Time Programmable) is a type of memory for microcontrollers, which means one-time programmable: after the program is burned into the microcontroller, it cannot be changed or cleared again.

[0056] When setting the target protection mode specifically, its correspondence with the protection requirement level is: according to the low-level protection requirement of the chip to be processed, the first-level protection mode, the second-level protection mode and the third-level protection mode are generated in the first protection area; according to the medium-level protection requirement of the chip to be processed, the first-level protection mode, the second-level protection mode, the third-level protection mode and the fourth-level protection mode are generated in the first protection area; according to the high-level protection requirement of the chip to be processed, the first-level protection mode, the second-level protection mode and the third-level protection mode are generated in the first protection area; the fifth-level protection mode is generated in the second protection area; according to the higher-level protection requirement of the chip to be processed, the first-level protection mode, the second-level protection mode, the third-level protection mode and the fourth-level protection mode are generated in the first protection area; the fifth-level protection mode is generated in the second protection area.

[0057] After the target protection mode is set, the chip to be processed is monitored. When the target operation of the chip to be processed is detected, the target operation is detected using the target protection mode, and when the target operation passes the verification of each sub-protection mode in the target protection mode in turn, the target operation is performed on the chip to be processed.

[0058] For chips to be processed with low-level protection requirements, the target operation needs to be verified by the first-level protection mode, the second-level protection mode, and the third-level protection mode. For chips to be processed with medium-level protection requirements, the target operation needs to be verified by the first-level protection mode, the second-level protection mode, the third-level protection mode, and the fourth-level protection mode. For chips to be processed with high-level protection requirements, the target operation needs to be verified by the first-level protection mode, the second-level protection mode, the third-level protection mode, and the fifth-level protection mode. For chips to be processed with higher-level protection requirements, the target operation needs to be verified by the first-level protection mode, the second-level protection mode, the third-level protection mode, the fourth-level protection mode, and the fifth-level protection mode.

[0059] During the specific verification, the first identification bit, the second identification bit, the third identification bit, and the fourth identification bit corresponding to the first level protection mode, the second level protection mode, the third level protection mode, and the fourth level protection mode are read from the first protection area; the fifth identification bit of the fifth level protection mode is read from the second protection area; the first identification bit, the second identification bit, the third identification bit, the fourth identification bit, and the fifth identification bit are verified in turn, and when all the identification bits pass the verification, the target operation is performed on the chip to be processed. If any of the first identification bit, the second identification bit, the third identification bit, the fourth identification bit, and the fifth identification bit fails to pass the verification, no subsequent verification is performed, and the target operation is not performed on the chip to be processed.

[0060] In an optional implementation manner, the writing and erasing operations on the FLASH need to be enabled by configuring the relevant registers of the flash before the FLASH can be written and erased.

[0061] The first level of protection: access protection for FLASH registers. All FLASH registers are protected by eallow, that is, eallow must be configured before the FLASH registers can be configured. If eallow is not enabled, FLASH cannot be enabled.

[0062] The second level protection mode: FLASH enable protection (overall operation enable protection). When FLASH enable is turned off, FLASH will ignore all write and erase instructions, and the third level protection mode will definitely not take effect.

[0063] The third level protection mode: FLASH operation protection (sub-operation enable protection), there are separate write operation enable and erase operation enable for FLASH writing and erasing. When the corresponding enable is not turned on, the write and erase operations will not be performed.

[0064] The fourth level of protection: lock protection (sub-area lock protection), locks different areas (different sectors) of FLASH. The lock function can only be written from 0 to 1, and cannot be rewritten from 1 to 0, and the reset domain is a power-on reset, that is, the register will be reset to 0 only when the chip is powered on, and other resets cannot be reset. That is, after mass production and testing, the code can be protected by locking the programming area to ensure that the chip program will not be rewritten by mistake during normal operation. It should be noted that if the flash area is locked, the chip will not be able to unlock the lock without powering off. That is, the locked area cannot be updated during online updates.

[0065] The fifth level protection mode: permanent protection mechanism (whole area lock protection), in the OTP area, define a control lockflag for FLASH. If the corresponding lockflag is effective, the whole chip erase of FLASH and the sector erase and program of the corresponding sector cannot be executed. It should be noted that if the flash area marked by OTP is locked, the FLASH area corresponding to the chip will be permanently locked.

[0066] In an optional embodiment, if Figure 2 As shown, for FLASH write operation: configure the eallow register to allow write operation to the FLASH operation register; configure FLASHenable to be valid to allow FLASH to perform erase and write operations;

[0067] Configure the write enable of FLASH, that is, flash_write_enable is valid, allowing flash to perform write operations; determine whether the sector of the current write address is locked by wr_lock, if locked, the operation is not allowed (FLASHwritelock: each sector has its own lock flag, which can be locked individually, if locked, writing is not allowed); if there is no write lock, execute the read lockflag from OTP to see if the flag is marked as locked, if it is locked, writing cannot be performed, if not locked, write data to FLASH.

[0068] For FLASH erase operation: configure eallow register to allow write operation to FLASH operation register; configure FLASHenable to be valid, allow FLASH to perform erase and write operation; configure FLASH erase enable, i.e. flash_erase_enable is valid, and FLASH is allowed to execute erase command; if the whole flash is erased, it is necessary to judge whether all sectoreraselock are 0, i.e. all sectors are allowed to be erased, if all are allowed, erase is executed, otherwise it is not allowed to execute; if part of the flash is erased, it is necessary to judge whether the sectoreraselock to be erased is 0, if it is allowed (lock=0), erase is executed, otherwise it is not allowed to execute; read from otp, lock flag mark, and judge the subsequent process; if there is no lock, erase the corresponding data. Other instructions: if FLASH erase and write enable is turned on and the erase or write operation process is completed, the enable will be automatically turned off through the hardware circuit. That is, the enable of the second level protection mode of FLASH will be automatically turned off, and thus the enable of the third level protection mode will also be turned off; further avoiding the risk of data corruption due to misoperation caused by the developer forgetting to turn off the enable after programming or erasing.

[0069] Figure 3 A schematic diagram of the structure of an on-chip firmware security protection device provided by an embodiment of the present application is shown, and the device includes:

[0070] A generating module, configured to generate a target protection mode corresponding to the protection requirement level of the chip to be processed according to the protection requirement level of the chip to be processed; wherein the target protection mode includes a plurality of sub-protection modes of different levels;

[0071] A detection module, configured to detect the target operation using the target protection mode when a target operation on the chip to be processed is detected;

[0072] The verification module is used to execute the target operation on the chip to be processed when the target operation passes the verification of each sub-protection mode in the target protection mode in sequence.

[0073] The chip to be processed includes a first protection area; the protection requirement level of the chip to be processed is a low-level protection requirement;

[0074] According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including:

[0075] According to the low-level protection requirements of the chip to be processed, a first-level protection mode, a second-level protection mode and a third-level protection mode are generated in the first protection area; wherein the first-level protection mode is register access protection, the second-level protection mode is the overall operation enable protection of the register, and the third-level protection mode is the sub-operation enable protection of the register.

[0076] The chip to be processed includes a first protection area; the register of the chip to be processed includes a plurality of sub-areas, and the protection requirement level of the chip to be processed is a medium protection requirement;

[0077] According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including:

[0078] According to the intermediate-level protection requirements of the chip to be processed, a first-level protection mode, a second-level protection mode, a third-level protection mode and a fourth-level protection mode are generated in the first protection area; wherein the first-level protection mode is register access protection, the second-level protection mode is the overall operation enable protection of the register, the third-level protection mode is the sub-operation enable protection of the register, and the fourth-level protection mode is the sub-area locking protection.

[0079] The chip to be processed includes a first protection area and a second protection area; the protection requirement level of the chip to be processed is a high-level protection requirement;

[0080] According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including:

[0081] According to the high-level protection requirements of the chip to be processed, a first-level protection mode, a second-level protection mode and a third-level protection mode are generated in the first protection area; a fifth-level protection mode is generated in the second protection area; wherein the first-level protection mode is register access protection, the second-level protection mode is the overall operation enable protection of the register, the third-level protection mode is the sub-operation enable protection of the register, and the fifth-level protection mode is the overall area locking protection.

[0082] The chip to be processed includes a first protection area and a second protection area; the protection requirement level of the chip to be processed is a higher level protection requirement;

[0083] According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including:

[0084] According to the higher level protection requirements of the chip to be processed, a first level protection mode, a second level protection mode, a third level protection mode and a fourth level protection mode are generated in the first protection area; a fifth level protection mode is generated in the second protection area; wherein the first level protection mode is register access protection, the second level protection mode is the overall operation enable protection of the register, the third level protection mode is the sub-operation enable protection of the register, the fourth level protection mode is the sub-area locking protection, and the fifth level protection mode is the overall area locking protection.

[0085] When the target operation passes the verification of each sub-protection mode in the target protection mode in sequence, executing the target operation on the chip to be processed includes:

[0086] Reading a first identification bit, a second identification bit, a third identification bit, and a fourth identification bit corresponding to the first level protection mode, the second level protection mode, the third level protection mode, and the fourth level protection mode from the first protection area;

[0087] Reading the fifth identification bit of the fifth level protection mode from the second protection area;

[0088] The first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the fifth identification bit are verified in sequence, and when all the identification bits pass the verification, the target operation is performed on the chip to be processed.

[0089] If any one of the first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the fifth identification bit fails the verification, no subsequent verification is performed, and the target operation is not performed on the chip to be processed.

[0090] like Figure 4 As shown, an embodiment of the present application provides an electronic device for executing the on-chip firmware security protection method in the present application, the device includes a memory, a processor, a bus, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the on-chip firmware security protection method when executing the computer program.

[0091] Specifically, the above-mentioned memory and processor can be general-purpose memory and processor, which are not specifically limited here. When the processor runs the computer program stored in the memory, the above-mentioned on-chip firmware security protection method can be executed.

[0092] Corresponding to the on-chip firmware security protection method in the present application, an embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is run by a processor, the steps of the above-mentioned on-chip firmware security protection method are executed.

[0093] Specifically, the storage medium can be a general storage medium, such as a mobile disk, a hard disk, etc. When the computer program on the storage medium is run, the above-mentioned on-chip firmware security protection method can be executed.

[0094] In the embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. The system embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of systems or units, which can be electrical, mechanical or other forms.

[0095] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0096] In addition, each functional unit in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0097] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0098] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and are not to be understood as indicating or implying relative importance.

[0099] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. They should all be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for on-chip firmware security protection, characterized in that: The method comprises: According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels; When a target operation on the chip to be processed is detected, detecting the target operation using the target protection mode; When the target operation passes the verification of each sub-protection mode in the target protection mode in sequence, the target operation is performed on the chip to be processed.

2. The method according to claim 1, characterized in that The chip to be processed includes a first protection area; the protection requirement level of the chip to be processed is a low-level protection requirement; According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including: According to the low-level protection requirements of the chip to be processed, a first-level protection mode, a second-level protection mode and a third-level protection mode are generated in the first protection area; wherein the first-level protection mode is register access protection, the second-level protection mode is the overall operation enable protection of the register, and the third-level protection mode is the sub-operation enable protection of the register.

3. The method according to claim 1, characterized in that The chip to be processed includes a first protection area; the register of the chip to be processed includes a plurality of sub-areas, and the protection requirement level of the chip to be processed is a medium protection requirement; According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including: According to the intermediate-level protection requirements of the chip to be processed, a first-level protection mode, a second-level protection mode, a third-level protection mode and a fourth-level protection mode are generated in the first protection area; wherein the first-level protection mode is register access protection, the second-level protection mode is the overall operation enable protection of the register, the third-level protection mode is the sub-operation enable protection of the register, and the fourth-level protection mode is the sub-area locking protection.

4. The method according to claim 1, characterized in that: The chip to be processed includes a first protection area and a second protection area; the protection requirement level of the chip to be processed is a high-level protection requirement; According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including: According to the high-level protection requirements of the chip to be processed, a first-level protection mode, a second-level protection mode and a third-level protection mode are generated in the first protection area; a fifth-level protection mode is generated in the second protection area; wherein the first-level protection mode is register access protection, the second-level protection mode is the overall operation enable protection of the register, the third-level protection mode is the sub-operation enable protection of the register, and the fifth-level protection mode is the overall area locking protection.

5. The method according to claim 1, characterized in that: The chip to be processed includes a first protection area and a second protection area; the protection requirement level of the chip to be processed is a higher level protection requirement; According to the protection requirement level of the chip to be processed, a target protection mode corresponding to the protection requirement level is generated; wherein the target protection mode includes a plurality of sub-protection modes of different levels, including: According to the higher level protection requirements of the chip to be processed, a first level protection mode, a second level protection mode, a third level protection mode and a fourth level protection mode are generated in the first protection area; a fifth level protection mode is generated in the second protection area; wherein the first level protection mode is register access protection, the second level protection mode is the overall operation enable protection of the register, the third level protection mode is the sub-operation enable protection of the register, the fourth level protection mode is the sub-area locking protection, and the fifth level protection mode is the overall area locking protection.

6. The method according to claim 5, characterized in that When the target operation passes the verification of each sub-protection mode in the target protection mode in sequence, executing the target operation on the chip to be processed includes: Reading a first identification bit, a second identification bit, a third identification bit, and a fourth identification bit corresponding to the first level protection mode, the second level protection mode, the third level protection mode, and the fourth level protection mode from the first protection area; Reading the fifth identification bit of the fifth level protection mode from the second protection area; The first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the fifth identification bit are verified in sequence, and when all the identification bits pass the verification, the target operation is performed on the chip to be processed.

7. The method according to claim 6, characterized in that The method further comprises: If any one of the first identification bit, the second identification bit, the third identification bit, the fourth identification bit and the fifth identification bit fails the verification, no subsequent verification is performed, and the target operation is not performed on the chip to be processed.

8. A device for on-chip firmware security protection, characterized in that: The device comprises: A generating module, configured to generate a target protection mode corresponding to the protection requirement level of the chip to be processed according to the protection requirement level of the chip to be processed; wherein the target protection mode includes a plurality of sub-protection modes of different levels; A detection module, configured to detect the target operation using the target protection mode when a target operation on the chip to be processed is detected; The verification module is used to execute the target operation on the chip to be processed when the target operation passes the verification of each sub-protection mode in the target protection mode in sequence.

9. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the on-chip firmware security protection method as described in any one of claims 1 to 7 are performed.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which, when executed by a processor, executes the steps of the on-chip firmware security protection method as described in any one of claims 1 to 7.

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