Power supply integrity protection method and device

Abstract

The embodiment of the invention discloses a power supply integrity protection method and device. The power supply integrity protection method comprises the following steps: acquiring a historical read-write request, a historical request processing amount, a current read-write request and a current request processing amount of a target memory; the power supply supplies power to the target memory; according to the historical read-write request, the historical request handling capacity, the current read-write request and the current request handling capacity, predicting the read-write request and the request handling capacity of the target memory at the next moment; and generating risk warning information according to the read-write request and the request processing amount of the target memory at the next moment so as to protect the integrity of the power supply. According to the power supply integrity protection method and device provided by the embodiment of the invention, the power supply integrity can be protected.

Description

Technical Field

[0001] The embodiments of the present invention relate to power supply protection technology, and more particularly to a power supply integrity protection method and device. Background Art

[0002] As a representative of high-speed video memory, high-bandwidth storage is used in many artificial intelligence chips due to its excellent bandwidth, high capacity and other characteristics. It has high requirements for power integrity. If the power integrity is not reliably protected, the effective bandwidth of high-bandwidth storage may be lost by 10% or even more, which will also affect other aspects such as yield. Summary of the invention

[0003] The embodiments of the present invention provide a power integrity protection method and device to protect power integrity.

[0004] In a first aspect, an embodiment of the present invention provides a power integrity protection method, comprising:

[0005] Acquiring historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of a target memory; the power supply supplies power to the target memory;

[0006] Predicting the read and write requests and request processing volume of the target storage at the next moment according to the historical read and write requests, the historical request processing volume, the current read and write requests and the current request processing volume;

[0007] Generate risk warning information according to the read and write requests and the requested processing volume of the target memory at the next moment to protect power integrity.

[0008] Optionally, predicting the read and write requests and the request processing amount of the target memory at the next moment according to the historical read and write requests, the historical request processing amount, the current read and write requests, and the current request processing amount includes:

[0009] Based on the historical read / write requests and the historical request processing volume, determining the time when the current read / write request and the current request processing volume correspond to the historical read / write requests and the historical request processing volume;

[0010] The read / write requests and request processing amount at the next moment of the corresponding moment are used as the read / write requests and request processing amount of the target storage at the next moment.

[0011] Optionally, generating risk warning information according to the read and write requests and the requested processing volume of the target storage at the next moment includes:

[0012] If the read and write requests and the requested processing amount of the target storage at the next moment exceed a preset range, a first risk warning message is generated, where the first risk warning message is a warning message;

[0013] If the read and write requests and the requested processing volume of the target storage at the next moment are within a preset range, a second risk warning message is generated, and the second risk warning message is information that no warning has occurred.

[0014] Optionally, if the read / write request and the requested processing amount of the target storage at the next moment exceed a preset range, first risk warning information is generated, and the first risk warning information is information of a warning, including:

[0015] If the read and write requests and the request processing amount of the target memory at the next moment are lower than a preset first threshold, an overshoot voltage risk warning message is generated;

[0016] If the read and write requests and the request processing amount of the target memory at the next moment are higher than a preset second threshold, an undershoot voltage risk warning message is generated, and the preset first threshold is smaller than the preset second threshold.

[0017] Optionally, the generating of risk warning information to protect power integrity includes:

[0018] If the risk warning information is undershoot voltage risk warning information, throttling control is performed on the read / write request in the direction in which the target memory receives the read / write request to protect power integrity.

[0019] Optionally, the generating of risk warning information to protect power integrity includes:

[0020] If the risk warning information is an overshoot voltage risk warning information, throttling control is performed on the read / write request in the direction in which the target memory returns the read / write request to protect power integrity.

[0021] Optionally, the number of the target memory is at least one, the target memory is a video memory, and the power supply is a power supply of the video memory.

[0022] In a second aspect, an embodiment of the present invention provides a power integrity protection device, including:

[0023] An acquisition module is used to acquire historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of a target memory; the power supply supplies power to the target memory;

[0024] A prediction module, configured to predict the read and write requests and the request processing amount of the target memory at the next moment according to the historical read and write requests, the historical request processing amount, the current read and write requests and the current request processing amount;

[0025] The protection module is used to generate risk warning information according to the read and write requests and the requested processing amount of the target memory at the next moment to protect the power integrity.

[0026] Optionally, the prediction module includes:

[0027] A time determination unit, configured to determine, based on the historical read / write requests and the historical request processing volume, the time corresponding to the current read / write request and the current request processing volume in the historical read / write requests and the historical request processing volume;

[0028] The prediction unit is used to use the read and write requests and request processing amount at the next moment of the corresponding moment as the read and write requests and request processing amount of the target memory at the next moment.

[0029] Optionally, the protection module includes:

[0030] A first protection unit, configured to generate first risk warning information if the read and write requests and the requested processing amount of the target storage at the next moment exceed a preset range, wherein the first risk warning information is information of a warning;

[0031] The second protection unit is used to generate second risk warning information if the read and write requests and the requested processing amount of the target storage at the next moment are within a preset range, and the second risk warning information is information that no warning has occurred.

[0032] The power integrity protection method and device provided by the embodiment of the present invention include: obtaining historical read and write requests, historical request processing volume, current read and write requests and current request processing volume of the target memory; powering the target memory with a power supply; predicting the read and write requests and request processing volume of the target memory at the next moment according to the historical read and write requests, historical request processing volume, current read and write requests and current request processing volume; generating risk warning information according to the read and write requests and request processing volume of the target memory at the next moment to protect power integrity. The power integrity protection method and device provided by the embodiment of the present invention generate risk warning information according to the predicted read and write requests and request processing volume of the target memory at the next moment, if the read and write requests and request processing volume of the target memory at the next moment are lower than the preset first threshold, then generate undershoot voltage risk warning information, and perform throttling control on the read and write requests in the direction where the target memory receives the read and write requests, so as to prevent the power integrity from being affected due to the lack of throttling control, thereby protecting the power integrity. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a flow chart of a power integrity protection method provided by Embodiment 1 of the present invention;

[0034] Figure 2 is a flow chart of a power integrity protection method provided by Embodiment 2 of the present invention;

[0035] Figure 3 is a structural block diagram of a power integrity protection device provided by Embodiment 3 of the present invention;

[0036] Figure 4 is a structural block diagram of another power integrity protection device provided by Embodiment 3 of the present invention;

[0037] Figure 5 This is a structural block diagram of a connection between HBM and MC provided in Embodiment 3 of the present invention;

[0038] Figure 6 It is a structural block diagram of a DFI monitor and a risk pattern detector connected according to a third embodiment of the present invention;

[0039] Figure 7 This is a structural block diagram of a risk processor connected to a bus provided by Embodiment 3 of the present invention. DETAILED DESCRIPTION

[0040] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0041] Embodiment 1

[0042] Figure 1 1 is a flow chart of a power integrity protection method provided by Embodiment 1 of the present invention. This embodiment is applicable to aspects such as protecting the power integrity of a memory. The method can be executed by a power integrity protection device. The device can be integrated in an electronic device such as a computer. The electronic device can be implemented in the form of software and / or hardware. The method specifically includes the following steps:

[0043] Step 110: Obtain historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of the target memory; and supply power to the target memory.

[0044] The number of target memories is at least one and may be multiple. The target memory may be a video memory, and the power supply is a power supply of the video memory. The historical read and write requests include historical read requests, historical write requests, and historical read and write requests, and the historical request processing volume includes historical read request processing volume, historical write request processing volume, and historical read and write request processing volume. The current read and write requests include current read requests, current write requests, and current read and write requests, and the current request processing volume includes current read request processing volume, current write request processing volume, and current read and write request processing volume. The power integrity protection device is connected in communication with the target memory to obtain the historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of the target memory.

[0045] Step 120: predict the read and write requests and request processing volume of the target storage at the next moment based on the historical read and write requests, the historical request processing volume, the current read and write requests, and the current request processing volume.

[0046] Specifically, based on historical read and write requests and historical request processing volume, determine the times corresponding to the current read and write requests and current request processing volume in the historical read and write requests and historical request processing volume, and use the read and write requests and request processing volume at the next moment of the corresponding moment as the read and write requests and request processing volume of the target storage at the next moment.

[0047] Step 130 : Generate risk warning information according to the read and write requests and the requested processing volume of the target memory at the next moment to protect the power integrity.

[0048] Specifically, if the read / write request and request processing amount of the target memory at the next moment exceed the preset range, a first risk warning message is generated, and the first risk warning message is the message of the occurrence of a warning; if the read / write request and request processing amount of the target memory at the next moment are within the preset range, a second risk warning message is generated, and the second risk warning message is the message of no occurrence of a warning. Exemplarily, if the read / write request and request processing amount of the target memory at the next moment are lower than the preset first threshold, an undershoot voltage risk warning message is generated, and the read / write request is throttled in the direction where the target memory receives the read / write request to protect the power integrity.

[0049] It should be noted that, in this embodiment, the size of the preset range and the preset first threshold can be set according to actual protection requirements and are not limited here.

[0050] The power integrity protection method provided by the present embodiment includes: obtaining historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of the target memory; powering the target memory with a power supply; predicting the read and write requests and request processing volume of the target memory at the next moment according to the historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume; generating risk warning information according to the read and write requests and request processing volume of the target memory at the next moment to protect power integrity. The power integrity protection method provided by the present embodiment generates risk warning information according to the predicted read and write requests and request processing volume of the target memory at the next moment, and if the read and write requests and request processing volume of the target memory at the next moment are lower than a preset first threshold, an undershoot voltage risk warning information is generated, and throttling control is performed on the read and write requests in the direction where the target memory receives the read and write requests to prevent the power integrity from being affected due to the lack of throttling control, thereby protecting the power integrity.

[0051] Embodiment 2

[0052] Figure 2 1 is a flow chart of a power integrity protection method provided by Embodiment 2 of the present invention. This embodiment is applicable to aspects such as protecting the power integrity of a memory. The method can be executed by a power integrity protection device. The device can be integrated in an electronic device such as a computer. The electronic device can be implemented in the form of software and / or hardware. The method specifically includes the following steps:

[0053] Step 210: Obtain historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of the target memory; and supply power to the target memory.

[0054] The number of target memories is at least one and may be multiple. The target memory may be a video memory, and the power supply is a power supply of the video memory. The historical read and write requests include historical read requests, historical write requests, and historical read and write requests, and the historical request processing volume includes historical read request processing volume, historical write request processing volume, and historical read and write request processing volume. The current read and write requests include current read requests, current write requests, and current read and write requests, and the current request processing volume includes current read request processing volume, current write request processing volume, and current read and write request processing volume. The power integrity protection device is connected in communication with the target memory to obtain the historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of the target memory.

[0055] Step 220: Based on the historical read / write requests and the historical request processing volume, determine the time when the current read / write request and the current request processing volume correspond to the historical read / write requests and the historical request processing volume.

[0056] Specifically, if the read / write request and request processing volume at a certain time before the current time, such as time k, are the same as the current read / write request and current request processing volume, then the corresponding time is determined to be time k. If the current read / write request and current request processing volume have no corresponding time in the historical read / write request and historical request processing volume, then the time in the historical read / write request and historical request processing volume that is closest to the current read / write request and current request processing volume is used as the corresponding time.

[0057] Step 230: The read / write request and request processing amount at the next moment of the corresponding moment are used as the read / write request and request processing of the target storage at the next moment.

[0058] Specifically, if the read / write requests and request processing volume at a certain moment before the current moment, such as moment k, are the same as the current read / write requests and request processing volume, then the read / write requests and request processing volume at moment k+1 are used as the read / write requests and request processing at the next moment of the current moment.

[0059] Step 240: If the read and write requests and the request processing amount of the target memory at the next moment are lower than a preset first threshold, an overshoot voltage risk warning message is generated.

[0060] The read / write request and request processing amount of the target memory at the next moment is lower than the preset first threshold, which may be that the total amount of the read / write request and request processing amount is lower than the preset first threshold. If the read / write request and request processing amount of the target memory at the next moment is lower than the preset first threshold, it means that the read / write request and request processing amount of the target memory at the next moment are too low, and there is a risk of overshoot voltage, so an overshoot voltage risk warning message is generated.

[0061] Step 250: If the read and write requests and the requested processing volume of the target memory at the next moment are higher than the preset second threshold, an undershoot voltage risk warning message is generated, and the preset first threshold is smaller than the preset second threshold.

[0062] Wherein, the read / write request and request processing amount of the target memory at the next moment is higher than the preset second threshold value, and the total amount of the read / write request and request processing amount is higher than the preset second threshold value. If the read / write request and request processing amount of the target memory at the next moment is higher than the preset second threshold value, it means that the read / write request and request processing amount of the target memory at the next moment are too high, and there is a risk of undershoot voltage, so an undershoot voltage risk warning message is generated.

[0063] In addition, if the read and write requests and the requested processing volume of the target storage at the next moment are within a preset range, information indicating that no warning has occurred is generated.

[0064] Step 260: If the risk warning information is an undershoot voltage risk warning information, throttling control is performed on the read and write requests in the direction in which the target memory receives the read and write requests to protect power integrity.

[0065] Specifically, throttling control is performed on the read and write requests in the direction in which the target memory receives the read and write requests, so as to prevent the target memory from having too many read and write requests and request processing volume at the next moment and affecting the power integrity of the target memory.

[0066] Step 270: If the risk warning information is an overshoot voltage risk warning information, throttling control is performed on the read and write requests in the direction in which the target memory returns the read and write requests to protect power integrity.

[0067] Specifically, throttling control is performed on the read and write requests in the direction in which the target memory returns the read and write requests, so as to prevent the read and write requests and request processing amount of the target memory at the next moment from being too low and affecting the power integrity of the target memory.

[0068] It should be noted that, in this embodiment, the preset range and the sizes of each preset threshold can be set according to actual protection requirements and are not limited here.

[0069] The power integrity protection method provided in this embodiment generates warning information based on the predicted read and write requests and request processing of the target memory at the next moment. If the read and write requests and request processing volume of the target memory at the next moment are lower than a preset first threshold, an overshoot voltage risk warning information is generated, and throttling control is performed on the read and write requests in the direction in which the target memory returns the read and write requests. If the read and write requests and request processing volume of the target memory at the next moment are higher than a preset second threshold, an undershoot voltage risk warning information is generated, and throttling control is performed on the read and write requests in the direction in which the target memory receives the read and write requests, so as to prevent the occurrence of overshoot voltage risks and undershoot voltage risks and protect the power integrity.

[0070] Embodiment 3

[0071] Figure 3 is a structural block diagram of a power integrity protection device provided by Embodiment 3 of the present invention. Figure 3 The power integrity protection device includes: an acquisition module 310, a prediction module 320 and a protection module 330; wherein the acquisition module 310 is used to acquire the historical read and write requests, the historical request processing volume, the current read and write requests and the current request processing volume of the target memory; the power supply supplies power to the target memory; the prediction module 320 is used to predict the read and write requests and the request processing volume of the target memory at the next moment according to the historical read and write requests, the historical request processing volume, the current read and write requests and the current request processing volume; the protection module 330 is used to generate risk warning information according to the read and write requests and the request processing volume of the target memory at the next moment to protect the power integrity.

[0072] Based on the above implementation, the prediction module 320 includes:

[0073] A time determination unit, used to determine the time corresponding to the current read / write request and the current request processing amount in the historical read / write request and the historical request processing amount based on the historical read / write request and the historical request processing amount;

[0074] The prediction unit is used to use the read / write request and request processing amount at the next moment of the corresponding moment as the read / write request and request processing amount of the target memory at the next moment.

[0075] In one embodiment, the protection module 330 includes:

[0076] A first protection unit, configured to generate first risk warning information if the read and write requests and the requested processing amount of the target storage at the next moment exceed a preset range, wherein the first risk warning information is information of a warning;

[0077] The second protection unit is used to generate second risk warning information if the read and write requests and the requested processing amount of the target memory at the next moment are within a preset range, and the second risk warning information is information that no warning has occurred.

[0078] Optionally, the above-mentioned first protection unit includes: a first information generating subunit and a second information generating subunit; wherein the first information generating subunit is used to generate an undershoot voltage risk warning message if the read and write requests and request processing volume of the target memory at the next moment are lower than a preset first threshold; the second information generating subunit includes generating an overshoot voltage risk warning message if the read and write requests and request processing volume of the target memory at the next moment are higher than a preset second threshold, and the preset first threshold is less than the preset second threshold.

[0079] Optionally, the protection module 330 includes: a first throttling control unit, which is used to throttle the read and write requests in the direction where the target memory receives the read and write requests if the risk warning information is undershoot voltage risk warning information, so as to protect power integrity.

[0080] Optionally, the protection module 330 includes: a second throttling control unit, which is used to throttle the read and write requests in the direction in which the target memory returns the read and write requests if the risk warning information is an overshoot voltage risk warning information, so as to protect the power integrity.

[0081] Figure 4 is a structural block diagram of another power integrity protection device provided by Embodiment 3 of the present invention, Figure 5 is a structural block diagram of a connection between HBM and MC provided in Embodiment 3 of the present invention, Figure 6 is a structural block diagram of a DFI monitor and a risk pattern detector connected to each other provided by Embodiment 3 of the present invention, Figure 7 FIG. 1 is a block diagram of a risk processor connected to a bus according to Embodiment 3 of the present invention. Figure 4-Figure 7 The power integrity protection system includes a DFI (DDR PHY Interface, double rate physical layer interface) monitor 10, a risk mode detector 20 and a risk processor 30. The load (number of instructions) between a specific MC (memory controller) and an HBM PHY (High Bandwidth Memory Physical Interface) is collected through the DFI protocol, and the sampling period is configurable. The DFI monitor 10 (equivalent to the above-mentioned acquisition module) collects DFI events, i.e., read and write requests, and summarizes them to the risk mode detector, and then transmits the detection results to the risk processor, and takes protection measures according to the situation. Each HBM channel of the HBM corresponds to an independent DFI monitor, and each DFI monitor supports statistics of multiple DFI instructions (read, write, read + write), and each DFI instruction has an independent counter. Each DFI monitor supports a configurable statistical window (such as 128, 256, 512, 1024 cycles), supports infinite loop periodic statistics, and supports shadow cache. The collected information of the previous cycle is pushed into the shadow cache, and the counter is reset to start the statistics of the new cycle. At the end of each DFI monitor statistical cycle, the risk mode detector 20 (equivalent to the above prediction module) reads the data in the shadow cache of the DFI monitor, accumulates the values ​​of different instruction counters in the DFI monitor, selects one of the instruction counters through the selector, updates the historical DFI data, in which the DFI data of the past N-1 cycles are stored (N is an integer greater than 1, and the specific value is configured according to the design requirements), performs risk warning matching, and generates risk prompts. The risk processor 30 (equivalent to the above protection module) performs protection according to the risk prompt and the bus unreturned request, generates the first risk warning information or the second risk warning information, the second risk warning information is the information of the warning (the corresponding instruction is 1), and the second risk warning information is the information of the non-warning (the corresponding instruction is 0). When the first risk warning information is the undershoot voltage risk warning information, the control logic is inserted in the direction of the target memory receiving the read and write request, and the read and write request is throttled; when the first risk warning information is the overshoot voltage risk warning information, the control logic is inserted in the direction of the target memory returning the read and write request, and the read and write request is throttled to protect the power integrity.

[0082] The power integrity protection device provided in this embodiment and the power integrity protection method provided in any embodiment of the present invention belong to the same inventive concept and have corresponding beneficial effects. For technical details not detailed in this embodiment, please refer to the power integrity protection method provided in any embodiment of the present invention.

[0083] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A power integrity protection method, characterized in that: include: Obtain historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of the target storage; The power supply supplies power to the target memory; Predicting the read and write requests and request processing volume of the target storage at the next moment according to the historical read and write requests, the historical request processing volume, the current read and write requests and the current request processing volume; Generate risk warning information according to the read and write requests and the requested processing volume of the target memory at the next moment to protect power integrity.

2. The power integrity protection method according to claim 1, characterized in that: The predicting the read / write requests and request processing amount of the target memory at the next moment according to the historical read / write requests, the historical request processing amount, the current read / write requests and the current request processing amount includes: Based on the historical read / write requests and the historical request processing volume, determining the time when the current read / write request and the current request processing volume correspond to the historical read / write requests and the historical request processing volume; The read / write requests and request processing amount at the next moment of the corresponding moment are used as the read / write requests and request processing amount of the target storage at the next moment.

3. The power integrity protection method according to claim 1, characterized in that: Generating risk warning information according to the read and write requests and the requested processing volume of the target storage at the next moment includes: If the read and write requests and the requested processing amount of the target storage at the next moment exceed a preset range, a first risk warning message is generated, where the first risk warning message is a warning message; If the read and write requests and the requested processing volume of the target storage at the next moment are within a preset range, a second risk warning message is generated, and the second risk warning message is information that no warning has occurred.

4. The power integrity protection method according to claim 3, characterized in that: If the read / write request and the requested processing amount of the target storage at the next moment exceed a preset range, a first risk warning message is generated, and the first risk warning message is the information of the occurrence of the warning, including: If the read and write requests and the requested processing amount of the target memory at the next moment are lower than a preset first threshold, an overshoot voltage risk warning message is generated; If the read and write requests and the request processing amount of the target memory at the next moment are higher than a preset second threshold, an undershoot voltage risk warning message is generated, and the preset first threshold is smaller than the preset second threshold.

5. The power integrity protection method according to claim 1, characterized in that: The risk warning information is generated to protect the power integrity, including: If the risk warning information is undershoot voltage risk warning information, throttling control is performed on the read / write request in the direction in which the target memory receives the read / write request to protect power integrity.

6. The power integrity protection method according to claim 1, characterized in that: The risk warning information is generated to protect the power integrity, including: If the risk warning information is an overshoot voltage risk warning information, throttling control is performed on the read / write request in the direction in which the target memory returns the read / write request to protect power integrity.

7. The power integrity protection method according to claim 1, characterized in that: The number of the target memory is at least one, the target memory is a video memory, and the power supply is a power supply of the video memory.

8. A power integrity protection device, characterized in that: include: An acquisition module, used to acquire historical read and write requests, historical request processing volume, current read and write requests, and current request processing volume of a target storage; The power supply supplies power to the target memory; A prediction module, configured to predict the read and write requests and the request processing amount of the target memory at the next moment according to the historical read and write requests, the historical request processing amount, the current read and write requests and the current request processing amount; The protection module is used to generate risk warning information according to the read and write requests and the requested processing amount of the target memory at the next moment to protect the power integrity.

9. The power integrity protection device according to claim 8, characterized in that: The prediction module comprises: A time determination unit, configured to determine, based on the historical read / write requests and the historical request processing volume, the time corresponding to the current read / write request and the current request processing volume in the historical read / write requests and the historical request processing volume; The prediction unit is used to use the read and write requests and request processing amount at the next moment of the corresponding moment as the read and write requests and request processing amount of the target memory at the next moment.

10. The power integrity protection device according to claim 8, characterized in that: The protection module comprises: A first protection unit, configured to generate first risk warning information if the read and write requests and the requested processing amount of the target storage at the next moment exceed a preset range, wherein the first risk warning information is information of a warning; The second protection unit is used to generate second risk warning information if the read and write requests and the requested processing amount of the target storage at the next moment are within a preset range, and the second risk warning information is information that no warning has occurred.

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