Method for semiconductor design verification, database system and related products thereof

Abstract

The invention provides a method for semiconductor design verification, a database system and related products thereof. The method comprises the following steps: identifying layout fragments with violation errors in a semiconductor layout verification process and determining fragment information of the layout fragments; performing pattern classification on the layout fragment by utilizing geometric clustering so as to determine a pattern category of the layout fragment; the mode category and the fragment information are stored in a database in an associated mode; extracting the fragment information from the database according to the mode category; and assembling the layout segments into a test matrix based on the segment information for optimizing semiconductor design verification. According to the scheme, the accuracy and efficiency of error detection are effectively improved, and the efficiency and reliability of design verification are enhanced.

Description

Technical Field

[0001] The present disclosure generally relates to the field of semiconductors. More specifically, the present disclosure relates to a method, an electronic device, a database system, a database device, an electronic device, and a computer-readable storage medium for semiconductor design verification. Background Art

[0002] There are several major technical challenges in the field of semiconductor design verification, especially in the design rule checking (DRC), photolithography process correction (OPC) and OPC verification (OPCV) processes. These challenges affect the efficiency and accuracy of semiconductor manufacturing, thus having a significant impact on the entire industry.

[0003] First, in some cases, the design verification process may generate a large number of violations or errors. Current technology lacks an effective way to handle these similar violations or errors. This leads to a huge amount of data, making verification, review, and processing extremely complex and time-consuming. For the design and verification team, manually handling these large numbers of violations or errors is not only inefficient, but also prone to errors.

[0004] Secondly, what is missing from the prior art is the ability to compare violations or errors across different designs and physical verification runs. This comparison is critical to identifying and resolving common issues that arise under different design conditions, such as different configurations, decks, or recipes. The lack of this comparison mechanism limits the ability to learn from experience and improve the design.

[0005] Finally, there is currently no automated or easy way to extract, store, and retrieve relevant test cases, and being able to quickly access and reuse previous test cases is critical to accelerating the design process and improving design quality. The lack of this capability increases the length and complexity of the design cycle and reduces overall efficiency.

[0006] In view of this, there is an urgent need to provide an innovative semiconductor design verification solution to effectively handle a large amount of illegal or erroneous data and significantly improve the efficiency and accuracy of data processing, thereby improving the overall performance and efficiency of the semiconductor design verification process. Summary of the invention

[0007] In order to at least solve one or more of the technical problems mentioned above, the present disclosure proposes a solution for semiconductor design verification in multiple aspects.

[0008] In a first aspect, the present disclosure provides a method for semiconductor design verification, comprising: identifying layout fragments that have violation errors during the semiconductor layout verification process and determining their fragment information; using geometric clustering to perform pattern classification on the layout fragments to determine the pattern category of the layout fragments; storing the pattern category and the fragment information in a database in association with each other; extracting the fragment information from the database according to the pattern category; and assembling the layout fragments into a test matrix based on the fragment information for optimizing semiconductor design verification.

[0009] In some embodiments, the violation errors include size violations and / or configuration errors, and wherein identifying layout fragments where violation errors occur during a semiconductor layout verification process includes: running a verification tool on the semiconductor layout to detect layout areas where size violations and / or configuration errors occur; and identifying the layout areas where size violations and / or configuration errors occur as layout fragments where violation errors occur.

[0010] In some embodiments, the fragment information includes violation information of the location, type and / or extent of the violation error.

[0011] In some embodiments, using geometric clustering to classify the layout fragments includes using the fragment information to classify the layout fragments to obtain the pattern category; and assigning a unique pattern number to the pattern category to achieve association between the two.

[0012] In some embodiments, using geometric clustering to perform pattern classification on the layout fragments includes: in response to identifying multiple layout fragments, performing pattern classification on the multiple layout fragments respectively to determine their respective pattern categories; clustering layout fragments with the same pattern category, and assigning a unique pattern to the same pattern category to achieve association between the two; and for a layout fragment with a pattern category different from that of other layout fragments, assigning a unique pattern number to its pattern category to achieve association between the two.

[0013] In some embodiments, wherein the database is a graph database or a non-relational database, storing the pattern category and the fragment information in the database in association with each other includes: storing the unique pattern number and the layout information in the graph database or the non-relational database in association with each other.

[0014] In some embodiments, extracting the fragment information from the database according to the pattern category includes extracting multiple fragment information of corresponding multiple layout fragments from the database according to multiple unique pattern numbers, and assembling the layout fragments into a test matrix based on the fragment information includes arranging the multiple layout fragments using the multiple fragment information to assemble into the test matrix.

[0015] In some embodiments, assembling the layout snippets into a test matrix based on the snippet information further comprises: using the test matrix in conjunction with one or more verification tools to provide additional testing and analysis.

[0016] In a second aspect, the present disclosure provides an electronic device for semiconductor design verification, comprising: a processor; a memory on which program instructions for semiconductor design verification are stored, and when the program instructions are executed by the processor, the method described in the first aspect and its multiple embodiments is implemented.

[0017] In a third aspect, the present disclosure provides a computer-readable storage medium having program instructions for semiconductor design verification stored thereon, which, when executed by a processor, implement the method according to the first aspect and its multiple embodiments.

[0018] In a fourth aspect, the present disclosure provides a database system for semiconductor design verification, comprising: a database configured to store pattern categories and fragment information of multiple layout fragments of a semiconductor, wherein the layout fragments are layout fragments with violation errors identified during a semiconductor layout verification process, and the pattern categories are determined after pattern classification of the layout fragments using geometric clustering; and a graphical user interface configured to assist a user in selecting pattern categories and locating fragment information from the database, so as to assemble the layout fragments into a test matrix using the fragment information.

[0019] In some embodiments, the violation error includes a size violation and / or a configuration error of the layout fragment.

[0020] In some embodiments, each of the mode categories is assigned a unique mode number and is associated with the layout fragment and the fragment information.

[0021] In some embodiments, the database is configured to store historical pattern numbers and / or new pattern numbers, wherein the historical pattern numbers include unique pattern numbers obtained through the geometric clustering in past semiconductor layout verifications, and the new pattern numbers include unique pattern numbers obtained through the geometric clustering in recent semiconductor layout verifications and have not been stored in the pattern database.

[0022] In some embodiments, the graphical user interface is further configured to assist a user in reviewing pattern categories and fragment information stored in a database to implement a handling process, wherein the handling process is used to determine whether to mark violations or errors in the fragment information as ignorable or non-ignorable.

[0023] In some embodiments, in response to a violation or error being marked as ignorable, no further action is taken; and in response to the violation or error being marked as non-ignorable, further action is taken to resolve the violation or error.

[0024] In some embodiments, the database is further configured to store the results of the treatment process for subsequent data analysis and improvement of the validation tool.

[0025] In a fifth aspect, the present disclosure provides a database device for semiconductor design verification, comprising: a processor; and a database system according to the fourth aspect and its multiple embodiments, wherein when the database system is executed by the processor, it is used to assist the semiconductor design verification.

[0026] According to the method, electronic device, database system, database equipment and computer-readable storage medium for semiconductor design verification as discussed above, the disclosed embodiment can effectively optimize the semiconductor design verification process and improve the accuracy and efficiency of error detection by identifying the layout fragments with violation errors in the semiconductor layout verification process and determining their fragment information, using geometric clustering to classify the layout fragments, storing the pattern categories and fragment information in a database in association, extracting fragment information according to the pattern categories, and assembling the layout fragments into a test matrix based on the fragment information. Further, by running a verification tool on the semiconductor layout to detect size violations and / or configuration errors, and identifying the layout areas of violations or errors as layout fragments, potential design problems can be more accurately located and identified. In addition, by storing the pattern categories and fragment information in a database (such as a database or a non-relational database) in association, the present application can provide more flexible and efficient data management and retrieval capabilities. Finally, by using a graphical user interface to assist users in reviewing pattern categories and fragment information and implementing a disposal process, the present application can further enhance the efficiency and reliability of semiconductor design verification while ensuring that violations or errors are properly handled. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0028] Figure 1 is a simplified flow chart illustrating a method for semiconductor design verification according to some embodiments of the present disclosure;

[0029] Figure 2 is a detailed flow chart showing a method for semiconductor design verification according to some embodiments of the present disclosure;

[0030] Figure 3 is a flowchart illustrating a process for performing database storage according to some embodiments of the present disclosure;

[0031] Figure 4 is a flowchart showing relevant operations performed at a database according to some embodiments of the present disclosure;

[0032] Figure 5 is a schematic diagram showing a usage scenario of a test matrix according to some embodiments of the present disclosure;

[0033] Figure 6 is an exemplary structural block diagram showing a database system according to some embodiments of the present disclosure; and

[0034] Figure 7 is a block diagram showing an exemplary structure of a database device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0036] It should be understood that the terms "include" and "comprising" used in the specification and claims of the present disclosure indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0037] It should also be understood that the terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the disclosure. As used in this disclosure and claims, the singular forms of "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in this disclosure and claims refers to any combination of one or more of the associated listed items and all possible combinations, including these combinations.

[0038] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" may be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0039] As mentioned above, in the current prior art, the design verification process often faces the challenge of dealing with a large amount of violation or error data, which is often complex and complicated, making the verification, review and processing process extremely time-consuming and inefficient. In addition, the prior art lacks an effective mechanism to compare violations or errors in different designs and physical verification runs, limiting the ability to learn from experience and improve designs. At the same time, there is also a lack of an automated or easy way to extract, store and retrieve relevant test cases, which increases the length and complexity of the design cycle and reduces overall efficiency.

[0040] In view of this, the solution of the present application proposes an innovative processing flow for effectively identifying and managing illegal or erroneous data generated during the semiconductor layout verification process. The solution involves accurately identifying problematic layout fragments and obtaining relevant information, and then using geometric clustering technology to effectively classify these fragments to determine their pattern categories. Then, these pattern categories and fragment information are associatively stored in a database for future retrieval and analysis. Finally, by extracting this information from the database and assembling it into a test matrix, the present application can provide an optimized solution for the semiconductor design verification process.

[0041] Through the scheme of the present application, the efficiency and accuracy of processing illegal or erroneous data can be significantly improved, thereby optimizing the entire semiconductor design verification process. This method can not only effectively reduce the complexity and time-consuming of data processing, but also improve the accuracy of illegal or error detection. In addition, by storing data in an efficient database system, such as a database or a non-relational database, the present application provides more flexible and efficient data management and retrieval capabilities, thereby accelerating the design process and improving the quality of the design. Through this method, the present application not only improves the efficiency of design verification, but also enhances the performance and efficiency of the entire semiconductor manufacturing process.

[0042] The specific implementation of the present disclosure is described in detail below with reference to the accompanying drawings.

[0043] Figure 1 is a simplified flow chart illustrating a method 100 for semiconductor design verification according to some embodiments of the present disclosure. Figure 1As shown in , the method 100 includes, at step S102, identifying a layout segment where a violation error occurs during the semiconductor layout verification process and determining its segment information. In one embodiment, this step involves running a verification tool on the semiconductor layout to detect layout areas with size violations and / or configuration errors, and then identifying these areas as layout segments where violation errors occur. By accurately capturing the specific location, type, and severity of violations and errors, a foundation is laid for the next step of processing.

[0044] In one embodiment, the above fragment information may include the severity level associated with the violation error, the specific results of the design rule check (DRC), the photolithography process correction (OPC) parameters, and the impact that these violations or errors may have on the semiconductor manufacturing process. In addition, these fragment information may be further refined to include metadata such as design version, manufacturing process parameters, OPCV rule check name and key dimensions to enhance its usability and practicality in data management and retrieval. Through such detailed records, rich contextual information can be provided for subsequent steps, ensuring efficient management and rapid retrieval in the database, and providing strong support for the verification and improvement work of the present disclosure.

[0045] Next, at step S104, geometric clustering is used to classify the layout fragments to determine the pattern category of the layout fragments. In one embodiment, the pattern classification can be based on the shape, size, and arrangement of the pattern to ensure that the layout fragments can be accurately classified into pattern categories. In one embodiment, the aforementioned geometric clustering can compare and cluster the information of the layout fragments to generate a pattern category with a unique pattern number. Specifically, this step involves assigning a unique pattern number to the pattern category and realizing the association between the pattern and the fragment information. In addition, with respect to the aforementioned geometric clustering, its operating principle is to compare and cluster the pattern fragments using fixed geometric parameters, such as pattern radius, direction, and fuzziness of polygon edges. Edge fuzziness represents the range of differences that allow different patterns to be classified into the same category. Through this clustering method, the disclosed scheme can identify and cluster violation errors that occur in common in different designs or physical verification runs, thereby improving the efficiency and accuracy of data processing. In addition, the clustering method disclosed in the present invention can efficiently manage known patterns (or historical patterns) and new patterns through the structuring of the database (described later), and support rapid retrieval and matching of pattern data, which can significantly accelerate the design verification process and improve design quality.

[0046] After determining the pattern category of the layout fragment, in step S106, the pattern category and the fragment information are stored in a database in association. In one embodiment, the process may include assigning a pattern number to each unique pattern, and the pattern number may correspond to a specific fragment information. Depending on different application scenarios, the fragment information may include design versions, manufacturing process parameters, and related OPCV rule check names. In terms of application, the database of the present application can not only store historical data (including pattern numbers and fragment information that have been previously identified and stored), but can also effectively handle the addition of new pattern numbers and fragment information, making the overall data organization, storage, and retrieval more efficient.

[0047] Thereafter, at step S108, the fragment information is extracted from the database according to the pattern category. In one embodiment, this step may first involve using a previously determined pattern category (such as a pattern number) as a key index to quickly locate all relevant fragment information corresponding to the pattern category in the database. As an example, the above-mentioned fragment information may include, but is not limited to, design rule check results, lithography process correction parameters, OPCV rule check names, and severity levels associated with violation errors. Furthermore, advanced query algorithms can be used to efficiently retrieve and extract accurate fragment information related to a specified pattern category from a huge database. In addition, during the extraction process, the system can filter and sort the extracted information according to the needs of the implementation, such as prioritizing according to the severity level of the violation error or the design version, so as to ensure that the most critical data can be processed efficiently and in a targeted manner in subsequent processing steps.

[0048] Finally, at step S110, the layout fragments are assembled into a test matrix based on the fragment information to optimize the semiconductor design verification. In one embodiment, this step may include integrating and analyzing the extracted fragment information to construct a test matrix that comprehensively reflects the various violation error modes present in the semiconductor design verification process. As an example, the construction of the test matrix (or "Clip Matrix", fragment matrix) of the present application can be based on factors such as the geometric characteristics of the layout fragments, the violation error types, and their distribution in the design. During the construction process, the layout fragments of different modes can be properly organized and arranged to form a comprehensive test scenario that reflects various possible errors. In addition, the test matrix can also include test cases for specific error modes, as well as expected optimization measures and expected effects. Through this assembly method of the present application, the test matrix can not only provide a comprehensive perspective to observe and analyze layout errors, but also provide an effective reference basis for design verification, thereby significantly improving the quality and verification efficiency of semiconductor design.

[0049] By implementing Figure 1The method 100 shown in the present application can achieve efficient data processing and accurate design verification optimization. Specifically, by identifying and determining the fragment information of the layout fragment of the violation error, the violation error occurring in the semiconductor layout verification process can be quickly and accurately identified, providing key preliminary data for subsequent steps. Further, the pattern classification of the layout fragments using geometric clustering not only improves the efficiency of data classification, but also can more accurately identify and handle specific types of design problems through accurate pattern classification. In addition, storing the pattern category and the fragment information in the database in association provides a powerful data management capability, so that historical and new fragment information can be efficiently organized and retrieved, thereby improving the efficiency of overall data processing. Further, extracting the fragment information from the database according to the pattern category can be achieved through an efficient query algorithm, ensuring the rapid and accurate extraction of the required data, and providing strong support for subsequent data processing and analysis. In addition, assembling the layout fragments into a test matrix based on the fragment information not only helps to comprehensively analyze and understand the error mode in the design, but also can provide a practical reference basis for optimizing semiconductor design verification, thereby significantly improving the design quality and the efficiency of the verification process. In summary, through the combined application of the aforementioned multiple steps, the solution of the present application provides significant technical improvements in data processing efficiency, accuracy and design verification optimization.

[0050] Figure 2 is a detailed flow chart showing a method 200 for semiconductor design verification according to some embodiments of the present disclosure. Figure 2 As shown, in step S202, a verification tool is run on the semiconductor layout to detect layout areas with size violations and / or configuration errors. Then, in step S204, the layout areas with size violations and / or configuration errors are identified as layout fragments where violation errors occur. In one embodiment, the function of the aforementioned verification tool is to scan the layout to detect any areas that may violate size specifications or configuration settings. In some scenarios, this may involve dimensional measurement of the layout, spatial layout checking, and electrical connectivity testing. The present disclosure can provide a solid foundation for the entire design verification process by accurately identifying those areas (i.e., layout fragments) that require further analysis.

[0051] In step S206, the fragment information of the layout fragment is determined. Specifically, this step concretizes the detected problem area into a clearly defined layout fragment. It can be understood that this is not only an identification process, but also includes classifying and recording the error type, location, and the importance of possible impact (such as the degree of violation error). In some embodiments, the fragment information here may include the collected geometric data of the fragment, the relevant design rules, the nature of the violation, and other key parameters that may affect manufacturing and performance. This fragment information can directly affect the quality of pattern classification and database retrieval in subsequent steps.

[0052] Thereafter, at step S208, the fragment information collected in the previous step is used to perform pattern classification on the layout fragments to obtain pattern categories. In some embodiments, the aforementioned pattern classification may be a classification according to different error patterns. In this case, the classification process of the present application may not only be based on the physical properties of the fragments, but may also consider the environment ("context" or "setting") in the design, such as the frequency of errors and their performance in different manufacturing processes. The result of the classification is that the layout fragments are effectively organized into different pattern categories, so that a systematic error pattern library can be established.

[0053] Then, the process proceeds to step S210. At this step, a unique pattern number can be assigned or given to each pattern category to achieve the association between the two. By assigning a unique pattern number, the necessary identification can be provided for the retrieval and reference of the pattern in the database. This step ensures that a clear correspondence is established between the pattern category and the related fragment information, thereby facilitating the structure of the database and the retrieval of subsequent steps. At step S212, the pattern number and the fragment information are stored in the database in association. As mentioned above, in order to achieve effective management, retrieval and editing and updating of data, the present application proposes structured management in the database, such as including the management of known or historical patterns and new patterns. In one embodiment, the database of the present application can use a predefined data structure, such as a table or a collection to store entries representing different classification patterns, which can contain features, tags and metadata. To this end, the known pattern is labeled when the data is entered into the database, and is retrieved by querying based on the aforementioned pattern number. Based on this, the geometric (or pattern) classification algorithm can use these stored pattern data for prediction or comparison. After the new pattern is subjected to feature extraction, the extracted features and the pattern identifier (ie, pattern number) can be associated and stored in a database.

[0054] In some application scenarios, pattern annotation can also be performed during the associative storage in the database. The pattern annotation process can add rich pattern information, such as design version, manufacturing process parameters, OPCV rule check name and key dimension metadata to enhance the understanding and practicality of the identified layout fragments. According to different application requirements, the annotation process can be semi-automatic, fully automatic or assisted by the (pattern) database system of the present application. In some scenarios, when the annotation process is combined with automated tools and manual intervention (such as the aforementioned semi-automatic or assisted methods), accurate and comprehensive pattern annotations can be further ensured.

[0055] Then, in step S214, multiple fragment information of the corresponding multiple layout fragments are extracted from the database according to the multiple unique pattern numbers. In one embodiment, the aforementioned extraction operation may involve using the unique pattern number as a key index to quickly locate the detailed layout fragment information associated therewith in the database. As mentioned above, these fragment information may include but are not limited to the specific violation type associated with the layout fragment, the severity level of the violation, the design rule check results involved and / or the possible impact on the semiconductor manufacturing process, etc. Further, the extracted fragment information will support the geometric feature analysis of the pattern to ensure efficient and accurate assembly into a test matrix for subsequent steps. In addition, the scheme of the present application can also screen and sort these proposed fragment information according to the needs of implementation, so that the most critical data can be processed in a targeted manner, thereby optimizing the subsequent verification process and improving the design quality. In this way, the efficiency of pattern classification and recognition in the database can be significantly improved, and the learning and extraction of knowledge from historical data can be accelerated to optimize current and future design verification activities.

[0056] Thereafter, in step S216, the plurality of layout fragments are arranged using the plurality of fragment information to assemble the test matrix. In one embodiment, the arrangement operation may involve accurately arranging different layout fragments according to their geometric characteristics and violation characteristics based on the extracted fragment information, such as the specific location, type, severity and relevant results of the design rule check (DRC) of the violation. This arrangement method takes into account the relationship and interaction between the fragments, ensuring that the test matrix can fully reflect the various violation modes that may be encountered in the semiconductor design process. After obtaining the test matrix, the scheme of the present application uses the test matrix to perform operations aimed at optimizing semiconductor design verification. Specifically, the test matrix is ​​used to simulate the actual semiconductor manufacturing process, and to identify and solve potential design problems by analyzing and verifying these arranged fragments. This includes detailed simulation of the patterns in the test matrix, evaluating their performance in the actual manufacturing process, and adjusting the design to improve the reliability and performance of the overall manufacturing. In addition, these test matrices can also be used to guide the development of lithography process correction (OPC) models, and as a key tool for silicon verification, thereby helping to improve the design quality of semiconductor products, reduce errors, and accelerate the time to market.

[0057] In addition, the test matrix of the present application can also be used to perform additional analysis, the results of which are added to the database to further improve the operating efficiency of the verification tool. Based on the disclosure of the present application, those skilled in the art can understand that this additional analysis can reduce the running time of DRC / OPC / OPCV because only the matrix of the selected area is cut / extracted from the complete layout for simulation. In addition, the test matrix of the present application can also be used for future DRC / OPC / OPCV quality assurance and regression test cases, as well as film output for silicon verification, thereby significantly increasing the flexibility and practicality of the design verification process.

[0058] Figure 3 3 is a flowchart showing the execution of database storage processing 300 according to some embodiments of the present disclosure. It can be understood that the above has been Figure 3 The terms and related processes shown in the are mentioned or described in detail, so the same also applies to the following Figure 3 and are not repeated for the purpose of clarity and conciseness.

[0059] like Figure 3As shown, at step S301, a layout is received. As mentioned above, the layout may be generated by an automated design tool, which may include, for example, detailed electronic files of circuit diagrams and component layouts. Next, at step S302, the received layout is verified using a verification tool. Depending on the application scenario, the verification may involve design rule checking (DRC) automatically performed by software, as well as confirmation of size, spacing, and layout compliance. Through the verification operation, violations / errors may be found at step S303. As mentioned above, the violations / errors may include elements in the layout that do not meet the design specifications, such as too narrow spacing or inappropriate wire width. Thereafter, at step S304, pattern classification is performed. The pattern classification here is also the aforementioned geometric classification, which may involve comparing layout fragments with patterns stored in a database, and clustering similar patterns based on fixed geometric parameters such as pattern radius, direction, and polygon edge fuzziness. As Figure 3 As shown by the arrow line from step S307 to step S304, the pattern classification step may also involve extracting stored historical patterns from the database for comparison and analysis.

[0060] Next, the obtained pattern category is classified, that is, it is determined as a historical pattern (or existing or old) pattern at step S305, and a corresponding historical pattern number is assigned, that is, a unique pattern number obtained by the geometric clustering in the past semiconductor layout verification. Alternatively, at step S306, the identified pattern is determined as a new pattern and a corresponding new pattern number is assigned. Unlike the historical pattern number, the new pattern number includes a unique pattern number obtained by the geometric clustering in the recent semiconductor layout verification (that is, in this processing step S304) and has not been stored in the pattern database. As an example, the aforementioned determination operation can be, for example, to process the stored data using a classification algorithm to identify new features of the pattern or compare it with a known pattern. Finally, at step S307, the assigned pattern number is stored in the database in association with the fragment information. As mentioned above, in this storage process, pattern annotations can also be used to enrich the information of the pattern, such as design version, manufacturing process, OPCV rule check name and key dimension metadata.

[0061] Figure 4 4 is a flow chart showing the execution of a correlation operation 400 at a database according to some embodiments of the present disclosure. Figure 4 As shown in FIG. 4 , the operation 400 can be combined with the aforementioned Figure 3300 overlaps and common steps described. Specifically, the historical pattern determined at step S305, the new pattern determined at step S306, and the violation / error information found at step S303 can be stored in the database at step S401. In step S405, the data stored in the database (such as pattern number and layout information) can be operated as required through a graphical user interface (GUI). The GUI can be used to display information such as images about the pattern, violation / error information, such as mark location, violation type and violation degree. Additionally or optionally, the GUI can also be used to display analysis results extracted from the database or pattern annotations that add additional information to the pattern category. For example, this additional information can be further physical analysis results, such as electron microscope images, or information from simulation tools.

[0062] Further, the GUI can also be used to process the identified patterns. For example, the user can use the information stored in the database to determine whether the pattern related to the violation / error can be passed, such as the determination of passing ("Approval") in step S407, or determine whether it can be exempted, that is, the disposal ("Disposition") operation is performed at step S406. Here, exemption means that the pattern related to the violation / error can be ignored, that is, it is determined to be ignorable at step S408. On the contrary, when it is determined to be non-exempt, it is determined to be non-ignorable at step S409. At this time, further actions can be taken to process the violation / error pattern. This further action can be, for example, extracting the layout information of the pattern from the database, and performing separate testing or verification on the associated layout fragments with the layout information. This further operation can also be for the violation / error pattern that cannot be ignored, to perform a detailed technical analysis to determine the root cause of the violation / error. According to the nature of the violation / error pattern, develop and implement one or more correction schemes to solve the problem. Then, the correction scheme is tested to verify its effectiveness and ensure that it will not introduce new problems. According to the test results, the layout is modified as necessary to eliminate the violation / error or reduce it to an acceptable level. After modifying the layout, the verification tool is used again to verify that all violations / errors have been properly addressed. In addition, the information in the database can be updated to record the corrective actions and subsequent verification results for future reference and continuous improvement.

[0063] It is understandable that the above-mentioned decision-making process (i.e., steps S405 to S409) can also be an automatic processing flow. Therefore, user input using the GUI is not required in this process. In some application scenarios, additional approvals can be implemented to recognize the exemption before the layout can be released for subsequent processing. In addition, the above-mentioned decision-making process of the present application can be a business process and requires formal approval from different levels of the organization. In addition, all approvals can be tracked, all records can be retrieved, and the results of the decision-making process can be stored in a database, such as a persistent database.

[0064] Figure 5 is a schematic diagram showing a usage scenario 500 of a test matrix according to some embodiments of the present disclosure. Figure 5 As shown in , it shows how to use a clip matrix ("Clip Matrix", that is, a test matrix in the context of this application) 501 for additional analysis and add the analysis results to a database 506. The advantage of using a test matrix 501 for additional analysis is that it reduces the runtime of the verification tool 502 and more interesting modes while wafer processing 503, and the increase in runtime and more interesting modes may limit yield. Here, because only the clips of interest are used when creating the test matrix 501 instead of using a larger complete original layout. Another advantage is that clips of different layouts can be merged into a single test matrix 501.

[0065] In operation, test matrix 501 can be used with verification tools 502, such as but not limited to design rule checking (DRC), lithography process correction (OPC), or lithography simulation, to perform additional analysis. This can also be done by re-running verification tool 502 after modifying a set of programs / configurations ("deck / recipes"). Figure 5 As shown in , errors / violations 504 detected by verification tool 502 can be added back to database 506. As described above, test matrix 501 can also be used to process ("503") wafers. The produced wafers can then be scanned by defect scanning tools 505, such as but not limited to scanning electron microscopes (SEM) for visual analysis, confirmation and / or measurement. Similarly, the results of defect scans 505 of the processed wafers can be added back to database 506 for further analysis.

[0066] Accordingly, newly added information from errors / violations 504 and / or defect scans 505 in database 506 can be used for further analysis, and / or to create a new test matrix 501. This iterative process is very useful for fine-tuning processes in technology development, manufacturing processes, and / or physical design.

[0067] Figure 6is an exemplary structural block diagram showing a database system 600 according to some embodiments of the present disclosure. Figure 6 As shown in the figure, the database system 600 includes a database 602, which is configured to store pattern categories and fragment information of multiple layout fragments of a semiconductor, wherein the layout fragment is a layout fragment with violation errors identified in the semiconductor layout verification process, and the pattern category is determined after the layout fragment is classified by geometric clustering. It can be understood that the layout fragment and fragment information here are also referred to as the layout fragments and fragment information in the above text. Figure 1-Figure 5 The layout fragments and fragment information are described, so the same content will not be repeated here. In addition, the database system 600 of the present application can also include a graphical user interface 604, which can be configured to assist the user in selecting a pattern category and locating fragment information from the database, so as to assemble the layout fragments into a test matrix using the fragment information.

[0068] In some scenarios, as described above, database 602 can be configured to store historical pattern numbers and / or new pattern numbers, wherein the historical pattern numbers include unique pattern numbers obtained through the geometric clustering in past semiconductor layout verifications, and the new pattern numbers include unique pattern numbers obtained through the geometric clustering in recent semiconductor layout verifications and have not been stored in the pattern database.

[0069] In some scenarios, such as combining Figure 4 As described, the graphical user interface 604 is further configured to assist the user in reviewing the pattern categories and fragment information stored in the database to implement a handling process, wherein the handling process is used to determine whether to mark the violation or error in the fragment information as ignorable or non-ignorable. Specifically, in response to the violation or error being marked as ignorable, no further action is taken; and in response to the violation or error being marked as non-ignorable, further action is taken to resolve the violation or error. Regarding the further action here, the above has been combined with Figure 4 In addition, the database 603 can also be configured to store the results of the treatment process for subsequent data analysis and improvement of verification tools.

[0070] Figure 7 is an exemplary structural block diagram showing a database device 700 according to some embodiments of the present disclosure. Figure 7 As shown in FIG. , the database device may include a processor 702 and a Figure 6The described database system 600, when executed by the processor, is used to assist the semiconductor design verification. For example, the database system may utilize a graphical user interface to receive user input, thereby assisting in forming a test matrix for semiconductor verification.

[0071] In different application scenarios, the processor of the present application can be a central processing unit (CPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other microprocessors, all of which have the ability to execute preset instruction sets to process data, control database system operations, and perform complex computing tasks. In addition, the processor can enhance its computing efficiency through parallel processing or multi-threaded execution, thereby supporting the stable operation of database equipment in a high-speed data environment.

[0072] In various application scenarios, the memory of the present application can be a random access memory (RAM), a hard disk drive (HDD), a solid state drive (SSD), a read-only memory (ROM) or other forms of electronic data storage units. The memory is used to store data and instruction sets of the operating system, application programs, and the database system. It can provide fast data reading and writing capabilities to ensure that the processor can efficiently access and process the required data and program code.

[0073] Although multiple embodiments of the present disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Those skilled in the art may think of many changes, modifications, and alternatives without departing from the thought and spirit of the present disclosure. It should be understood that in the process of practicing the present disclosure, various alternatives to the embodiments of the present disclosure described herein may be adopted. The attached claims are intended to define the scope of protection of the present disclosure, and therefore cover equivalents or alternatives within the scope of these claims.

Claims

1. A method for semiconductor design verification, characterized in that, include: Identifying a layout fragment that has a violation error during a semiconductor layout verification process and determining its fragment information; Performing pattern classification on the layout fragments by using geometric clustering to determine the pattern category of the layout fragments; storing the mode category and the segment information in association with each other in a database; extracting the fragment information from the database according to the pattern category; as well as The layout fragments are assembled into a test matrix based on the fragment information for optimizing semiconductor design verification.

2. The method according to claim 1, characterized in that The violation errors include size violations and / or configuration errors, and identifying layout segments that have violation errors during semiconductor layout verification includes: Running verification tools on the semiconductor layout to detect areas of the layout that have size violations and / or configuration errors; and The layout region with size violation and / or configuration error is identified as a layout fragment with violation error.

3. The method according to claim 1, characterized in that The segment information includes violation information of the location, type and / or extent of the violation error.

4. The method according to claim 1, characterized in that The pattern classification of the layout fragments by using geometric clustering includes: Using the fragment information to classify the layout fragment into modes to obtain the mode category; and A unique mode number is allocated to the mode category to achieve association between the two.

5. The method according to claim 4, characterized in that The pattern classification of the layout fragments by using geometric clustering includes: In response to identifying a plurality of layout fragments, performing pattern classification on the plurality of layout fragments respectively to determine respective pattern categories; Clustering layout fragments with the same pattern category, and assigning a unique pattern to the same pattern category to achieve association between the two; and For a layout fragment having a mode category different from other layout fragments, a unique mode number is assigned to its mode category to achieve association between the two.

6. The method according to claim 4, characterized in that The database is a graph database or a non-relational database, and storing the pattern category and the fragment information in the database in association with each other comprises: The unique mode number and the layout information are stored in a graph database or a non-relational database in association with each other.

7. The method according to claim 5, characterized in that Wherein extracting the fragment information from the database according to the pattern category includes extracting multiple fragment information of the corresponding multiple layout fragments from the database according to the multiple unique pattern numbers, and assembling the layout fragments into a test matrix based on the fragment information includes arranging the multiple layout fragments using the multiple fragment information to assemble into the test matrix.

8. The method according to any one of claims 1 to 7, characterized in that: Assembling the layout fragments into a test matrix based on the fragment information further includes: The test matrix is ​​used in conjunction with one or more verification tools to provide additional testing and analysis.

9. An electronic device for semiconductor design verification, characterized in that: include: processor; A memory having program instructions for semiconductor design verification stored therein, wherein when the program instructions are executed by the processor, the method according to any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium having stored thereon program instructions for semiconductor design verification, wherein when the program instructions are executed by a processor, the method according to any one of claims 1 to 8 is implemented.

11. A database system for semiconductor design verification, characterized in that: include: A database configured to store pattern categories of a plurality of semiconductor layout fragments and fragment information thereof, wherein the layout fragments are layout fragments with violation errors identified in a semiconductor layout verification process, and the pattern categories are determined after pattern classification of the layout fragments is performed using geometric clustering; and A graphical user interface is configured to assist a user in selecting a pattern category and locating fragment information from the database so as to assemble the layout fragments into a test matrix using the fragment information.

12. The database system according to claim 11, characterized in that: The violation errors include size violations and / or configuration errors of the layout fragments.

13. The database system according to claim 11, characterized in that: Each of the mode categories is assigned a unique mode number and is associated with the layout fragment and the fragment information.

14. The database system according to claim 13, characterized in that: The database is configured to store historical pattern numbers and / or new pattern numbers, wherein the historical pattern numbers include unique pattern numbers obtained through the geometric clustering in past semiconductor layout verifications, and the new pattern numbers include unique pattern numbers obtained through the geometric clustering in recent semiconductor layout verifications and have not been stored in the pattern database.

15. The database system according to claim 11, characterized in that: The graphical user interface is also configured to assist a user in reviewing the pattern categories and segment information stored in the database to implement a handling process, wherein the handling process is used to determine whether to mark violations or errors in the segment information as ignorable or non-ignorable.

16. The database system according to claim 15, characterized in that: In response to the violation or error being marked as ignorable, no further action is taken; and in response to the violation or error being marked as non-ignorable, further action is taken to resolve the violation or error.

17. The database system according to claim 15 or 16, characterized in that: The database is further configured to store the results of the treatment process for subsequent data analysis and improvement of the validation tool.

18. A database device for semiconductor design verification, characterized in that: include: processor; as well as The database system according to any one of claims 11 to 17, wherein when the database system is executed by the processor, it is used to assist the semiconductor design verification.

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