Semiconductor structure and preparation method thereof
By forming a stop layer on the substrate and covering the semiconductor material layer, the problem of easy substrate damage in the back thinning process is solved, and the performance and process accuracy of the semiconductor device are improved.
Patent Information
- Application Number
- CN202411622504.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-14
- Publication Date
- 2025-03-11
AI Technical Summary
In the existing back thinning process, the underlying substrate is easily damaged, affecting the improvement of semiconductor device performance.
The stop layer is formed on the upper surface of the substrate of the isolation structure and peripheral region, covering the semiconductor material layer, and exposing the upper surface of the stop layer by grinding, thereby improving the selection ratio of the grinding process, reducing the grinding rate of the stop layer, and protecting the substrate.
It effectively avoids substrate losses, improves the accuracy of the back thinning process, and further improves the performance of semiconductor devices.
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Figure CN119601463A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art
[0002] With the continuous development of semiconductor processing technology, semiconductor devices are increasingly used in electronics, communications and other fields due to their smaller size, higher performance and higher conversion efficiency.
[0003] The backside thinning process can reduce the thickness of the wafer, thereby reducing the chip packaging volume and improving the performance of semiconductor devices. Therefore, it has received widespread attention. However, there are still some problems with the backside thinning process. For example, the underlying substrate is easily damaged, which in turn affects the further improvement of the performance of semiconductor devices. Summary of the invention
[0004] Based on this, the embodiments of the present application provide a semiconductor structure and a method for preparing the same, which can effectively prevent the underlying substrate from being damaged, thereby further improving the performance of the semiconductor device.
[0005] According to some embodiments, the present application provides a method for preparing a semiconductor structure, comprising the following steps:
[0006] Providing a substrate, the substrate having an array region and a peripheral region;
[0007] Forming an isolation structure in the substrate to define a plurality of active areas arranged in an array in the array area, wherein the upper surface of the isolation structure is higher than the upper surface of the substrate;
[0008] forming a stop layer, wherein the stop layer covers an upper surface of the isolation structure and an upper surface of the substrate in the peripheral region;
[0009] forming a semiconductor material layer covering the stop layer on the upper surface of the substrate;
[0010] The upper surface of the semiconductor material layer is ground until the upper surface of the stop layer is exposed.
[0011] According to some embodiments, forming the stop layer comprises the following steps:
[0012] forming an initial stop layer covering the isolation structure on the upper surface of the substrate;
[0013] The initial stop layer on the upper surface of the substrate in the array region is removed to form a stop layer.
[0014] According to some embodiments, the material of the stop layer includes nitride, and the material of the semiconductor material layer includes polysilicon.
[0015] According to some embodiments, grinding the upper surface of the semiconductor material layer until the upper surface of the stop layer is exposed further includes: removing the stop layer.
[0016] According to some embodiments, removing the stop layer includes: removing the stop layer using a wet etching process.
[0017] According to some embodiments, the present application provides a semiconductor structure on the other hand, which is prepared by the method for preparing the semiconductor structure described in the above embodiments, including: a substrate, a plurality of isolation structures and a first semiconductor layer. The substrate has an array area and a peripheral area. The plurality of isolation structures are located in the array area. The plurality of isolation structures define a plurality of active areas arranged in an array, and the upper surface of the isolation structure is higher than the upper surface of the substrate. There is at least one sidewall of the isolation structure in contact with the substrate in the peripheral area. The first semiconductor layer is located on the upper surface of the substrate in the array area and between the plurality of isolation structures.
[0018] According to some embodiments, the semiconductor structure further includes: a second semiconductor layer. The second semiconductor layer is located on the upper side of the substrate in the peripheral region and covers an exposed sidewall of the at least one isolation structure.
[0019] According to some embodiments, the semiconductor structure further includes: a stop layer, wherein the stop layer is located between the second semiconductor layer and the substrate.
[0020] According to some embodiments, the material of the stop layer includes: nitride. The material of the first semiconductor layer includes polysilicon. The material of the second semiconductor layer includes polysilicon.
[0021] According to some embodiments, the height difference between the upper surface of the isolation structure and the upper surface of the substrate ranges from:
[0022] The embodiments of the present application may or at least have the following advantages:
[0023] In an embodiment of the present application, before forming a semiconductor material layer, a stop layer is first formed on the upper surface of the isolation structure and the upper surface of the substrate in the peripheral area. Then a semiconductor material layer covering the stop layer is formed, and finally the upper surface of the semiconductor material layer is ground until the upper surface of the stop layer is exposed. In this way, the selectivity of the subsequent grinding process can be improved by the stop layer, that is, the grinding rate of the stop layer is reduced, thereby effectively avoiding substrate loss, improving the accuracy of the back thinning process, and further improving the performance of the semiconductor device. Therefore, the embodiment of the present application can protect the substrate and improve the performance of the semiconductor device by only adding a stop layer without increasing the complexity of the process.
[0024] In addition, the embodiments of the present application can also prevent the substrate from being ground to the front side when the back side is thinned, and the front and back sides of the substrate can be known in time when an alarm occurs in the machine. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without paying any creative work.
[0026] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in some embodiments;
[0027] Figure 2 A schematic flow chart of step S300 in a method for preparing a semiconductor structure provided in some embodiments;
[0028] Figure 3 is a schematic cross-sectional structural diagram of a structure obtained in S100 in a method for preparing a semiconductor structure provided in some embodiments;
[0029] Figure 4 A schematic cross-sectional view of a structure obtained in S200 in a method for preparing a semiconductor structure provided in some embodiments;
[0030] Figure 5 A schematic cross-sectional view of a structure obtained in S310 in a method for preparing a semiconductor structure provided in some embodiments;
[0031] Figure 6 A schematic cross-sectional view of a structure obtained in S320 in a method for preparing a semiconductor structure provided in some embodiments;
[0032] Figure 7 A schematic cross-sectional view of a structure obtained in S400 in a method for preparing a semiconductor structure provided in some embodiments;
[0033] Figure 8 A schematic cross-sectional view of a structure obtained in S500 in a method for preparing a semiconductor structure provided in some embodiments;
[0034] Fig. 9 is a schematic cross-sectional structural diagram of a structure obtained in S600 in a method for preparing a semiconductor structure provided in some embodiments;
[0035] Fig.10 A schematic cross-sectional structure diagram of a semiconductor structure provided in some embodiments.
[0036] Description of reference numerals:
[0037] 1-substrate; 2-isolation structure; 30-initial stop layer; 3-stop layer; 40-semiconductor material layer; 41-first semiconductor layer; 42-second semiconductor layer; A-array area; P-peripheral area; AA-active area. DETAILED DESCRIPTION
[0038] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0040] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers.
[0041] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0042] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.
[0043] As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).
[0044] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of ideal embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, and their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present application.
[0045] With the continuous development of semiconductor processing technology, semiconductor devices are increasingly used in electronics, communications and other fields due to their smaller size, higher performance and higher conversion efficiency.
[0046] In the back-end process stage, the wafer (silicon wafer with circuits on the front) needs to be thinned on the back before subsequent dicing, bonding and packaging to reduce the package mounting height, reduce the chip package volume, improve the chip's thermal diffusion efficiency, electrical performance, mechanical properties and reduce the amount of dicing. Back grinding has the advantages of high efficiency and low cost. It has replaced traditional wet etching and ion etching processes to become the most important back thinning technology. However, there are still some problems with the current back thinning process. For example, the underlying substrate is easily damaged, which in turn affects the further improvement of semiconductor device performance.
[0047] Based on this, the embodiments of the present application provide a semiconductor structure and a method for preparing the same, which can effectively prevent the underlying substrate from being damaged, thereby further improving the performance of the semiconductor device.
[0048] See also Figure 1Some embodiments of the present application provide a method for preparing a semiconductor structure, including steps S100 to S500.
[0049] S100, providing a substrate, wherein the substrate has an array region and a peripheral region.
[0050] S200 , forming an isolation structure in the substrate to define a plurality of active areas arranged in an array in the array region, wherein an upper surface of the isolation structure is higher than an upper surface of the substrate.
[0051] S300 , forming a stop layer, wherein the stop layer covers an upper surface of the isolation structure and an upper surface of the substrate in the peripheral region.
[0052] S400, forming a semiconductor material layer covering the stop layer on the upper surface of the substrate.
[0053] S500, grinding the upper surface of the semiconductor material layer until the upper surface of the stop layer is exposed.
[0054] In an embodiment of the present application, before forming a semiconductor material layer, a stop layer is first formed on the upper surface of the isolation structure and the upper surface of the substrate in the peripheral area. Then a semiconductor material layer covering the stop layer is formed, and finally the upper surface of the semiconductor material layer is ground until the upper surface of the stop layer is exposed. In this way, the selectivity of the subsequent grinding process can be improved by the stop layer, that is, the grinding rate of the stop layer is reduced, thereby effectively avoiding substrate loss, improving the accuracy of the back thinning process, and further improving the performance of the semiconductor device. Therefore, the embodiment of the present application can protect the substrate and improve the performance of the semiconductor device by only adding a stop layer without increasing the complexity of the process.
[0055] In addition, the embodiments of the present application can also prevent the substrate from being ground to the front side when the back side is thinned, and the front and back sides of the substrate can be known in time when an alarm occurs in the machine.
[0056] In some embodiments, see Figure 2 , step S300 of forming a stop layer includes steps S310 to S320.
[0057] S310, forming an initial stop layer covering the isolation structure on the upper surface of the substrate.
[0058] S320, removing the initial stop layer on the upper surface of the substrate in the array region to form a stop layer.
[0059] In some embodiments, the material of the stop layer includes nitride, and the material of the semiconductor material layer includes polysilicon.
[0060] It should be noted that, in the above-mentioned embodiments, the execution of each step in the method is not strictly limited in order, and these steps may not necessarily be executed in the order described, but may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps. The method is limited to being able to achieve the preparation of the corresponding semiconductor structure.
[0061] Based on this, with respect to the methods for preparing semiconductor structures provided in some of the above embodiments, the following embodiments of the present application illustrate some methods as some possible implementation methods of the above preparation methods.
[0062] In some embodiments, after step S500 of grinding the upper surface of the semiconductor material layer until the upper surface of the stop layer is exposed, step S600 is further included: removing the stop layer.
[0063] In some embodiments, removing the stop layer in step S600 includes: removing the stop layer by a wet etching process.
[0064] In order to more clearly illustrate the method for preparing the semiconductor structure provided by the above embodiment, Figure 3 to Figure 9 The preparation method is described in detail.
[0065] In step S100, refer to Figure 3 , a substrate 1 is provided, wherein the substrate 1 has an array area A and a peripheral area P.
[0066] In some examples, the material of the substrate 1 can be any suitable substrate material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, referred to as DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and the embodiments of the present application are not limited here.
[0067] In step S200, refer to Figure 4 , an isolation structure 2 is formed in the substrate 1 to define a plurality of active areas AA arranged in an array in the array area A, wherein the upper surface of the isolation structure 2 is higher than the upper surface of the substrate 1 .
[0068] In some examples, forming the isolation structure 2 in the substrate 1 includes: forming trenches (not shown in the figure) arranged at intervals in the substrate 1; and filling the trenches to form the isolation structure 2.
[0069] Here, the trenches are formed to match the arrangement of the active area AA.
[0070] For example, the substrate 1 may be etched to form the grooves by using, but not limited to, a self-aligned double patterning technique (SADP) or a self-aligned quadruple patterning technique (SAQP).
[0071] In some examples, the surface of the bottom of the trench is planar.
[0072] For example, a hard mask layer may be formed on the substrate 1 first, and then the hard mask layer of the array region A may be patterned to form a mask pattern corresponding to the array region A. In this way, the trench may be formed by etching based on the mask pattern.
[0073] In some embodiments, a photoresist material layer may be coated on the substrate 1 first, and the photoresist material layer is subjected to a series of steps such as exposure and development to form a patterned photoresist layer, the patterned photoresist layer having an opening pattern that defines the position and shape of the groove, the photoresist may be a positive photoresist or a negative photoresist, and the development method may be a positive development or a negative development. In this way, an etching process may be used to etch the substrate 1 using the patterned photoresist layer as a mask to form a groove.
[0074] In some examples, the material of the isolation structure 2 may include, but is not limited to, oxide. For example, the material of the isolation structure 2 may be silicon oxide.
[0075] In some embodiments, the height difference between the upper surface of the isolation structure 2 and the upper surface of the substrate 1 ranges from: For example, the height difference between the upper surface of the isolation structure 2 and the upper surface of the substrate 1 may be: or etc.
[0076] In step S310, refer to Figure 5 , an initial stop layer 30 covering the isolation structure 2 is formed on the upper surface of the substrate 1 .
[0077] In some examples, a deposition process may be used to form an initial stop layer 30 covering the isolation structure 2 on the upper surface of the substrate 1 .
[0078] For example, a sub-atmospheric chemical vapor deposition (SACVD) process can be used to form an initial stop layer 30 covering the isolation structure 2 on the upper surface of the substrate 1. The SACVD process refers to a deposition process performed under conditions below atmospheric pressure. The SACVD process can obtain higher film density and uniformity.
[0079] For example, a process such as chemical vapor deposition or physical vapor deposition (PVD) can be used to form an initial stop layer 30 covering the isolation structure 2 on the upper surface of the substrate 1. The chemical vapor deposition process method can include one or more of atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). For example, the initial stop layer 30 can be formed by plasma enhanced chemical vapor deposition, which is formed by ionizing the film layer by glow discharge in a deposition chamber and then chemically reacting on the film layer to deposit and form the initial stop layer 30. The plasma enhanced chemical vapor deposition method can enhance the activity of chemical vapor reaction substances through plasma activation, increase the surface reaction rate, and significantly reduce the deposition temperature through high-energy ions.
[0080] In some examples, the initial stop layer 30 conformally covers the exposed surface of the isolation structure 2. Here, the initial stop layer 30 conformally covers the exposed surface of the isolation structure 2, which means that the initial stop layer 30 is a thin layer structure, and the surface of the initial stop layer 30 mimics the exposed surface of the isolation structure 2, so that the surface shape of the initial stop layer 30 is similar to the exposed surface shape of the isolation structure 2.
[0081] In some embodiments, the material of the initial stop layer 30 includes nitride. For example, the material of the initial stop layer 30 may be silicon nitride.
[0082] In some examples, the thickness of the initial stop layer 30 ranges from: For example, the thickness of the initial stop layer 30 may be: or etc.
[0083] In step S320, refer to Figure 6, the initial stop layer 30 on the upper surface of the substrate 1 in the array region A is removed to form a stop layer 3. The stop layer 3 covers the upper surface of the isolation structure 2 and the upper surface of the substrate 1 in the peripheral region P.
[0084] In some examples, a photolithography process or an etching process may be used to remove the initial stop layer 30 on the upper surface of the substrate 1 in the array region A to form a stop layer 3 .
[0085] In step S400, refer to Figure 7 , a semiconductor material layer 40 covering the stop layer 3 is formed on the upper surface of the substrate 1 .
[0086] In some examples, a semiconductor material layer 40 covering the stop layer 3 may be formed on the upper surface of the substrate 1 by a deposition process.
[0087] For example, a semiconductor material layer 40 covering the stop layer 3 can be formed on the upper surface of the substrate 1 by using a chemical vapor deposition process (SACVD) below atmospheric pressure. The SACVD process refers to a deposition process performed under conditions below atmospheric pressure. The SACVD process can obtain higher film density and uniformity.
[0088] For example, a semiconductor material layer 40 covering the stop layer 3 can be formed on the upper surface of the substrate 1 by chemical vapor deposition or physical vapor deposition (PVD) and other processes. The chemical vapor deposition process can include one or more of atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). For example, the semiconductor material layer 40 can be formed by plasma enhanced chemical vapor deposition, which is formed by ionizing the semiconductor material layer by glow discharge in a deposition chamber and then chemically reacting on the film layer to deposit the semiconductor material layer 40. The plasma enhanced chemical vapor deposition can enhance the activity of chemical vapor reaction substances through plasma activation, increase the surface reaction rate, and significantly reduce the deposition temperature through high-energy ions.
[0089] In some embodiments, the material of the semiconductor material layer 40 includes polysilicon.
[0090] In step S500, refer to Figure 8 , grinding the upper surface of the semiconductor material layer 40 until the upper surface of the stop layer 3 is exposed.
[0091] In some examples, a chemical mechanical polishing process may be used to polish the upper surface of the semiconductor material layer 40 until the upper surface of the stop layer 3 is exposed.
[0092] Here, it should be specially explained that, since the polishing pad is made of soft polyurethane, it has a certain deformation during polishing and will try to fit the surface of the material. However, at the corners of some graphics (such as the side walls of the raised isolation structure 2 in the embodiment of the present application), it cannot be completely fitted, and a small amount of semiconductor material layer 40 will remain. The stop layer 3 under the semiconductor material layer 40 is retained. Since there is less residual semiconductor material layer 40, the subsequent semiconductor device performance is less affected.
[0093] In step S600, refer to Fig. 9 , remove the stop layer 3.
[0094] In some embodiments, removing the stop layer 3 includes: removing the stop layer 3 by a wet etching process.
[0095] It should be added that the "etching process" mentioned in some embodiments of the present disclosure can be understood as: etching based on the pattern of the same mask plate at the same time to form multiple patterns in one etching process; it is not limited to a specific etching method, for example, it can be implemented by dry etching, it can be implemented by wet etching, or it can be implemented by both dry etching and wet etching, etc.
[0096] As described above, in an embodiment of the present application, before forming a semiconductor material layer, a stop layer is first formed on the upper surface of the isolation structure and the upper surface of the substrate in the peripheral area. Then a semiconductor material layer covering the stop layer is formed, and finally the upper surface of the semiconductor material layer is ground until the upper surface of the stop layer is exposed. The unexpected technical effect is: the embodiment of the present application can improve the selectivity of the subsequent grinding process through the stop layer, that is, reduce the grinding rate of the stop layer, thereby effectively avoiding substrate loss, improving the accuracy of the back thinning process, and further improving the performance of the semiconductor device. Therefore, the embodiment of the present application can protect the substrate and improve the performance of the semiconductor device by simply adding a stop layer without increasing the complexity of the process.
[0097] In addition, the embodiments of the present application can also prevent the substrate from being ground to the front side when the back side is thinned, and the front and back sides of the substrate can be known in time when an alarm occurs in the machine.
[0098] According to some embodiments, the present application provides a semiconductor structure on the other hand, which is prepared using the semiconductor structure preparation method described in the aforementioned embodiment. The semiconductor structure also has the technical advantages of the aforementioned preparation method, which will not be repeated here.
[0099] In some embodiments, see Fig.10 , the semiconductor structure includes: a substrate 1, a plurality of isolation structures 2 and a first semiconductor layer 41. The substrate 1 has an array area A and a peripheral area P. The plurality of isolation structures 2 are located in the array area A. The plurality of isolation structures 2 define a plurality of active areas AA arranged in an array, and the upper surface of the isolation structure 2 is higher than the upper surface of the substrate 1. At least one sidewall of the isolation structure 2 is in contact with the substrate 1 in the peripheral area P. The first semiconductor layer 41 is located on the upper surface of the substrate 1 in the array area A and between the plurality of isolation structures 2.
[0100] In some examples, the material of the substrate 1 can be any suitable substrate material known in the art, for example, it can be at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), carbon silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or it can also be double-sided polished silicon wafers (Double Side Polished Wafers, referred to as DSP), or it can be a ceramic substrate such as alumina, a quartz or glass substrate, etc., and the embodiments of the present application are not limited here.
[0101] In some embodiments, the semiconductor structure further includes: a second semiconductor layer 42 . The second semiconductor layer 42 is located on the upper side of the substrate 1 in the peripheral region P and covers an exposed sidewall of at least one isolation structure 2 .
[0102] In some examples, the material of the isolation structure 2 may include, but is not limited to, oxide. For example, the material of the isolation structure 2 may be silicon oxide.
[0103] In some embodiments, the height difference between the upper surface of the isolation structure 2 and the upper surface of the substrate 1 ranges from: For example, the height difference between the upper surface of the isolation structure 2 and the upper surface of the substrate 1 may be: or etc.
[0104] In some embodiments, the semiconductor structure further includes: a stop layer 3. The stop layer 3 is located between the second semiconductor layer 42 and the substrate.
[0105] In some embodiments, the material of the stop layer 3 includes nitride. For example, the material of the stop layer 3 may be silicon nitride.
[0106] In some examples, the thickness of the initial stop layer 30 ranges from: For example, the thickness of the initial stop layer 30 may be: or etc.
[0107] In some embodiments, the material of the first semiconductor layer 41 includes polysilicon. The material of the second semiconductor layer 42 includes polysilicon.
[0108] Here, it should be specially explained that since the polishing pad is made of soft polyurethane, it has a certain deformation during polishing and will try to fit the surface of the material. However, at the corners of some graphics (such as the side walls of the raised isolation structure 2 in the embodiment of the present application), it cannot be completely fitted, and a small amount of the second semiconductor layer 42 will remain. The stop layer 3 under the second semiconductor layer 42 is retained, and the nitrogen residue in the second semiconductor layer 42 is small, which has little effect on the performance of subsequent semiconductor devices.
[0109] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0110] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate having an array region and a peripheral region; forming an isolation structure in the substrate to define a plurality of active areas arranged in an array in the array area, wherein an upper surface of the isolation structure is higher than an upper surface of the substrate; forming a stop layer, wherein the stop layer covers an upper surface of the isolation structure and an upper surface of the substrate in the peripheral region; forming a semiconductor material layer covering the stop layer on the upper surface of the substrate; The upper surface of the semiconductor material layer is ground until the upper surface of the stop layer is exposed.
2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The forming of the stop layer comprises: forming an initial stop layer covering the isolation structure on the upper surface of the substrate; The initial stop layer on the upper surface of the substrate in the array region is removed to form a stop layer.
3. The method for preparing a semiconductor structure according to claim 1, characterized in that: The material of the stop layer includes nitride; the material of the semiconductor material layer includes polysilicon.
4. The method for preparing a semiconductor structure according to claim 1, wherein: After grinding the upper surface of the semiconductor material layer until the upper surface of the stop layer is exposed, the method further includes: removing the stop layer.
5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The removing of the stop layer comprises: The stop layer is removed by a wet etching process.
6. A semiconductor structure, characterized in that: The method for preparing a semiconductor structure according to any one of claims 1 to 5 comprises: A substrate; the substrate has an array region and a peripheral region; A plurality of isolation structures are located in the array region; the plurality of isolation structures define a plurality of active regions arranged in an array, and the upper surface of the isolation structure is higher than the upper surface of the substrate; at least one sidewall of the isolation structure is in contact with the substrate in the peripheral region; The first semiconductor layer is located on the upper surface of the substrate in the array region and between the plurality of isolation structures.
7. The semiconductor structure according to claim 6, wherein: Also includes: The second semiconductor layer is located on the upper side of the substrate in the peripheral region and covers at least one exposed side wall of the isolation structure.
8. The semiconductor structure according to claim 7, wherein: Also includes: The stop layer is located between the second semiconductor layer and the substrate.
9. The semiconductor structure according to claim 8, characterized in that The material of the stop layer includes: nitride; the material of the first semiconductor layer includes polysilicon; and the material of the second semiconductor layer includes polysilicon.
10. The semiconductor structure according to claim 6, wherein: The height difference between the upper surface of the isolation structure and the upper surface of the substrate includes: