Crosstalk suppression driving circuit for power device and double-pulse testing device

Abstract

The invention relates to a crosstalk suppression driving circuit for a power device and a double-pulse testing device.The crosstalk suppression driving circuit is connected between a grid electrode and a source electrode of the power device and comprises a negative voltage generation sub-circuit, a driving current-limiting resistor R2 and a Miller clamping sub-circuit; the negative voltage generation sub-circuit is respectively connected with the driving current-limiting resistor R2 and the miller clamping sub-circuit, the driving current-limiting resistor R2 is connected with the miller clamping sub-circuit, the negative voltage generation sub-circuit is used for generating negative voltage during turn-off, and the driving current-limiting resistor R2 is used for limiting current flowing through a grid electrode of a device so as to control the switching speed of the device. And the Miller clamping sub-circuit is used for realizing Miller clamping through negative voltage driving. Compared with the prior art, the method has the advantages of having a certain inhibition effect on positive and negative crosstalk and the like.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a crosstalk suppression driving circuit and a double pulse testing device for power devices. Background Art

[0002] In the field of power electronics, bridge circuits play an important role. Inverters, half-bridges, full-bridges and other topological circuits using bridge circuits play a vital role in design, production and life. However, bridge circuits are subject to the influence of bridge arm crosstalk, especially when high-speed switching devices are used.

[0003] Bridge arm crosstalk means that on the same bridge arm, the turning on and off of a switching device will generate positive and negative spikes on the gate source of another switching device, especially when the switching transient dv / dt is large. This interference may cause the bridge arm to be directly turned on or burn out the power device.

[0004] The mechanism of bridge arm crosstalk is as follows: when the lower switch device of the bridge arm is turned on, the voltage across the upper switch device of the bridge arm rises sharply, and the Miller capacitance C of the upper switch device gd A higher dv / dt is generated on the capacitor, which charges the Miller capacitor and generates a charging current. Part of this current is fed to C gs The other part flows through the driving impedance, so that the gate-source voltage of the switching device is pulled up, resulting in a positive spike, which is called forward crosstalk. In addition, when the lower switch device of the bridge arm is turned off, the voltage across the upper switch device of the bridge arm drops sharply, generating a high dv / dt on the Miller capacitor of the upper switch device, which makes the Miller capacitor C gd Discharge, generating a discharge current, part of which is supplied by C gs The other part flows through the driving impedance, which causes the gate-source voltage of the switching device to be pulled down, thereby generating a negative spike, which is called negative crosstalk.

[0005] There are many technologies that can suppress bridge arm crosstalk to a certain extent. The existing technical solutions are mainly divided into two types:

[0006] 1. Multi-level drive technology. That is, when positive crosstalk occurs, the drive voltage is set to a negative voltage, and when negative crosstalk occurs, the drive voltage is set to 0. This solution can effectively avoid the bridge arm shoot-through phenomenon caused by positive crosstalk, but this method often requires an additional active interface.

[0007] 2. Miller clamping technology: Since the bridge arm crosstalk is caused by the Miller current flowing through the driving resistor, the bridge arm crosstalk can be suppressed by reducing the impedance of the driving loop, but the Miller clamping technology often has a delay problem.

[0008] 3. Use soft switching technology: Soft switching technology can effectively reduce bridge arm crosstalk, but soft switching has relatively high topology requirements and has great limitations in practical applications. Summary of the invention

[0009] The purpose of the present invention is to provide a crosstalk suppression driving circuit and a double pulse testing device for a GaN power device bridge circuit that can reduce crosstalk.

[0010] The purpose of the present invention can be achieved by the following technical solutions:

[0011] A crosstalk suppression driving circuit for a power device is connected between the gate and source of the power device. The crosstalk suppression driving circuit comprises a negative voltage generating subcircuit, a driving current limiting resistor R2 and a Miller clamping subcircuit. The negative voltage generating subcircuit is respectively connected to the driving current limiting resistor R2 and the Miller clamping subcircuit. The driving current limiting resistor R2 is connected to the Miller clamping subcircuit. The negative voltage generating subcircuit is used to generate a negative voltage when turned off. The driving current limiting resistor R2 is used to limit the current flowing through the gate of the power device to control its switching speed. The Miller clamping subcircuit is used to realize Miller clamping by driving a negative voltage.

[0012] Furthermore, the negative voltage generating sub-circuit includes a resistor R1, a capacitor C1 and a Zener diode Z1, one end of the resistor R1 is connected to the output side of the driving chip in the power device, and the other end is connected to the driving current limiting resistor R2, the capacitor C1 is connected in parallel with the resistor R1, the cathode of the Zener diode Z1 is respectively connected to the other end of the resistor R1 and the driving current limiting resistor R2, and the anode of the Zener diode Z1 is connected to the source of the power device.

[0013] Furthermore, the Miller clamp subcircuit includes an NMOSFET Q1, a parasitic diode D1 and an NMOSFET driving resistor R3, the NMOSFET Q1 is connected in parallel with the driving current limiting resistor R2, the NMOSFET Q1 is also connected to the NMOSFET driving resistor R3, and the parasitic diode D1 is connected in parallel with the NMOSFET Q1.

[0014] Furthermore, the NMOSFET Q1 includes three electrodes, namely a drain, a source and a gate. The drain and the source are respectively connected to the two ends of the driving current limiting resistor R2, and the two ends of the parasitic diode D1 are respectively connected to the drain and the source, and the gate is connected to the source of the power device through the NMOSFET driving resistor R3.

[0015] Furthermore, the parasitic diode D1 includes three electrodes, namely an anode and a cathode. The anode is connected to the source of the NMOSFET Q1, and the cathode is connected to the drain of the NMOSFET Q1.

[0016] Furthermore, the types of power devices include GaN power devices, SiC Mosfet power devices, IGBT power devices, BJT power devices, SITH power devices, MCT power devices, IGCT power devices and IEGT power devices.

[0017] The present invention also provides a double pulse test device, the double pulse test device comprises an upper tube unit and a lower tube unit, the upper tube unit and the lower tube unit are connected in series, the upper tube unit and the lower tube unit both comprise any of the above crosstalk suppression drive circuits, the upper tube unit further comprises a first drive chip, a freewheeling tube Q H and load inductance L load The first driving chip is connected to the first crosstalk suppression driving circuit of the upper tube unit to generate a total driving voltage, and the first crosstalk suppression driving circuit is also connected to the freewheeling tube Q H Connect the freewheeling tube Q H Also with the load inductance L load The lower tube unit also includes a second driver chip and a control tube Q L The second driving chip is connected to the second crosstalk suppression driving circuit of the lower tube unit, and the second crosstalk suppression driving circuit is also connected to the control tube Q L Connect the control tube Q L Also with the freewheeling tube Q H connect.

[0018] Furthermore, the specific connection method of the upper tube unit is:

[0019] The first driving chip is respectively connected to the resistor R1 and the anode of the Zener diode Z1 in the first crosstalk suppression driving circuit. H The gate of is connected to the driving current limiting resistor R2 in the first crosstalk suppression driving circuit, and the freewheeling tube Q H The drain and source are connected to the load inductor L load both ends of .

[0020] Furthermore, the specific connection method of the lower pipe unit is:

[0021] The second driving chip is respectively connected to the resistor R1 and the anode of the Zener diode Z1 in the second crosstalk suppression driving circuit. L The gate of is connected to the driving current limiting resistor R2 in the second crosstalk suppression driving circuit, and the control tube Q L The drain of the freewheeling tube Q H The source of the control tube Q L The source of the freewheeling tube Q H of the drain.

[0022] Furthermore, the working principle of the double pulse test device includes:

[0023] Freewheeling tube Q H Pre-charging stage:

[0024] The first driving chip generates a total driving voltage A value, which is input into the first crosstalk suppression driving circuit. The first driving voltage of the first crosstalk suppression driving circuit is clamped to a value B by a Zener diode Z1 therein. At this time, the capacitor C1 stores a residual voltage C value, and then adjusts the values ​​of the resistor R1 and the capacitor C1 in the first crosstalk suppression driving circuit to adjust the decay time of the voltage C value, wherein A=B+C;

[0025] Control tube Q L Opening stage:

[0026] The control tube Q L When turned on, the second driving voltage of the second crosstalk suppression driving circuit is also clamped to the B value by the Zener diode Z1 located therein. At this time, the freewheeling tube Q H The gate-drain parasitic capacitance generates a charging current, and the NMOSFET Q1 in the first crosstalk suppression driving circuit is turned on, so that the generated charging current passes through the channel and does not flow through the driving current limiting resistor R2 in the first crosstalk suppression driving circuit, thereby suppressing the freewheeling tube Q H Forward crosstalk;

[0027] Control tube Q L Shutdown link:

[0028] The control tube Q L When turned off, the second driving voltage of the second crosstalk suppression driving circuit is -C value, and the freewheeling tube Q H The gate-drain parasitic capacitance generates a discharge current, and the NMOSFET Q1 in the first crosstalk suppression driving circuit is turned on, so that the generated discharge current passes through the channel, and does not flow through the driving current limiting resistor R2 in the first crosstalk suppression driving circuit, thereby suppressing the freewheeling tube Q H Negative positive crosstalk.

[0029] Compared with the prior art, the present invention has the following beneficial effects:

[0030] (1) The crosstalk suppression driving circuit of the present invention includes three parts: a negative voltage generating subcircuit, a driving current limiting resistor and a Miller clamping subcircuit. By generating a negative voltage when turned off and opening the gate channel of the NMOSFET, the driving circuit realizes multi-level driving and Miller clamping functions, thereby reducing crosstalk by controlling the switching speed.

[0031] (2) The crosstalk suppression driving circuit proposed in the present invention can suppress both positive and negative crosstalk voltages to below the safe voltage without sacrificing the high switching speed of the power device. In addition, the proposed crosstalk suppression driving circuit uses very few passive components, so it is suitable for integration in driver chips and power modules.

[0032] (3) The present invention is particularly directed to a power supply product of a bridge arm structure circuit, and is used for driving a switching device in the bridge arm circuit. It can effectively avoid the bridge arm direct-through problem and gate-source oxide layer breakdown problem of the bridge circuit.

[0033] (4) The crosstalk suppression driving circuit proposed in the present invention combines multi-level driving technology with Miller clamping technology. Compared with a single driving technology, its driving effect is better. First, by superimposing the negative voltage and Miller clamping scheme, the suppression effect of the crosstalk voltage can be further improved. In addition, the negative voltage of the negative voltage generating circuit is used to power the NMOSFET, making the Miller clamping faster and more effective. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of a crosstalk suppression driving circuit of the present invention;

[0035] Figure 2 is a schematic diagram of a conventional driving circuit of the present invention;

[0036] Figure 3 A schematic diagram of a simplified double pulse test device for a conventional GaN power device of the present invention;

[0037] Figure 4 A schematic diagram of a double pulse of a GaN power device of a crosstalk suppression driving circuit of the present invention;

[0038] Figure 5 This is a working mode diagram of the upper tube pre-charging link of the present invention;

[0039] Figure 6 This is a working mode diagram of the upper and lower tubes during forward crosstalk suppression of the present invention;

[0040] Figure 7 This is a working mode diagram of the upper and lower tubes during negative crosstalk suppression of the present invention;

[0041] Figure 8 The waveform diagram of the driving circuit after the crosstalk suppression circuit is adopted in the present invention;

[0042] Fig. 9 is an experimental waveform diagram of the conventional driving circuit of the present invention;

[0043] Fig.10 It is an experimental waveform diagram of the driving circuit of the present invention. DETAILED DESCRIPTION

[0044] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments. This embodiment is implemented based on the technical solution of the present invention, and provides a detailed implementation method and specific operation process, but the protection scope of the present invention is not limited to the following embodiments.

[0045] Example 1

[0046] Traditional driving circuits for GaN power devices such as Figure 2 As shown in the figure, there is only one driving current limiting resistor connected in series between the output side of the driving chip and the gate of the GaN power device. The corresponding simplified double pulse test device of the GaN power device is shown in the attached figure. Figure 3 As shown, it mainly includes: upper and lower tube GaN power devices Q H , Q L , where Q H For the freewheeling tube, Q L is the control tube. DC bus voltage V dc , load inductance L load .

[0047] Gate-source parasitic capacitance C of GaN power devices gs , gate-drain parasitic capacitance C gd , drain-source parasitic capacitance C ds , the gate drive resistor. The subscript "H" is related to the upper tube Q H The subscript "L" is related to the lower tube Q L The parameters of gs Connected between the gate and source of the GaN power device, C gd Connected between the gate and drain of GaN power devices, C ds Connect between the drain and source of the GaN power device. H With load inductance L load Parallel, Q H The drain of the DC power supply is connected to the positive terminal, Q H The source of Q L The drain, Q L The source of the capacitor is connected to the negative terminal of the DC voltage source. The traditional driving circuit used in the bridge circuit will face the influence of bridge arm crosstalk.

[0048] To this end, the present application provides a crosstalk suppression driving circuit for a power device, such as Figure 1 As shown, it includes a negative voltage generating sub-circuit, including a resistor R1, a capacitor C1 and a 6V Zener diode Z1; a driving current limiting resistor R2; and a Miller clamping sub-circuit, including an NMOSFET Q1, a parasitic diode D1 of the NMOSFET and an NMOSFET driving resistor R3. By generating a negative voltage when turned off and opening the gate channel of the NMOSFET, the driving circuit realizes multi-level driving and Miller clamping functions.

[0049] The left side of the resistor R1 in the negative voltage generating subcircuit is connected to the output port of the driving chip, the right side is connected to the driving current limiting resistor R2, and the capacitor C1 is connected in parallel with R1. The cathode of the 6V Zener diode Z1 is connected to the right side of R1 and C1. The left side of the driving current limiting resistor R2 is connected to the right side of R1, C1 and the cathode of the 6V Zener diode.

[0050] For the Miller clamp subcircuit, the drain of NMOSFET Q1 is connected to the right side of R1, the source is connected to the gate port of the power device, and the gate is connected to the source of the GaN power device through the NMOSFET driving resistor R3. The anode of the nanodiode Z1 is connected to the source of the NMOSFET, and the cathode is connected to the drain of the NMOSFET.

[0051] The specific working principle is: when the driving voltage is high, the 6V clamping diode will gs Clamped to 6V, the difference between the driving voltage and 6V is stored in capacitor C1. When turned off, the voltage on C1 can be used as a negative voltage to directly lower the positive crosstalk peak on the one hand, and drive the NMOSFET to open its channel, thereby providing a low-impedance path for the Miller current to achieve Miller clamping. In addition, it can also reduce the negative crosstalk peak.

[0052] In addition, the power devices of the embodiments of the present invention can use all other power switching devices in addition to GaN power devices, including but not limited to SiC Mosfet power devices, IGBT power devices, BJT power devices, SITH power devices, MCT power devices, IGCT power devices and IEGT power devices.

[0053] Example 2

[0054] This embodiment provides a double pulse test device for testing the crosstalk suppression effect of a crosstalk suppression driving circuit. Figure 4 As shown, the double pulse test device includes an upper tube unit and a lower tube unit connected in series therewith, wherein both the upper tube unit and the lower tube unit include the crosstalk suppression driving circuit in the above-mentioned embodiment 1, and the upper tube unit also includes a first driving chip, a freewheeling tube Q H and load inductance L load The lower tube unit also includes a second driver chip, a control tube Q L .

[0055] Specifically, the first driving chip is connected to the resistor R1 and the anode of the Zener diode Z1 in the first crosstalk suppression driving circuit respectively, and the freewheeling tube Q H The gate of is connected to the driving current limiting resistor R2 in the first crosstalk suppression driving circuit, and the freewheeling tube Q HThe drain and source are connected to the load inductor L load The second driving chip is respectively connected to the anode of the resistor R1 and the Zener diode Z1 in the second crosstalk suppression driving circuit, and the control tube Q L The gate of is connected to the driving current limiting resistor R2 in the second crosstalk suppression driving circuit, and the control tube Q L The drain of the freewheeling tube Q H The source of the control tube Q L The source of the freewheeling tube Q H of the drain.

[0056] The working principle of the double pulse test device to test the crosstalk suppression drive circuit is:

[0057] 1. Pre-charging stage of the upper tube (T4): Taking the 9V driving voltage as an example, in this stage, when the driving voltage is high, the driving circuit will be clamped to 6V by the 6V Zener diode Z1, and the 3V voltage is stored in the capacitor C1. At this time, the voltage drop speed can be adjusted by adjusting the values ​​of C1 and R1. Its working principle is as follows Figure 5 shown.

[0058] 2. Turning on the lower tube (T2): When the lower tube is turned on, the driving voltage of the lower tube is also clamped to 6V, which can meet the safe driving requirements of GaN power devices. gdH Generate charging current. Since there is a 3V negative voltage in the driving circuit of the upper tube at this time, the NMOSFET of the upper tube is turned on, and C gdH The charging current passes through the channel and does not flow through the driving resistor, so the forward crosstalk of the upper tube is suppressed, which can effectively avoid the bridge arm direct-through problem. Figure 6 shown.

[0059] 3. Turning off the lower tube (T3): When the lower tube is turned off, the driving voltage of the lower tube is -3V, which can accelerate the turning off of the lower tube. At this time, the Miller capacitance C of the upper tube gdH A discharge current is generated. Since there is a 3V negative voltage in the driving circuit of the upper tube at this time, the NMOSFET of the upper tube is turned on, and C gdH The charging current passes through the channel and does not flow through the driving resistor, so the negative crosstalk of the upper tube is suppressed, which can effectively avoid the problem of bridge arm direct conduction. Figure 7 shown.

[0060] The waveform of the driving circuit after adopting the crosstalk suppression circuit is as follows Figure 8 shown.

[0061] Finally, simulation is performed in LTspice to compare the traditional driving circuit with the driving circuit proposed in the embodiment of the present invention. The driving high level of the traditional driving circuit is 6V, and the driving low level is 0V. The driving high level in the embodiment of the present invention is 9V, and the driving low level is 0V. C1 used in the embodiment of the present invention is 10nF, R1 is 25Ω, R2 is 25Ω, R3 is 10Ω, and NMOSFET uses Infineon's BSC032NE2LS. Fig. 9 : is a simulation waveform diagram of a conventional driving circuit in an embodiment of the present invention. Fig.10 The following is a simulation waveform diagram of the driving circuit proposed in the embodiment of the present invention. Through simulation verification, the crosstalk suppression circuit proposed in the embodiment of the present invention has achieved a very effective effect in suppressing crosstalk.

[0062] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0063] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A crosstalk suppression driving circuit for a power device, connected between the gate source of the power device, characterized in that: The crosstalk suppression driving circuit includes a negative voltage generating subcircuit, a driving current limiting resistor R2 and a Miller clamping subcircuit, wherein the negative voltage generating subcircuit is respectively connected to the driving current limiting resistor R2 and the Miller clamping subcircuit, and the driving current limiting resistor R2 is connected to the Miller clamping subcircuit, wherein the negative voltage generating subcircuit is used to generate a negative voltage when turned off, wherein the driving current limiting resistor R2 is used to limit the current flowing through the gate of the power device to control its switching speed, and wherein the Miller clamping subcircuit is used to realize Miller clamping by driving a negative voltage.

2. A crosstalk suppression driving circuit for a power device according to claim 1, characterized in that: The negative voltage generating sub-circuit includes a resistor R1, a capacitor C1 and a Zener diode Z1, one end of the resistor R1 is connected to the output side of the driving chip in the power device, and the other end is connected to the driving current limiting resistor R2, the capacitor C1 is connected in parallel with the resistor R1, the cathode of the Zener diode Z1 is respectively connected to the other end of the resistor R1 and the driving current limiting resistor R2, and the anode of the Zener diode Z1 is connected to the source of the power device.

3. A crosstalk suppression driving circuit for a power device according to claim 1, characterized in that: The Miller clamp subcircuit includes an NMOSFET Q1, a parasitic diode D1 and an NMOSFET driving resistor R3. The NMOSFET Q1 is connected in parallel with the driving current limiting resistor R2. The NMOSFET Q1 is also connected to the NMOSFET driving resistor R3. The parasitic diode D1 is connected in parallel with the NMOSFET Q1.

4. A crosstalk suppression driving circuit for a power device according to claim 3, characterized in that: The NMOSFET Q1 includes three electrodes, namely a drain, a source and a gate. The drain and the source are respectively connected to the two ends of the driving current limiting resistor R2, and the two ends of the parasitic diode D1 are respectively connected to the drain and the source. The gate is connected to the source of the power device through the NMOSFET driving resistor R3.

5. A crosstalk suppression driving circuit for a power device according to claim 4, characterized in that: The parasitic diode D1 includes three electrodes, namely an anode and a cathode. The anode is connected to the source of the NMOSFET Q1, and the cathode is connected to the drain of the NMOSFET Q1.

6. A crosstalk suppression driving circuit for a power device according to claim 1, characterized in that: The types of power devices include GaN power devices, SiC Mosfet power devices, IGBT power devices, BJT power devices, SITH power devices, MCT power devices, IGCT power devices and IEGT power devices.

7. A double pulse test device, characterized in that: The double pulse test device comprises an upper tube unit and a lower tube unit, wherein the upper tube unit and the lower tube unit are connected in series, wherein the upper tube unit and the lower tube unit both comprise the crosstalk suppression driving circuit according to any one of claims 1 to 6, wherein the upper tube unit further comprises a first driving chip, a freewheeling tube Q H and load inductance L load The first driving chip is connected to the first crosstalk suppression driving circuit of the upper tube unit to generate a total driving voltage, and the first crosstalk suppression driving circuit is also connected to the freewheeling tube Q H Connect the freewheeling tube Q H Also with the load inductance L load The lower tube unit also includes a second driver chip and a control tube Q L The second driving chip is connected to the second crosstalk suppression driving circuit of the lower tube unit, and the second crosstalk suppression driving circuit is also connected to the control tube Q L Connect the control tube Q L Also with the freewheeling tube Q H connect.

8. A double pulse test device according to claim 7, characterized in that: The specific connection method of the upper tube unit is: The first driving chip is respectively connected to the resistor R1 and the anode of the Zener diode Z1 in the first crosstalk suppression driving circuit. H The gate of is connected to the driving current limiting resistor R2 in the first crosstalk suppression driving circuit, and the freewheeling tube Q H The drain and source are connected to the load inductor L load both ends of .

9. A double pulse test device according to claim 7, characterized in that: The specific connection method of the lower pipe unit is: The second driving chip is respectively connected to the resistor R1 and the anode of the Zener diode Z1 in the second crosstalk suppression driving circuit. L The gate of is connected to the driving current limiting resistor R2 in the second crosstalk suppression driving circuit, and the control tube Q L The drain of the freewheeling tube Q H The source of the control tube Q L The source of the freewheeling tube Q H of the drain.

10. A double pulse test device according to claim 7, characterized in that: The working principle of the double pulse test device includes: Freewheeling tube Q H Pre-charging stage: The first driving chip generates a total driving voltage A value, which is input into the first crosstalk suppression driving circuit. The first driving voltage of the first crosstalk suppression driving circuit is clamped to a value B by a Zener diode Z1 therein. At this time, the capacitor C1 stores a residual voltage C value, and then adjusts the values ​​of the resistor R1 and the capacitor C1 in the first crosstalk suppression driving circuit to adjust the decay time of the voltage C value, wherein A=B+C; Control tube Q L Opening stage: The control tube Q L When turned on, the second driving voltage of the second crosstalk suppression driving circuit is also clamped to the B value by the Zener diode Z1 located therein. At this time, the freewheeling tube Q H The gate-drain parasitic capacitance generates a charging current, and the NMOSFET Q1 in the first crosstalk suppression driving circuit is turned on, so that the generated charging current passes through the channel and does not flow through the driving current limiting resistor R2 in the first crosstalk suppression driving circuit, thereby suppressing the freewheeling tube Q H Forward crosstalk; Control tube Q L Shutdown link: The control tube Q L When turned off, the second driving voltage of the second crosstalk suppression driving circuit is -C value, and the freewheeling tube Q H The gate-drain parasitic capacitance generates a discharge current, and the NMOSFET Q1 in the first crosstalk suppression driving circuit is turned on, so that the generated discharge current passes through the channel, and does not flow through the driving current limiting resistor R2 in the first crosstalk suppression driving circuit, thereby suppressing the freewheeling tube Q H Negative positive crosstalk.

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