Operational amplifier with high common mode rejection ratio

Abstract

The invention discloses an operational amplifier with a high common-mode rejection ratio, which mainly solves the problems of low robustness and low signal transmission quality in the prior art. The circuit comprises a main body circuit, a common-mode rejection ratio improving circuit and a bias circuit T5, the main body circuit comprises a main body voltage-to-current module T1 and a current-to-voltage module T2, the common-mode rejection ratio improving circuit comprises a low-gain differential amplifier T3 and an auxiliary voltage-to-current module T4, two input ends of the T3 module are respectively connected with differential input voltage signals, and two output ends of the T3 module are respectively connected with the bias circuit T5. The main body voltage-to-current module T1 outputs two paths of amplified differential output voltage signals, the signals are converted into current through the auxiliary voltage-to-current module T4, the current is transmitted to the current-to-voltage module T2, the T2 carries out current-to-voltage and merging processing on the output current of the main body voltage-to-current module T1 and the output current of the auxiliary voltage-to-current module T4, and a voltage signal with a high common-mode rejection ratio is output. The method has high robustness and high signal transmission quality, and can be used for various analog systems and mixed signal systems.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic components, and particularly designs an operational amplifier with a high common mode rejection ratio, which can be used in various analog systems and mixed signal systems. Background Art

[0002] In recent years, with the rapid development of electronic products, semiconductor integrated circuit products have been widely used in various fields such as military and civilian use. For example, in the fields of computers, multimedia, and digital signal processing, the performance requirements for electronic products are getting higher and higher. If we analyze it to the bottom, we can find that the requirements for operational amplifiers are gradually increasing. This has prompted operational amplifiers to develop in the direction of low power consumption, high speed, high precision, high common-mode rejection ratio, and high power supply rejection ratio. In different applications, the requirements for operational amplifiers are also different. For example, in the signal chain system, most of them are fully differential inputs. Under ideal conditions, the input common-mode level remains unchanged, and the operational amplifier in the system only processes the differential signal. However, since the common-mode level of the external input signal often has certain disturbances, and the frequency and amplitude of the disturbance are related to the external environment, the disturbance of the common-mode level will introduce additional interference in the output signal, deteriorate the output signal quality, and reduce the system accuracy. Therefore, in such applications, operational amplifiers are often required to have a high common-mode rejection ratio.

[0003] Patent document with application number CN201210591649.6 discloses a low voltage high common mode rejection ratio operational amplifier circuit, such as Figure 1As shown, its main structure is a five-tube amplifier. The circuit in the dotted box assists the five-tube amplifier to improve the common mode rejection ratio. The differential input signal in the dotted box is connected to the gate of the fourth P-type transistor MP4 and the fifth P-type transistor MP5 respectively; the source and drain of MP4 and MP5 are connected together respectively; the drain of MP4 and MP5 is connected to the gate of the sixth P-type transistor MP6 and the gate of the third P-type transistor MP3. At the same time, the drain of the first N-type transistor MN1 is connected to the drain of MP1, and its gate is connected to the gate and drain of the second N-type transistor MN2; the drain of the third N-type transistor MN3 is connected to the drain of MP4 and MP5, and its gate is connected to the gate and drain of the fourth N-type transistor MN4, and the source of MN1, MN2, MN3, and MN4 is connected to the ground. Assuming that the common-mode level of the differential input signals VIN and VIP has a small positive increment at this time, the source end of the first P-type transistor MP1, the second P-type transistor MP2 and the gate of MP3 will also have a positive increment; similarly, the drain end of MP4 and MP5 will have a negative increment, that is, the gate of MP3 will have a negative increment; therefore, the potential of the drain end of MP3 increases and the potential of the gate end decreases, thereby ensuring that the source-drain current of MP3 remains basically unchanged, and the current flowing through MP1 and MP2 remains unchanged at this time, thereby improving the common-mode rejection ratio of the operational amplifier. However, in this circuit, since the gate of MP3 is biased and connected to the drain ends of MP4 and MP5, it is difficult to determine the static current in MP3, resulting in low robustness and inability to be applied to other complex occasions; and the circuit in the dotted box will introduce additional noise sources, deteriorating the noise performance of the overall circuit; Summary of the invention

[0004] The purpose of the present invention is to address the deficiencies of the above-mentioned prior art and propose a high common-mode rejection ratio operational amplifier to ensure that while improving the common-mode rejection ratio of the amplifier, it also has strong robustness, avoids additional noise sources, and improves the transmission quality of the signal.

[0005] To achieve the above object, the high common mode rejection ratio operational amplifier of the present invention comprises a main circuit, a common mode rejection ratio improvement circuit and a bias circuit T5, wherein the main circuit is a dual-input, single-output amplifier including a main voltage-to-current module T1 connected to a current-to-voltage module T2, and is characterized in that:

[0006] The common mode rejection ratio improving circuit comprises a low gain differential amplifier T3 and an auxiliary voltage-to-current module T4, wherein the low gain differential amplifier T3 is provided with two input terminals and two output terminals, and the auxiliary voltage-to-current module T4 is provided with four input terminals and two output terminals;

[0007] The two input terminals of the low-gain differential amplifier T3 are respectively connected to the differential input voltage signal, and are used to perform gain amplification on the differential input voltage signal, and output two amplified differential output voltage signals from the two output terminals, wherein one output voltage signal is connected to two inputs of the auxiliary voltage-to-current module T4, and the other output voltage signal is connected to the other two inputs of the auxiliary voltage-to-current module T4;

[0008] The auxiliary voltage-to-current module T4 performs voltage-to-current processing on the four-way input voltage signals, outputs two-way current signals and transmits them to the two input terminals of T2.

[0009] Preferably, the low-gain differential amplifier T3 comprises: a pre-voltage-to-current module T31 and a pre-current-to-voltage module T32;

[0010] The front voltage-to-current module T31 has an input end connected to a set of differential voltage signals VIP and VIN, and is used to convert the differential input signal into a differential current signal, and output it to the front current-to-voltage module T32;

[0011] The front-end current-to-voltage module T32 is used to convert the differential current signal output by the front-end voltage-to-current module T31 into a differential voltage signal, and output the differential voltage signal to the auxiliary voltage-to-current module T4.

[0012] Preferably, the first input end of the main voltage-to-current module T1 is connected to a differential signal VIP for voltage-to-current processing, and the second input end is connected to another differential signal VIN for voltage-to-current processing. The converted two differential current signals are connected to the two input ends of the current-to-voltage module T2.

[0013] Preferably, the current-to-voltage module T2 has a first input terminal connected to one output current signal of the main voltage-to-current module T1 and the auxiliary voltage-to-current module T4 for current-to-voltage processing, and a second input terminal connected to another output current signal of the main voltage-to-current module T1 and the auxiliary voltage-to-current module T4 for current-to-voltage processing, and the two converted voltage signals are merged to output a high common-mode rejection ratio voltage signal from the output terminal VOUT.

[0014] Compared with the prior art, the present invention has the following advantages:

[0015] Firstly, the present invention designs a common-mode rejection ratio enhancement circuit including a low-gain differential amplifier T3 and an auxiliary voltage-to-current module T4, obtains a common-mode disturbance voltage component in a differential input signal through the low-gain differential amplifier T3, converts it into a common-mode disturbance current component through the auxiliary voltage-to-current module T4, and then injects the common-mode disturbance current component into the current-to-voltage module T2, and cancels out the inverse common-mode disturbance current component output by the main voltage-to-current module T1, thereby greatly improving the common-mode rejection capability of the main circuit;

[0016] Secondly, the common-mode rejection ratio enhancement circuit in the present invention has a differential input voltage signal connected to its input, and is processed in turn by its internal low-gain differential amplifier T3 and auxiliary voltage-to-current module T4, and then input into the current-to-voltage module T2 in the form of current. Since it does not affect the current bias of the main circuit, it can not only determine the static current of all branches of the main circuit, but also make the common-mode rejection ratio enhancement circuit applicable to almost all types of operational amplifiers, such as: folded common-source common-gate amplifier, five-tube amplifier, sleeve amplifier, rail-to-rail input amplifier, etc., with strong robustness;

[0017] Thirdly, in the present invention, since the relevant noise sources of the low-gain differential amplifier T3 are respectively connected to the input end of the current-to-voltage module T2 through the auxiliary voltage-to-current module T4, the relevant noise sources can eventually cancel each other out at the output end of the current-to-voltage module T2, thereby improving the signal transmission quality of the main circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a circuit diagram of an existing low voltage high common mode rejection ratio operational amplifier;

[0019] Figure 2 It is a principle block diagram of a high common mode rejection ratio operational amplifier of the present invention;

[0020] Figure 3 A circuit diagram of a high common mode rejection ratio operational amplifier according to embodiment 1 of the present invention;

[0021] Figure 4 A circuit diagram of a high common mode rejection ratio operational amplifier according to Embodiment 2 of the present invention;

[0022] Figure 5 The following are comparison diagrams of the common mode rejection capability simulations of Example 1 of the present invention and the prior operational amplifier that does not include a common mode rejection enhancement module; DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, other embodiments obtained by ordinary technicians in this field without creative work should all fall within the scope of protection of the present invention.

[0024] Reference Figure 2 The high common-mode rejection ratio operational amplifier of this example includes a main circuit, a common-mode rejection ratio enhancement circuit and a bias circuit, wherein the main circuit includes a voltage-to-current module T1 and a current-to-voltage module T2, which is a dual-input, single-output amplifier; the common-mode rejection ratio enhancement circuit includes a low-gain differential amplifier T3 and an auxiliary voltage-to-current module T4, and the low-gain differential amplifier T3 includes a pre-voltage-to-current module T31 and a pre-current-to-voltage module T32; the bias circuit T5 is used to provide a bias voltage for the main circuit.

[0025] The first input end of the main voltage-to-current module T1 is connected to a differential signal VIP for voltage-to-current processing, and the second input end is connected to another differential signal VIN for voltage-to-current processing. The converted two differential current signals are respectively connected to the two input ends of the current-to-voltage module T2.

[0026] A front voltage-to-current module T31, whose input end is connected to a group of differential voltage signals VIP and VIN, is used to convert the differential input signal into a differential current signal, and output it to the front current-to-voltage module T32; the front current-to-voltage module T32 is used to convert the differential current signal output by the front voltage-to-current module T31 into a differential voltage signal, and connect one of the output voltage signals to two input ends of the auxiliary voltage-to-current module T4, and the other output voltage signal is connected to the other two input ends of the auxiliary voltage-to-current module T4; the auxiliary voltage-to-current module T4 performs voltage-to-current processing on the four input voltage signals, outputs two current signals and transmits them to the two input ends of T2;

[0027] The first input end of the current-to-voltage module T2 is connected to one output current signal of the main voltage-to-current module T1 and the auxiliary voltage-to-current module T4 for current-to-voltage processing, and the second input end is connected to another output current signal of the main voltage-to-current module T1 and the auxiliary voltage-to-current module T4 for current-to-voltage processing, and the two converted voltage signals are merged to output a high common-mode rejection ratio voltage signal from the output end VOUT.

[0028] Each of the above modules T1, T2, T3, and T4 can be implemented by building different circuit structures using multiple P-type transistors and multiple N-type transistors as needed.

[0029] It should be noted that the terms “first”, “second”… “Nth” in this specification, claims and the above-mentioned drawings.

[0030] Embodiment 1:

[0031] Reference Figure 3 , the high common mode rejection ratio operational amplifier of this example, its bias circuit T5 includes 4 P-type transistors MP and 8 N-type transistors MN; the main circuits T1 and T2 include 7 P-type transistors MP and 4 N-type transistors MN; the common mode rejection ratio enhancement circuits T3 and T4 include 3 P-type transistors MP and 6 N-type transistors MN; wherein:

[0032] The main voltage-to-current module T1 includes a fifth P-type transistor MP5, a sixth P-type transistor MP6, and a seventh P-type transistor MP7; the source end of MP5 is connected to the power supply VDD, the gate end is connected to the bias circuit module, and the drain end is connected to the source ends of MP6 and MP7; the gate ends of MP6 and MP7 are respectively connected to the differential input signals VIN and VIP, and are respectively connected to the two input ends of the low-gain differential amplifier T3, so as to output differential currents from their respective drain ends after performing voltage-to-current processing on the differential input signals.

[0033] The low-gain differential amplifier T3 includes a twelfth P-type transistor MP12, a thirteenth P-type transistor MP13, a fourteenth P-type transistor MP14, a thirteenth N-type transistor MN13, and a fourteenth N-type transistor MN14; the source end of MP12 is connected to a power supply VDD, the gate end is connected to a bias circuit module, and the drain end is connected to the source ends of MP13 and MP14; the gate ends of MP13 and MP14 are respectively connected to differential input signals VIN and VIP, and are respectively connected to two input ends of the main voltage-to-current module T1; the gate end and the drain end of MN13 are connected to the drain end of MP13; the gate end and the drain end of MN14 are connected to the drain end of MP14.

[0034] The auxiliary voltage-to-current module T4 includes a fifteenth N-type transistor MN15, a sixteenth N-type transistor MN16, a seventeenth N-type transistor MN17, and an eighteenth N-type transistor MN18; the gate end of MN15 and the gate end of MN16 are both connected to the gate end of MN14; the gate end of MN17 and the gate end of MN18 are both connected to the gate end of MN13; the drain end of MN15 is connected to the drain end of MN17 to form one output of the T4 module, and is connected to one output of the main voltage-to-current module T1 module to offset the common-mode component on this path; the drain end of MN16 is connected to the drain end of MN18 to form another output of the T4 module, and is connected to another output of the main voltage-to-current module T1 module to offset the common-mode component on this path;

[0035] The current-to-voltage module T2 includes an eighth P-type transistor MP8, a ninth P-type transistor MP9, a tenth P-type transistor MP10, an eleventh P-type transistor MP11, a ninth N-type transistor MN9, a tenth N-type transistor MN10, an eleventh N-type transistor MN11, and a twelfth P-type transistor MP12; the gate end of MN11, the gate end of MN12, the gate end of MN9, the gate end of MN10, the gate end of MP10, and the gate end of MP11 are all connected to the bias circuit module; the drain end of MN9 is respectively connected to the drain end of MP10 and the gate end of MP8; the drain end of MN10 is respectively connected to the output end VOUT and the drain end of MP11; the source end of MP10 is respectively connected to the drain end of MP8, and the source end of MP11 is connected to the drain end of MP9. The drain terminal of MN11 is respectively connected with the source terminal of MN9, one output terminal of the main voltage-to-current module T1, and one output terminal of the auxiliary voltage-to-current module T4, and is used to merge the output current in the main voltage-to-current module T1 with the output current in the auxiliary voltage-to-current module T4, and then convert it into a voltage through the gate terminal of MP8, and the voltage is converted into a current through MP9; the drain terminal of MN12 is respectively connected with the source terminal of MN10, another output terminal of the main voltage-to-current module T1, and another output terminal of the auxiliary voltage-to-current module T4, and is used to merge the output current in the main voltage-to-current module T1 with the output current in the auxiliary voltage-to-current module T4, and convert it into a high common-mode rejection ratio voltage signal, and output it from the output terminal VOUT.

[0036] The bias circuit T5 includes a first P-type transistor MP1, a second P-type transistor MP2, a third P-type transistor MP3, a fourth P-type transistor MP4, a first N-type transistor MN1, a second N-type transistor MN2, a third N-type transistor MN3, a fourth N-type transistor MN4, a fifth N-type transistor MN5, a sixth N-type transistor MN6, a seventh N-type transistor MN7, and an eighth N-type transistor MN8. The gate terminal of MN1 and the gate terminal of MN2 are both connected to the drain terminal of MN1, the source terminal of MN1 is connected to the drain terminal of MN2, and a first bias voltage signal VBNC is output, and the voltage signal is simultaneously connected to the gate terminals of MN9 and MN10 in the current-to-voltage module T2, providing a bias voltage for MN9 and MN10; the drain terminal of MN3 is simultaneously connected to the gate terminals of MN4, MN6, and MN8, and a second bias voltage signal VBN is output, and the voltage signal is simultaneously connected to the gate terminals of MN11 and MN12 in the current-to-voltage module T2, providing a bias voltage for MN11 and MN12, and the gate terminal of MN3 is respectively connected to the gate terminal of MN1, the gate terminal of MN2, the gate terminal of MN5, and the gate terminal of MN7; The source terminal of N5 is connected to the drain terminal of MN6, and the source terminal of MN7 is connected to the drain terminal of MN8; the gate terminal of MP1 is connected to the gate terminal of MP2, the drain terminal of MP2, the gate terminal of MP4, and the drain terminal of MN5, and outputs a third bias voltage signal VBPC. The voltage signal is also connected to the gate terminals of MP10 and MP11 in the current-to-voltage module T2 to provide a bias voltage for MP10 and MP11, and the drain terminal of MP1 is connected to the source terminal of MP2; the gate terminal of MP3 is connected to the drain terminal of MP4 and the drain terminal of MN7, and outputs a fourth bias voltage signal VBP. The voltage signal is also connected to the gate terminal of MP5 in the main voltage-to-current module T1 to provide a bias voltage for MP5, and the drain terminal of MP3 is connected to the source terminal of MP4.

[0037] The circuit works as follows:

[0038] One current source passes through MN1 and MN2 to generate a first bias voltage VBNC, and another current source passes through MN3 and MN4 to generate a second bias voltage VBN; the first bias voltage VBNC and the second bias voltage VBN pass through the gate terminals of MN6 and MN5 to generate a bias current, and then pass through MP1 and MP2 to generate a third bias voltage VBPC; the first bias voltage VBNC and the second bias voltage VBN pass through the gate terminals of MN8 and MN7 at the same time to generate another bias current, and then pass through MP3 and MP4 to generate a fourth bias voltage VBP;

[0039] The fourth bias voltage VBP provides bias for MP5 and MP12 through the gate terminals of MP5 and MP12; the third bias voltage VBPC provides bias for MP10 and MP11 through the gate terminals of MP10 and MP11; the first bias voltage VBNC provides bias for MN9 and MN10 through MN9 and MN10; the second bias voltage VBN provides bias for MN11 and MN12 through MN11 and MN12; the input full differential voltage signal is converted into a differential current signal through MP13 and MP14, and then converted into a differential voltage signal through MN13 and MN14, and then converted into a differential voltage signal through MN15, MN16, MN17 and MN18 are converted into two current signals; the input fully differential voltage signal is also converted into a differential current signal through MP6 and MP7. The current signal in MP6 is combined with the current in MN15 and MN17, converted into a voltage signal through MN11, MN9, MP10, and MP8, and then converted into a current signal through MP9; the current signal in MP7 is combined with the current in MN16 and MN18, and then converted into a high common-mode rejection ratio voltage signal through the small signal impedance of MN12, MN10, MP11, and MP9 with the current signal converted by MP9, and output from the output terminal VOUT.

[0040] Embodiment 2:

[0041] Reference Figure 4 In the high common mode rejection ratio operational amplifier of this embodiment, the main circuits T1 and T2 include 4 P-type transistors MP and 7 N-type transistors MN; the common mode rejection ratio enhancement circuits T3 and T4 include 6 P-type transistors MP and 3 N-type transistors MN; and the bias circuit T5 is the same as that in Embodiment 1.

[0042] The main voltage-to-current module T1 includes a twenty-fourth N-type transistor MN24, a twenty-fifth N-type transistor MN25, and a twenty-ninth N-type transistor MN19; the source end of MN19 is connected to the ground, the gate end is connected to the bias circuit module, and the drain end is connected to the source ends of MN24 and MN25; the gate ends of MN25 and MN25 are connected to the differential input signals VIN and VIP, and are respectively connected to the two input ends of the low-gain differential amplifier T3, so as to perform voltage-to-current processing on the differential input signals, and then output currents from their respective drain ends to connect to the two input ends of the current-to-voltage module T2.

[0043] The low-gain differential amplifier T3 includes a pre-voltage-to-current module T31 and a pre-current-to-voltage module T32; the pre-voltage-to-current module T31 includes a twenty-sixth N-type transistor MN26, a twenty-seventh N-type transistor MN27, and a twenty-eighth N-type transistor MN28; the pre-current-to-voltage module T32 includes a twenty-third P-type transistor MP23 and a twenty-fourth P-type transistor MP24; the source end of MN28 is connected to the ground, the gate end is connected to the bias circuit module, and the drain end is connected to the source ends of MN26 and MN27; the gate ends of MN26 and MN27 are respectively connected to the differential input signals VIN and VIP, and are respectively connected to the two input ends of the main voltage-to-current module T1; the gate end and the drain end of MP23 are connected to the drain end of MN27; the gate end and the drain end of MP24 are connected to the drain end of MN26.

[0044] The auxiliary voltage-to-current module T4 includes a twenty-second P-type transistor MP22, a twenty-first P-type transistor MP21, a nineteenth P-type transistor MP19, and a twentieth P-type transistor MP20; the gate end of MP22 and the gate end of MP21 are both connected to the gate end of MP23; the gate end of MP19 and the gate end of MP20 are both connected to the gate end of MP24; the drain end of MP19 is connected to the drain end of MP21 to form one output of the T4 module, and is connected to one output of the main voltage-to-current module T1 module, namely, the drain end of MN24, to offset the common-mode component on this path; the drain end of MP20 is connected to the drain end of MP22 to form another output of the T4 module, and is connected to another output of the main voltage-to-current module T1 module, namely, the drain end of MN25, to offset the common-mode component on this path; the common-mode rejection ratio is improved by offsetting the two common-mode components.

[0045] The current-to-voltage module T2 includes a seventeenth P-type transistor MP17, an eighteenth P-type transistor MP18, a fifteenth P-type transistor MP15, a sixteenth P-type transistor MP16, a twenty-second N-type transistor MN22, a twenty-third N-type transistor MN23, a twentieth N-type transistor MN20, and a twenty-first P-type transistor MP21; the gate end of MN22, the gate end of MN23, the gate end of MP15, the gate end of MP16, the gate end of MP17, and the gate end of MP18 are all connected to the bias circuit module; the drain end of MP15 is respectively connected to the drain end of MN22 and the gate end of MN20; the drain end of MN23 is respectively connected to the output end VOUT and the drain end of MP16; the source end of MN22 is connected to the drain end of MN20, and the source end of MN23 is connected to the drain end of MN21; the drain end of MP17 is respectively connected to the source end of MP15 and the main voltage One output terminal of the current conversion module T1, namely the drain terminal of MN25, and one output terminal of the auxiliary voltage conversion current module T4, namely the drain terminal of MN20 and MN22, are connected to combine the output current of the drain terminal of MN25 with the output current of the drain terminals of MN20 and MN22, and then convert it into a voltage through the gate terminal of MN20, and the voltage is then converted into a current through MN21; the drain terminal of MP18 is respectively connected to the source terminal of MP16, the drain terminal of another output terminal of the main voltage conversion current module T1, namely the drain terminal of MN24, and the drain terminal of another output terminal of the auxiliary voltage conversion current module T4, namely the drain terminal of MN19 and MN21, to combine the output current of the drain terminal of MN24 with the output current of the drain terminals of MN19 and MN21, and then convert it into a high common mode rejection ratio voltage signal with the current of the drain terminal of MN21 through the small signal impedance of MP16, MP18, MN23, and MN21 at the same time, and output it from the output terminal VOUT.

[0046] The bias circuit T5 has a circuit structure that is exactly the same as that of Example 1, and its connection relationship with the relevant transistors in the main voltage-to-current module T1 and the current-to-voltage module T2 is as follows: the first bias voltage VBNC is connected to the drain terminals of MN22 and MN23 in the current-to-voltage module T2; the second bias voltage VBN is respectively connected to the gate terminal of MN19 in the main voltage-to-current module T1 and the gate terminal of MN28 in the front voltage-to-current module T3; the third bias voltage VBPC is connected to the gate terminals of MP15 and MP16 in the current-to-voltage module T2; and the fourth bias voltage VBP is connected to the gate terminals of MP17 and MP18 in the current-to-voltage module T2.

[0047] The circuit works as follows:

[0048] One current source passes through MN1 and MN2 to generate a first bias voltage VBNC, and another current source passes through MN3 and MN4 to generate a second bias voltage VBN; the first bias voltage VBNC and the second bias voltage VBN pass through the gate terminals of MN6 and MN5 to generate a bias current, and then pass through MP1 and MP2 to generate a third bias voltage VBPC; the first bias voltage VBNC and the second bias voltage VBN pass through the gate terminals of MN8 and MN7 at the same time to generate another bias current, and then pass through MP3 and MP4 to generate a fourth bias voltage VBP;

[0049] The second bias voltage VBN provides bias for MN19 and MN28 through the gate terminals of MN19 and MN28; the first bias voltage VBNC provides bias for MP17 and MP18 through the gate terminals of MP17 and MP18; the third bias voltage VBPC provides bias for MP15 and MP16 through MP15 and MP16; the fourth bias voltage VBP provides bias for MP17 and MP18 through MP17 and MP18; the input full differential voltage signal is converted into a differential current signal through MN26 and MN27, and then converted into a differential voltage signal through MP24 and MP23, and then converted into a differential voltage signal through MP19, MP20 and MP 21 and MP22 are converted into two current signals; the input fully differential voltage signal is also converted into a differential current signal through MN24 and MN25; the current signal in MN25 is combined with the current in MP20 and MP22, converted into a voltage signal through MP17, MP15, MN22, and MN20, and then converted into a current signal through MN21; the current signal in MN24 is combined with the current in MP19 and MP21, and then converted into a high common-mode rejection ratio voltage signal with the current signal converted by MN21 through the small signal impedance of MP18, MP16, MN23, and MN21 at the same time, and output from the output terminal VOUT.

[0050] The effect of the present invention can be further illustrated by the following simulation experiment.

[0051] 1. Simulation conditions

[0052] Using Cadance Virtuoso software, set the temperature to 27°C and the power supply voltage to 3.3V.

[0053] 2. Simulation content

[0054] According to the above simulation conditions, the common mode rejection capability of the operational amplifier of Embodiment 1 of the present invention and the existing operational amplifier without the common mode rejection ratio enhancement module is simulated respectively. The results are as follows: Figure 5 shown.

[0055] from Figure 5It can be seen that the common-mode rejection capability of the first embodiment of the present invention becomes weaker as the frequency increases. In the frequency range of 1 Hz to 1000 Hz, the common-mode rejection capability of the first embodiment of the present invention is approximately -157 dB; while the common-mode rejection capability of the existing operational amplifier that does not include a common-mode rejection ratio enhancement module becomes weaker as the frequency increases. In the frequency range of 1 Hz to 1000 Hz, the common-mode rejection capability of the existing operational amplifier that does not include a common-mode rejection ratio enhancement module is approximately -124 dB;

[0056] By comparison, it is found that the common mode rejection capability of Example 1 of the present invention is enhanced by 33 dB compared with the existing operational amplifier that does not include a common mode rejection ratio enhancement module, indicating that the present invention has a stronger common mode rejection capability.

Claims

1. A high common mode rejection ratio operational amplifier, comprising a main circuit, a common mode rejection ratio improvement circuit and a bias circuit T5, wherein the main circuit is a dual-input, single-output amplifier including a main voltage-to-current module T1 connected to a current-to-voltage module T2, characterized in that: The common mode rejection ratio improving circuit comprises a low gain differential amplifier T3 and an auxiliary voltage-to-current module T4, wherein the low gain differential amplifier T3 is provided with two input terminals and two output terminals, and the auxiliary voltage-to-current module T4 is provided with four input terminals and two output terminals; The two input terminals of the low-gain differential amplifier T3 are respectively connected to the differential input voltage signal, and are used to perform gain amplification on the differential input voltage signal, and output two amplified differential output voltage signals from the two output terminals, wherein one output voltage signal is connected to two inputs of the auxiliary voltage-to-current module T4, and the other output voltage signal is connected to the other two inputs of the auxiliary voltage-to-current module T4; The auxiliary voltage-to-current module T4 performs voltage-to-current processing on the four-way input voltage signals, outputs two-way current signals and transmits them to the two input terminals of T2.

2. The high common mode rejection ratio operational amplifier according to claim 1, characterized in that: The low-gain differential amplifier T3 comprises: a pre-voltage-to-current module T31 and a pre-current-to-voltage module T32; The front voltage-to-current module T31 has an input end connected to a set of differential voltage signals VIP and VIN, and is used to convert the differential input signal into a differential current signal, and output it to the front current-to-voltage module T32; The front-end current-to-voltage module T32 is used to convert the differential current signal output by the front-end voltage-to-current module T31 into a differential voltage signal, and output the differential voltage signal to the auxiliary voltage-to-current module T4.

3. The high common mode rejection ratio operational amplifier according to claim 1, characterized in that: The first input end of the main voltage-to-current module T1 is connected to a differential signal VIP for voltage-to-current processing, and the second input end is connected to another differential signal VIN for voltage-to-current processing. The converted two differential current signals are connected to the two input ends of the current-to-voltage module T2.

4. The high common mode rejection ratio operational amplifier according to claim 1, characterized in that: The current-to-voltage module T2 has a first input terminal connected to one output current signal of the main voltage-to-current module T1 and the auxiliary voltage-to-current module T4 for current-to-voltage processing, and a second input terminal connected to another output current signal of the main voltage-to-current module T1 and the auxiliary voltage-to-current module T4 for current-to-voltage processing, and combines the two converted voltage signals to output a high common-mode rejection ratio voltage signal from the output terminal VOUT.

5. The high common mode rejection ratio operational amplifier according to claim 2, characterized in that: The front voltage-to-current module T31 is constructed by a plurality of P-type transistors or a plurality of N-type transistors; The front voltage-to-current module T31 composed of the plurality of P-type transistors includes a twelfth P-type transistor MP12, a thirteenth P-type transistor MP13, and a fourteenth P-type transistor MP14; The source end of MP12 is connected to the power supply VDD, the gate end is connected to the bias circuit module, and the drain end is connected to the source ends of MP13 and MP14; The gate terminals of MP13 and MP14 are respectively connected to the differential input signals VIN and VIP, and are respectively connected to the two input terminals of the main voltage-to-current module T1; they are used to perform voltage-to-current processing on the differential input signals, output current from their respective drain terminals, and connect to the two input terminals of the front current-to-voltage module T32; The front voltage-to-current module T31 composed of the plurality of N-type transistors includes a twenty-sixth N-type transistor MN26, a twenty-seventh N-type transistor MN27, and a twenty-eighth N-type transistor MN28; The source terminal of MN28 is connected to the ground, the gate terminal is connected to the bias circuit module, and the drain terminal is connected to the source terminals of MN26 and MN27; The gate terminals of MN26 and MN27 are respectively connected to the differential input signals VIN and VIP, and are respectively connected to the two input terminals of the main voltage-to-current module T1; they are used to perform voltage-to-current processing on the differential input signals, output current from their respective drain terminals, and connect to the two input terminals of the front current-to-voltage module T32.

6. The high common mode rejection ratio operational amplifier according to claim 2, characterized in that: The front-end current-to-voltage module T32 is constructed by a plurality of P-type transistors or a plurality of N-type transistors; The front current-to-voltage module T32 composed of the plurality of N-type transistors includes a thirteenth N-type transistor MN13 and a fourteenth N-type transistor MN14; The gate terminal and the drain terminal of MN13 are connected, and the drain terminal of MN13 is connected to an output current of the front voltage-to-current module T31, and converts the output current into a voltage signal, and outputs it to the auxiliary voltage-to-current module T4; The gate terminal and the drain terminal of the MN14 are connected, and the drain terminal of the MN14 is connected to another output current of the front voltage-to-current module T31, and converts it into another voltage signal, and outputs it to the auxiliary voltage-to-current module T4; The front current-to-voltage module T32 composed of the plurality of P-type transistors includes a twenty-third P-type transistor MP23 and a twenty-fourth P-type transistor MP24; The gate terminal and the drain terminal of MP23 are connected, and the drain terminal of MP23 is connected to an output current of the front voltage-to-current module T31, and converts it into a voltage signal, and outputs it to the auxiliary voltage-to-current module T4; The gate terminal and the drain terminal of MP24 are connected. The drain terminal of MP24 is connected to another output current of the front voltage-to-current module T31 and converts it into another voltage signal, which is output to the auxiliary voltage-to-current module T4.

7. The high common mode rejection ratio operational amplifier according to claim 1, characterized in that: The main voltage-to-current module T1 is constructed by a plurality of P-type transistors or a plurality of N-type transistors; The main voltage-to-current module T1 composed of the plurality of P-type transistors includes a fifth P-type transistor MP5, a sixth P-type transistor MP6, and a seventh P-type transistor MP7; The source end of MP5 is connected to the power supply VDD, the gate end is connected to the bias circuit module, and the drain end is connected to the source ends of MP6 and MP7; The gate terminals of MP6 and MP7 are connected to the differential input signals VIN and VIP, and are respectively connected to the two input terminals of the low-gain differential amplifier T3, so as to process the differential input signals from voltage to current, and then output currents from their respective drain terminals to the two input terminals of the current-to-voltage module T2; The main voltage-to-current module T1 composed of the plurality of N-type transistors includes a twenty-fourth N-type transistor MN24, a twenty-fifth N-type transistor MN25, and a twenty-ninth N-type transistor MN19; The source terminal of MN19 is connected to the ground, the gate terminal is connected to the bias circuit module, and the drain terminal is connected to the source terminals of MN24 and MN25; The gate terminals of MN25 and MN25 are connected to the differential input signals VIN and VIP, and are respectively connected to the two input terminals of the low-gain differential amplifier T3, so as to perform voltage-to-current processing on the differential input signals, and then output currents from their respective drain terminals to the two input terminals of the current-to-voltage module T2.

8. The high common mode rejection ratio operational amplifier according to claim 1, characterized in that: The auxiliary voltage-to-current module T4 is constructed by a plurality of P-type transistors or a plurality of N-type transistors; The auxiliary voltage-to-current module T4 constructed by a plurality of N-type transistors includes a fifteenth N-type transistor MN15, a sixteenth N-type transistor MN16, a seventeenth N-type transistor MN17, and an eighteenth N-type transistor MN18; The gate terminal of MN15 and the gate terminal of MN16 are both connected to the gate terminal of MN14; The gate terminal of MN17 and the gate terminal of MN18 are both connected to the gate terminal of MN13; The drain end of MN15 is connected to the drain end of MN17 to form an output of the T4 module, and is connected to one output of the main voltage-to-current module T1 module to offset the common mode component on this path; The drain end of MN16 is connected to the drain end of MN18 to form another output of the T4 module, and is connected to another output of the main voltage-to-current module T1 module to offset the common mode component on the path; The auxiliary voltage-to-current module T4 constructed by a plurality of P-type transistors includes a nineteenth P-type transistor MP19, a twentieth P-type transistor MP20, a twenty-second P-type transistor MP22, and a twenty-first P-type transistor MP21; The gate terminal of MP22 and the gate terminal of MP21 are both connected to the gate terminal of MP23; The gate terminal of MP19 and the gate terminal of MP20 are both connected to the gate terminal of MP24; The drain end of MP19 is connected to the drain end of MP21 to form an output of the T4 module, and is connected to one output of the main voltage-to-current module T1 module to offset the common mode component on this path; The drain end of MP20 is connected to the drain end of MP22 to form another output of the T4 module, and is connected to another output of the main voltage-to-current module T1 module to offset the common mode component on this path; By canceling out the two common-mode components, the common-mode rejection ratio is improved.

9. The high common mode rejection ratio operational amplifier according to claim 1, characterized in that: The main current-to-voltage module T2 includes a plurality of P-type transistors and a plurality of N-type transistors, and these P-type transistors and N-type transistors can be formed through different connection relationships; Connection relationship 1: the main current-to-voltage module T2 includes an eighth P-type transistor MP8, a ninth P-type transistor MP9, a tenth P-type transistor MP10, an eleventh P-type transistor MP11, a ninth N-type transistor MN9, a tenth N-type transistor MN10, an eleventh N-type transistor MN11, and a twelfth P-type transistor MP12; The gate terminals of MN11, MN12, MN9, MN10, MP10 and MP11 are all connected to the bias circuit module; The drain terminal of MN9 is connected to the drain terminal of MP10 and the gate terminal of MP8 respectively; The drain terminal of MN10 is connected to the output terminal VOUT and the drain terminal of MP11 respectively; The source end of MP10 is connected to the drain end of MP8, and the source end of MP11 is connected to the drain end of MP9; The drain terminal of MN11 is respectively connected to the source terminal of MN9, one output terminal of the main voltage-to-current module T1, and one output terminal of the auxiliary voltage-to-current module T4, and is used to combine the output current of the main voltage-to-current module T1 with the output current of the auxiliary voltage-to-current module T4, and then convert it into a voltage through the gate terminal of MP8, and the voltage is converted into a current through MP9; The drain end of MN12 is respectively connected to the source end of MN10, another output end of the main voltage-to-current module T1, and another output end of the auxiliary voltage-to-current module T4, so as to combine the output current of the main voltage-to-current module T1 with the output current of the auxiliary voltage-to-current module T4; The above two currents pass through MP9, MP11, MN10, and MN12 at the same time, and are converted into high common mode rejection ratio voltage signals, which are output from the output terminal VOUT; Connection relationship 2: the main current-to-voltage module T2 includes a seventeenth P-type transistor MP17, an eighteenth P-type transistor MP18, a fifteenth P-type transistor MP15, a sixteenth P-type transistor MP16, a twenty-second N-type transistor MN22, a twenty-third N-type transistor MN23, a twentieth N-type transistor MN20, and a twenty-first P-type transistor MP21; The gate terminals of MN22, MN23, MP15, MP16, MP17 and MP18 are all connected to the bias circuit module; The drain terminal of MP15 is connected to the drain terminal of MN22 and the gate terminal of MN20 respectively; The drain terminal of MN23 is connected to the output terminal VOUT and the drain terminal of MP16 respectively; The source terminal of MN22 is connected to the drain terminal of MN20, and the source terminal of MN23 is connected to the drain terminal of MN21; The drain end of MP17 is respectively connected to the source end of MP15, one output end of the main voltage-to-current module T1, and one output end of the auxiliary voltage-to-current module T4, and is used to combine the output current of the main voltage-to-current module T1 with the output current of the auxiliary voltage-to-current module T4, and then convert it into a voltage through the gate end of MN20, and the voltage is converted into a current through MN21; The drain end of MP18 is respectively connected to the source end of MP16, another output end of the main voltage-to-current module T1, and another output end of the auxiliary voltage-to-current module T4, so as to merge the output current of the main voltage-to-current module T1 with the output current of the auxiliary voltage-to-current module T4; The above two currents pass through MP16, MP18, MN23, and MN21 at the same time, are converted into high common-mode rejection ratio voltage signals, and are output from the output terminal VOUT.

10. The high common mode rejection ratio operational amplifier according to claim 1, characterized in that: The bias circuit T5 includes a plurality of P-type transistors and a plurality of N-type transistors, namely, a first P-type transistor MP1, a second P-type transistor MP2, a third P-type transistor MP3, a fourth P-type transistor MP4, a first N-type transistor MN1, a second N-type transistor MN2, a third N-type transistor MN3, a fourth N-type transistor MN4, a fifth N-type transistor MN5, a sixth N-type transistor MN6, a seventh N-type transistor MN7, and an eighth N-type transistor MN8; The gate terminal of MN1 and the gate terminal of MN2 are both connected to the drain terminal of MN1, the source terminal of MN1 is connected to the drain terminal of MN2, and a first voltage signal VBNC is output, and the voltage signal is simultaneously connected to the gate terminals of MN9 and MN10 in the current-to-voltage module T2; The drain terminal of MN3 is connected to the gate terminals of MN4, MN6 and MN8, and outputs a second voltage signal VBN, which is simultaneously connected to the gate terminals of MN11 and MN12 in the current-to-voltage module T2, and the gate terminal of MN3 is respectively connected to the gate terminals of MN1, MN2, MN5 and MN7; The source terminal of MN5 is connected to the drain terminal of MN6, and the source terminal of MN7 is connected to the drain terminal of MN8; The gate terminal of MP1 is connected to the gate terminal of MP2, the drain terminal of MP2, the gate terminal of MP4, and the drain terminal of MN5, and outputs a third voltage signal VBPC, which is simultaneously connected to the gate terminals of MP10 and MP11 in the current-to-voltage module T2, and the drain terminal of MP1 is connected to the source terminal of MP2; The gate terminal of MP3 is connected to the drain terminal of MP4 and the drain terminal of MN7, and outputs a fourth voltage signal VBP, which is also connected to the gate terminal of MP5 in the main voltage-to-current module T1. The drain terminal of MP3 is connected to the source terminal of MP4.

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