Level converter

Abstract

The invention provides a level converter which comprises a level conversion circuit and a voltage tracking circuit. The level conversion circuit receives an input signal through an input end and converts the input signal from a first power domain to a second power domain so as to generate an output signal at an output end. The voltage tracking circuit is coupled to the first power supply end and the second power supply end, and tracks one of the voltage of the first power supply end and the voltage of the second power supply end, which has a lower level, so as to generate a control voltage. The level conversion circuit includes a first N-type transistor and a second N-type transistor. The first N-type transistor has a gate coupled to the input terminal, a drain coupled to the first node, and a source coupled to the ground. The second N-type transistor has a gate for receiving the control voltage, a drain coupled to the output terminal at the second node, and a source coupled to the input terminal.

Description

Technical Field

[0001] The present invention relates to a level converter, and more particularly to a level converter without an input inverter. Background Art

[0002] In a multi-power integrated circuit, a level converter is required to convert a signal from one power domain to another power domain. However, the existing level converter is provided with at least one inverter on the input side to invert the input signal and provide it to the gate of at least one pull-down N-type transistor on the low voltage side. An inverter usually has a pair of N-type transistors and P-type transistors. Since an inverter provided on the input side is used to perform an inverse operation on the input signal, the power domain of the N-type well of the P-type transistor in the inverter is the power domain of the input signal. The circuit for level conversion includes a plurality of pull-up P-type transistors on the high voltage side, and the power domain of the N-type well of the P-type transistors is the power domain of the output signal. Therefore, it can be seen that the existing level converter requires two N-type wells in different power domains, which increases the size of the level converter. Summary of the invention

[0003] In view of this, the present invention proposes a level converter including a level conversion circuit and a voltage tracking circuit. The level conversion circuit receives an input signal through an input terminal, and converts the input signal from a first power domain to a second power domain to generate an output signal at an output terminal. The voltage tracking circuit is coupled to a first power terminal and a second power terminal, and tracks a first voltage of the first power terminal and a second voltage of the second power terminal, whichever has a lower level, to generate a control voltage. The level conversion circuit includes a first N-type transistor and a second N-type transistor. The first N-type transistor has a gate coupled to the input terminal, a drain coupled to a first node, and a source coupled to a ground. The second N-type transistor has a gate for receiving the control voltage, a drain coupled to the output terminal at a second node, and a source coupled to the input terminal.

[0004] The present invention proposes a level converter including a level conversion circuit and a voltage tracking circuit. The level conversion circuit receives an input signal through an input terminal, and converts the input signal from a first power domain to a second power domain to generate an output signal at an output terminal. The voltage tracking circuit is coupled to a first power terminal and a second power terminal, and tracks a first voltage of the first power terminal and a second voltage of the second power terminal, whichever has a lower level, to generate a control voltage. The level conversion circuit includes a first P-type transistor and a first N-type transistor. The first P-type transistor has a gate, a source coupled to the second power terminal, and a drain coupled to the output terminal at a first node. The first N-type transistor has a gate that receives the control voltage, a drain coupled to the first node, and a source coupled to the input terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The present application can be more fully understood through the following detailed description of the embodiments in conjunction with the accompanying drawings, in which:

[0006] Figure 1 A level converter according to an embodiment of the present invention;

[0007] Figure 2 is a schematic diagram of the operation of a level converter in a first mode according to another embodiment of the present invention;

[0008] Figure 3 is a schematic diagram of the operation of the level converter in the second mode according to another embodiment of the present invention;

[0009] Figure 4 FIG. 4 is a schematic diagram of an operation of a level converter in a third mode according to another embodiment of the present invention.

[0010] [Explanation of symbols]

[0011] 1: Level Converter

[0012] 10,11,14,15: N-type transistors

[0013] 12,13,18: P-type transistor

[0014] 10A,11A,12A,13A,14A,15A,18A: Gate

[0015] 10B,11B,12B,13B,14B,15B,18B: drain

[0016] 10C, 11C, 12C, 13C, 14C, 15C, 18C: Source

[0017] 10D,11D,12D,13D,14D,15D,18D: base

[0018] 16: Level conversion circuit

[0019] 17: Voltage tracking circuit

[0020] GND: Ground

[0021] IN: Input signal

[0022] N10~N14: Node

[0023] OUT: Output signal

[0024] T10: Input terminal

[0025] T11: Output terminal

[0026] T12, T13: Power supply terminal

[0027] V20, V30, V40: control voltage

[0028] VDD,VDDPST: voltage DETAILED DESCRIPTION

[0029] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, a preferred embodiment is given below and described in detail with reference to the accompanying drawings.

[0030] Figure 1 FIG. 1 is a level converter 1 according to an embodiment of the present invention. Figure 1 The level converter 1 includes a level converter circuit 16 and a voltage tracking circuit 17. The level converter circuit 16 is coupled to a power supply terminal T12 and a ground GND. The level converter circuit 16 has an input terminal T10 and an output terminal T11. When the level converter circuit 16 operates, an input signal (such as a voltage tracking circuit 17) received through the input terminal T10 is Figure 2 , Figure 3 as well as Figure 4 ) performs a level conversion operation to generate a corresponding output signal (such as Figure 2 , Figure 3 as well as Figure 4 Specifically, when the level conversion circuit 16 operates, an input signal received through the input terminal T10 is converted from one power domain to another power domain to generate a corresponding output signal (such as Figure 2 , Figure 3 as well as Figure 4 shown).

[0031] Referring to FIG. 1 , the level conversion circuit 16 includes N-type transistors 10 and 11 and P-type transistors 12, 13, and 18. In this embodiment, transistors 10 to 13 and 18 are implemented as metal-oxide-semiconductor (MOS) transistors. The N-type transistor 10 has a gate 10A, a drain 10B, a source 10C, and a base 10D. The gate 10A is coupled to the input terminal T10, the drain 10B is coupled to the node N10, the source 10C is coupled to the ground GND, and the base 10D is coupled to the ground GND. The N-type transistor 11 has a gate 11A, a drain 11B, a source 11C, and a base 11D. The gate 11A is coupled to the voltage tracking circuit 17 to receive the control voltage generated therein (such as Figure 2 , Figure 3 as well as Figure 4 As shown in FIG. 1 , the drain 11B outputs the terminal T11 at the node N11 , the source 11C is coupled to the input terminal T10 , and the base 11D is coupled to the ground GND.

[0032] The P-type transistor 12 has a gate 12A, a drain 12B, a source 12C, and a base 12D. The gate 12A is coupled to the node N11 (i.e., coupled to the output terminal T11), the source 12C is coupled to the power supply terminal T12, the drain 12B is coupled to the node N10, and the base 12D is coupled to the power supply terminal T12. The P-type transistor 13 has a gate 13A, a drain 13B, a source 13C, and a base 13D. The gate 13A is coupled to the node N10, the source 13C is coupled to the power supply terminal T12, the drain 13B is coupled to the node N11, and the base 13D is coupled to the power supply terminal T12. The P-type transistor 18 has a gate 18A, a drain 18B, a source 18C, and a base 18D. The gate 18A is coupled to the power terminal T12 , the source 18C is coupled to the power terminal T12 , the drain 18B is coupled to the node N11 , and the base 18D is coupled to the power terminal T12 .

[0033] The voltage tracking circuit 17 is coupled to the power terminals T12 and T13, and tracks the voltage of the power terminal T12 and the voltage of the power terminal T13 which has a lower level to generate a control voltage. In the embodiment of the present invention, the voltage tracking circuit 17 only includes N-type transistors and does not include any P-type transistors. Figure 1, the voltage tracking circuit 17 includes N-type transistors 14 and 15. In this embodiment, the transistors 14 and 15 are implemented by MOS transistors. The N-type transistor 14 has a gate 14A, a drain 14B, a source 14C, and a base 14D. The gate 14A is coupled to the power supply terminal T12 at the node N13, the drain 14B is coupled to the power supply terminal T13 at the node N12, the source 14C is coupled to the node N14, and the base 14D is coupled to the ground GND. The N-type transistor 15 has a gate 15A, a drain 15B, a source 15C, and a base 15D. The gate 15A is coupled to the node N12, the drain 15B is coupled to the node N13, the source 15C is coupled to the node N14, and the base 15D is coupled to the ground GND.

[0034] See also Figure 1 The gate 11A of the N-type transistor 11 is coupled to the voltage tracking circuit 17 at the node N14. The voltage tracking circuit 17 generates a control voltage at the node N14. Therefore, the gate 11A receives the control voltage generated by the voltage tracking circuit 17 through the node N14.

[0035] The following is through Figure 2 , Figure 3 as well as Figure 4 The operations of the level converter 1 of the present application in the first to third modes are described below.

[0036] See also Figure 2 When the level converter 1 operates in the first mode, the power terminal T12 receives the voltage VDDPST, and the power terminal T13 receives the voltage VDD. The voltage VDDPST is greater than the voltage VDD. In this embodiment, the voltage VDD is, for example, 1.8 volts (Volt, V), and the voltage VDDPST is, for example, 6V. In the voltage tracking circuit 17, based on the voltages VDD and VDDPST, both the N-type transistors 14 and 15 can be turned on. Since the voltage VDDPST (6V) is greater than the voltage VDD (1.8V), the N-type transistor 14 is more easily turned on than the N-type transistor 15, so that the control voltage V20 on the node N14 is close to or equal to the voltage VDD (1.8V). In this way, the voltage tracking circuit 17 tracks the voltage VDDST (6V) of the power terminal T12 and the voltage VDD (1.8V) of the power terminal T13, whichever has a lower level, to generate a control voltage V20 (1.8V) equal to the voltage VDD.

[0037] The level conversion circuit 16 receives the input signal IN through the input terminal T10. The input signal IN is provided by a device or circuit in the power domain of the voltage VDD (hereinafter referred to as the VDD power domain). The voltage level of the input signal IN is between 0V and 1.8V (voltage VDD). When the input signal IN is at a voltage level of 0V, the N-type transistor 10 is turned off. Based on the control voltage V20 of 1.8V (VDD), the N-type transistor 11 is turned on (ON), so that the voltage on the node N11 is equal to the voltage of the input signal IN (0V). Based on the voltage of 0V on the node N11, the P-type transistor 12 is turned on, so that the voltage on the node N10 is equal to the voltage VDDPST (6V). According to the voltage of 6V on the node N10, the P-type transistor 13 is turned off. In addition, the P-type transistor 18 is turned off according to the voltage VDDPST.

[0038] According to the above operation, the voltage on the node N11 is equal to the voltage (0V) of the input signal IN through the turned-on N-type transistor 11, and therefore, the output signal OUT of 0V is generated at the output terminal T11 coupled to the node N11. In this case, since both the P-type transistors 13 and 18 are in the off state, the output signal OUT can be stably at a voltage level of 0V along with the input signal IN.

[0039] In the first mode, when the input signal IN has a voltage level of VDD (1.8V), the N-type transistor 10 is turned on. Through the turned-on N-type transistor 10, the voltage on the node N10 is equal to the voltage of the ground GND, for example, 0V. According to the voltage of 0V on the node N10, the P-type transistor 13 is turned on. At this time, since the control voltage V20 of 1.8V (VDD) is low, it is difficult for the N-type transistor 11 to be turned on by the control voltage V20.

[0040] According to the above operation, the voltage on the node N11 is equal to the voltage VDDPST (6V) through the turned-on P-type transistor 13, and the 6V output signal OUT is generated at the output terminal T11 coupled to the node N11. In this case, according to the 6V voltage on the node N11, the P-type transistor 12 is turned off, so that the node N10 is not affected by the voltage VDDPST and can be stably at the voltage level of 0V. According to the above operation, the level conversion circuit 16 converts the input signal IN from the VDD power domain to the power domain of the voltage VDDPST (hereinafter referred to as the VDDPST power domain) to generate the 6V output signal OUT at the output terminal T11, thereby completing the level conversion operation.

[0041] See also Figure 3When the level converter 1 operates in the second mode, the power terminal T12 receives the voltage VDDPST (6V), and the power terminal T13 receives the voltage of 0V. The fact that the power terminal T13 receives the voltage of 0V indicates that the power terminal T13 does not receive the voltage VDD, that is, the power of the device or circuit generating the input signal IN is turned off. The N-type transistor 14 is turned on according to the voltage VDDPST (6V), and the N-type transistor 15 is turned off according to the voltage of 0V. Through the turned-on N-type transistor 14, the voltage V30 on the node N14 is close to or equal to 0V. In this way, the voltage tracking circuit 17 tracks the voltage VDDST (6V) of the power terminal T12 and the voltage of 0V on the power terminal T13, whichever has a lower level, to generate a control voltage V30 equal to 0V.

[0042] The level conversion circuit 16 receives an input signal IN through the input terminal T10. Since the power of the device or circuit generating the input signal IN is turned off, the voltage level of the input signal IN is 0V, so as to turn off the N-type transistor 10. Based on the control voltage V30 of 0V, the N-type transistor 11 is turned off. At this time, the node N11 is in a floating state. Subsequently, the node N11 is charged by the leakage current flowing through the P-type transistors 13 and 18, and the voltage on the node N11 is close to or equal to the voltage VDDPST (6V), and the output signal OUT of 6V is generated at the output terminal T11 coupled to the node N11. According to the above, when the power terminal T13 does not receive the voltage VDD (in the second mode), the level converter 1 can generate the output signal OUT of 6V, so as to avoid the output terminal T11 being in a floating state to cause malfunction of the subsequent circuit.

[0043] See also Figure 4 When the level converter 1 operates in the third mode, the power terminal T12 receives a voltage of 0V, and the power terminal T13 receives a voltage VDD (1.8V). The power terminal T12 receiving a voltage of 0V indicates that the power terminal T12 does not receive the voltage VDDPST, which means that the power of the power domain where the level converter 1 is located is turned off. The N-type transistor 14 is turned off according to the voltage of 0V, and the N-type transistor 15 is turned on according to the voltage VDD (1.8V). Through the turned-on N-type transistor 15, the voltage V40 on the node N14 is close to or equal to 0V. In this way, the voltage tracking circuit 17 tracks the voltage of 0V on the power terminal T12 and the voltage VDD (1.8V) on the power terminal T13, whichever has a lower level, to generate a control voltage V40 equal to 0V.

[0044] The level conversion circuit 16 receives an input signal IN whose voltage level is between 0V and 1.8V (voltage VDD) through the input terminal T10. When the input signal IN is at a voltage level of 0V, the N-type transistor 10 is turned off. Based on the control voltage V40 of 0V, the N-type transistor 11 is turned off. At this time, the node N11 is in a floating state. Subsequently, through the path of the leakage current of the P-type transistors 13 and 18, the voltage on the node N11 is close to or equal to the voltage of 0V on the power supply terminal T12. The output signal OUT of 0V is generated at the output terminal T11 coupled to the node N11.

[0045] In the third mode, when the input signal IN is at a voltage level of 1.8V, the N-type transistor 10 is turned on. Through the turned-on N-type transistor 10, the voltage on the node N10 is equal to the voltage of the ground GND (0V). Based on the control voltage V40 of 0V, the N-type transistor 11 is turned off (OFF). At this time, according to the voltage of 0V on the node N10, the P-type transistor 13 is turned on. Through the turned-on P-type transistor 13, the voltage on the node N11 is equal to the voltage of 0V on the power supply terminal T12. The voltage of 0V on the node N11 turns on the P-type transistor 12, so that the node N10 can stably have a voltage of 0V. The output signal OUT of 0V is generated at the output terminal T11 coupled to the node N11.

[0046] According to the above operation, in the third mode, no matter the voltage level of the input signal IN is between 0V and 1.8V, the output signal OUT generated by the level converter 1 has a voltage level of 0V.

[0047] According to the above embodiment, the gate 11A of the pull-down N-type transistor 11 on the output side of the level converter 1 receives the control voltage generated by the voltage tracking circuit 17. Compared with the existing level converter, the level converter 1 of the present application does not have any inverter in the VDD power domain at the input terminal T10. That is, the input signal IN received from the input terminal T10 is directly provided to the level conversion circuit 16 without passing through any inverter. In this way, the level converter 1 of the present application only needs to form the N-type wells of the P-type transistors 12, 13, and 18 in the VDDPST power domain, which reduces the size of the level converter 1.

[0048] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the claims.

Claims

1. A level converter, characterized in that: include: A level conversion circuit receives an input signal through an input terminal and converts the input signal from a first power domain to a second power domain to generate an output signal at an output terminal; as well as A voltage tracking circuit is coupled to a first power terminal and a second power terminal, and tracks a first voltage of the first power terminal and a second voltage of the second power terminal, which has a lower level, to generate a control voltage; Wherein, the level conversion circuit comprises: a first N-type transistor having a gate coupled to the input terminal, a drain coupled to a first node, and a source coupled to a ground; and A second N-type transistor has a gate receiving the control voltage, a drain coupled to the output terminal at a second node, and a source coupled to the input terminal.

2. The level converter according to claim 1, characterized in that: All transistors in the voltage tracking circuit are N-type transistors.

3. The level converter according to claim 1, wherein: The voltage tracking circuit comprises: a third N-type transistor having a gate coupled to the second power supply terminal at a third node, a drain coupled to the first power supply terminal at a fourth node, and a source coupled to a fifth node; as well as a fourth N-type transistor having a gate coupled to the fourth node, a drain coupled to the third node, and a source coupled to the fifth node; The gate of the second N-type transistor is coupled to the fifth node, and the control voltage is generated at the fifth node.

4. The level converter according to claim 1, wherein: Also includes: a first P-type transistor having a gate coupled to the second node, a source coupled to the second power terminal, and a drain coupled to the first node; as well as A second P-type transistor has a gate coupled to the first node, a source coupled to the second power terminal, and a drain coupled to the second node.

5. The level converter according to claim 4, characterized in that: Also includes: A third P-type transistor has a gate and a source coupled to the second power terminal, and a drain coupled to the second node.

6. The level converter according to claim 1, wherein: The first power terminal receives a first power voltage of the first power domain as the first voltage, and the second power terminal receives a second power voltage of the second power domain as the second voltage, and the first voltage is lower than the second voltage.

7. The level converter according to claim 1, wherein: The first power end receives a shutdown voltage corresponding to a shutdown state of the first power domain as the first voltage, the second power end receives a power voltage of the second power domain as the second voltage, and the first power voltage is lower than the second power voltage.

8. The level converter according to claim 1, wherein: The first power end receives a first power voltage of the first power domain as the first voltage, and the second power end receives a shutdown voltage corresponding to a shutdown state of the second power domain as the second voltage, and the second power voltage is lower than the first power voltage.

9. A level converter, characterized in that: include: A level conversion circuit receives an input signal through an input terminal and converts the input signal from a first power domain to a second power domain to generate an output signal at an output terminal; as well as A voltage tracking circuit is coupled to a first power terminal and a second power terminal, and tracks a first voltage of the first power terminal and a second voltage of the second power terminal, which has a lower level, to generate a control voltage; Wherein, the level conversion circuit comprises: a first P-type transistor having a gate, a source coupled to the second power supply terminal, and a drain coupled to the output terminal at a first node; and A first N-type transistor has a gate receiving the control voltage, a drain coupled to the first node, and a source coupled to the input terminal.

10. The level converter according to claim 9, characterized in that: The voltage tracking circuit comprises: a second N-type transistor having a gate coupled to the second power supply terminal at a second node, a drain coupled to the first power supply terminal at a third node, and a source coupled to a fourth node; as well as a third N-type transistor having a gate coupled to the third node, a drain coupled to the second node, and a source coupled to the fourth node; The gate of the first N-type transistor is coupled to the fourth node, and the control voltage is generated at the fourth node.

11. The level converter according to claim 10, wherein: The level conversion circuit also includes: a second P-type transistor having a gate coupled to the first node, a source coupled to the second power supply terminal, and a drain coupled to a fifth node; as well as a fourth N-type transistor having a gate coupled to the input terminal, a drain coupled to the fifth node, and a source coupled to the ground; The gate of the first P-type transistor is coupled to the fifth node.

12. The level converter according to claim 11, wherein: Also includes: A third P-type transistor has a gate and a source coupled to the second power terminal, and a drain coupled to the first node.

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