Digital-to-analog converter structure determination method and digital-to-analog converter structure

Abstract

The invention provides a digital-to-analog converter structure determination method and a digital-to-analog converter structure, and the method comprises the steps: building a combined resistor segment under the condition that a resistor simulation result does not meet a preset condition; random mismatch calibration is carried out on the combined resistor segments through directional element matching; under the condition that random mismatch calibration reaches a set calibration condition, resistance simulation is carried out on the combined resistor segments; under the condition that the simulation result of the resistance simulation does not meet the preset condition, resistance nonlinear calibration is carried out on the combined resistance segments; the structure of the digital-to-analog converter is determined through combination type resistor segmentation of resistor non-linear calibration. The digital-to-analog converter is arranged by adopting a combined resistor segmented resistor structure, compromise between the area and the precision can be realized, and the precision of the digital-to-analog converter is improved while the size of the digital-to-analog converter is reduced. In addition, the random mismatch of the resistor is calibrated by adopting a directional element matching technology, so that the calibration cost is relatively low.

Description

Technical Field

[0001] The present application relates to the field of electronic circuits, and in particular to a method for determining a digital-to-analog converter structure and a digital-to-analog converter structure. Background Art

[0002] In modern digital signal processing and analog circuit design, the digital-to-analog converter (DAC) plays a vital role in converting digital signals into corresponding analog signals. The resistive DAC achieves digital-to-analog conversion through resistor voltage division, and its output noise is mainly determined by the thermal noise of the resistor, which decreases approximately linearly with decreasing temperature, so the resistive DAC has excellent noise performance at low temperatures. Most high-precision DACs rely on precise resistor arrays to complete data conversion, so their accuracy is very sensitive to the matching degree of the resistor network.

[0003] However, under low temperature conditions, the physical characteristics of the resistor element will change significantly, and these changes will directly lead to a decrease in the accuracy of the DAC output analog signal. Summary of the invention

[0004] In view of this, an object of the embodiments of the present application is to provide a method for determining a digital-to-analog converter structure and a digital-to-analog converter structure, which can improve the accuracy of the digital-to-analog converter while reducing the size of the digital-to-analog converter.

[0005] In a first aspect, an embodiment of the present application provides a method for determining a structure of a digital-to-analog converter, comprising: constructing a combined resistor segment when a resistance simulation result does not meet a preset condition; performing a random mismatch calibration on the combined resistor segment through directional element matching; performing a resistance simulation on the combined resistor segment when the random mismatch calibration reaches a set calibration condition; performing a resistance nonlinearity calibration on the combined resistor segment when a simulation result of the resistance simulation does not meet the preset condition; and determining the structure of the digital-to-analog converter through the combined resistor segment with the resistance nonlinearity calibration.

[0006] In the above implementation process, the digital-to-analog converter is set by adopting a combined resistor segmented resistor structure. Since the combined resistor segment combines the advantages of the thermometer structure and the binary coding structure, a compromise between area and accuracy can be achieved, and the accuracy of the digital-to-analog converter can be improved while reducing the volume of the digital-to-analog converter. In addition, the random mismatch of the resistor is calibrated by adopting the directional element matching technology. Since the directional element matching technology only needs to change the decoding method of the thermometer code segment, the calibration cost is very low, which can reduce the cost of determining the structure of the digital-to-analog converter.

[0007] In one embodiment, the combined resistor segment includes: a higher weight bit and a lower weight bit; the random mismatch calibration of the combined resistor segment through directional element matching includes: sorting the resistor pins of all thermometer-type structures in the higher weight bit according to the resistance value; pairing two symmetrically distributed resistor pins among the resistor pins after the resistance value sorting to obtain a folded higher weight bit; starting from sorting the resistor pins of all thermometer-type structures in the folded higher weight bit according to the resistance value, repeating until the iteration termination condition is reached to obtain a completely folded higher weight bit; wherein the completely folded higher weight bit is a binary code structure.

[0008] In the above implementation process, the resistor pins of the thermometer type structure are completely folded, which can greatly reduce the random mismatch error between the resistor pins of the thermometer type structure and improve the random mismatch accuracy.

[0009] In one embodiment, the method further includes: constructing a calibration bit; setting the calibration bit on a side of the lower weight bit away from the higher weight bit; wherein the calibration bit is configured to reserve the calibration space of the lower weight.

[0010] In the above implementation process, by setting a calibration bit on the side of the lower weight bit away from the higher weight bit, calibration space can be reserved for the lower weight. When the lower weight bit needs to be calibrated, it can be calibrated through the calibration bit, thereby improving calibration flexibility.

[0011] In one embodiment, a portion of the resistor pins in each region in the higher weight bit is connected to a voltage, and another portion of the resistor pins in each region is grounded; the resistor pins are connected to a PMOS transistor and an NMOS transistor, and the gates of the PMOS transistor and the NMOS transistor are respectively connected to two R-2R digital-to-analog converter biases; the PMOS transistor and the NMOS transistor constitute a complementary transmission gate switch; the resistance nonlinear calibration of the combined resistor segment includes: determining the on-resistance that needs to be adjusted based on the relationship between the output voltage of the combined resistor segment and a preset voltage; wherein the on-resistance is connected to the complementary transmission gate switch; the on-resistance is adjusted by controlling the R-2R digital-to-analog converter bias; wherein the on-resistance configuration bit compensates for the nonlinear change of the corresponding resistor pin.

[0012] In the above implementation process, by determining the on-resistance that needs to be adjusted based on the relationship between the output voltage and the preset voltage, and adjusting the on-resistance by controlling the bias of the digital-to-analog converter, the nonlinear change of the corresponding resistor pin can be compensated, so that the nonlinear change of the sum of the switch resistance and the resistance pin within the output voltage range of the digital-to-analog converter is reduced, thereby improving the nonlinear calibration capability.

[0013] In one embodiment, when the resistance simulation result does not meet the preset conditions, building a combined resistance segment includes: building a plurality of combined resistance segments respectively according to the digital-to-analog converter; wherein the higher weight bit in each of the combined resistance segments adopts a thermometer code structure, and the lower weight bit in each of the combined resistance segments adopts a binary coding structure; according to the accuracy of the binary coding structure in each combined resistance segment, determining the main combined resistance segment; the main combined resistance segment is configured to construct the digital-to-analog converter; and performing random mismatch calibration on the combined resistance segment by directional element matching, including: performing random mismatch calibration on the main combined resistance segment by directional element matching.

[0014] In the above implementation process, by selecting the main body combined resistor segment according to the accuracy and then constructing the digital-to-analog converter, the main body combined resistor segment that meets the accuracy requirement of the digital-to-analog converter can be determined to improve the accuracy of the digital-to-analog converter.

[0015] In one embodiment, before performing random mismatch calibration on the combined resistor segment by directional element matching, the method further includes: judging whether the main combined resistor segment needs to be further segmented according to the occupied area of ​​the thermometer code structure of the main combined resistor segment; and further segmenting the thermometer code structure of the main combined resistor segment if it is determined that the main combined resistor segment needs to be further segmented.

[0016] In the above implementation process, when the area occupied by the thermometer code pattern structure is relatively large, the thermometer code pattern structure may be further segmented to further reduce the area occupied by the thermometer code pattern structure.

[0017] In a second aspect, an embodiment of the present application further provides a digital-to-analog converter structure, comprising: determined by the above-mentioned first aspect, or any one of the methods of the first aspect, the digital-to-analog converter structure comprises: a combined resistance segment; wherein the higher weight bits in the combined resistance segment adopt a thermometer code structure, and the lower weight bits in the combined resistance segment adopt a binary coding structure; the thermometer code structure comprises two thermometer code substructures, and the two thermometer code substructures are connected by a bridging resistor.

[0018] In the above implementation process, a digital-to-analog converter is set by adopting a combined resistor segmented resistor structure. Since the combined resistor segment combines the advantages of a thermometer structure and a binary coding structure, a compromise between area and accuracy can be achieved, thereby reducing the volume of the digital-to-analog converter while improving the accuracy of the digital-to-analog converter.

[0019] In one embodiment, a portion of the resistance pins in each region in the higher weight bit is connected to a voltage, and another portion of the resistance pins in each region is grounded; the digital-to-analog converter structure also includes: a PMOS transistor and an NMOS transistor; the gates of the PMOS transistor and the NMOS transistor are respectively connected to two R-2R digital-to-analog converter biases; a complementary transmission gate switch formed by the PMOS transistor and the NMOS transistor; the complementary transmission gate switch is connected to an on-resistance; the R-2R digital-to-analog converter bias is connected to the input of the resistance pin; wherein the R-2R digital-to-analog converter bias is configured to adjust the on-resistance, and the on-resistance configuration bit compensates for the nonlinear change of the corresponding resistance pin.

[0020] In the above implementation process, by designing a complementary transmission gate switch composed of a PMOS transistor and an NMOS transistor and connecting a conduction switch, the nonlinear change of the resistor pin is supplemented by the conduction switch, thereby reducing the nonlinear change of the digital-to-analog converter.

[0021] In one embodiment, the digital-to-analog converter structure is an 18-bit digital-to-analog converter structure; the combined resistor segment is a 10-bit-2-bit-6-bit segment structure; wherein the low-order 10 bits are an R-2R structure, and the middle-order 2 bits and the high-order 6 bits are both thermometer code structures.

[0022] In the above implementation process, for the 18-bit digital-to-analog converter structure, the combined resistor segment is designed to be a 10-bit-2-bit-6-bit segment structure, which can greatly reduce the area occupied by the combined resistor segment.

[0023] In one embodiment, it further includes: a calibration bit; the calibration bit is set on a side of the lower 10 bits away from the middle 2 bits; wherein the calibration bit is configured to reserve calibration space for the lower 10 bits.

[0024] In the above implementation process, by setting a calibration bit on the side of the lower weight bit away from the higher weight bit, calibration space can be reserved for the lower weight. When the lower weight bit needs to be calibrated, it can be calibrated through the calibration bit, thereby improving calibration flexibility.

[0025] In a third aspect, an embodiment of the present application further provides a device for determining the structure of a digital-to-analog converter, comprising: a building module: used to build a combined resistor segment when a resistor simulation result does not meet a preset condition; a first calibration module: used to perform a random mismatch calibration on the combined resistor segment through directional element matching; a simulation module: used to perform a resistor simulation on the combined resistor segment when the random mismatch calibration reaches a set calibration condition; a second calibration module: used to perform a resistor nonlinear calibration on the combined resistor segment when a simulation result of the resistor simulation does not meet the preset condition; a determination module: used to determine the structure of the digital-to-analog converter through the combined resistor segment with the resistor nonlinear calibration.

[0026] In a fourth aspect, an embodiment of the present application further provides an electronic device, comprising: a processor and a memory, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the machine-readable instructions are executed by the processor to perform the steps of the method in the above-mentioned first aspect, or any possible implementation of the first aspect.

[0027] In a fifth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for determining the structure of a digital-to-analog converter in the above-mentioned first aspect, or any possible implementation of the first aspect are executed.

[0028] In order to make the above-mentioned objects, features and advantages of the present application more obvious and understandable, embodiments are given below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 A block diagram of an electronic device provided in an embodiment of the present application;

[0031] Figure 2 A flowchart of a method for determining a digital-to-analog converter structure provided in an embodiment of the present application;

[0032] Figure 3 The I / V characteristics of a resistor with a nominal resistance of 110.8 kΩ at 300 K and 4 K respectively provided in the embodiment of the present application;

[0033] Figure 4A schematic diagram of simulation results of a Monte Carlo simulation of a resistor with a nominal resistance of 110.8 kΩ provided in an embodiment of the present application;

[0034] Figure 5 A schematic diagram of performing random mismatch calibration on a thermometer-type structure provided in an embodiment of the present application;

[0035] Figure 6 A schematic diagram of the main structure of an 18-bit DAC provided in an embodiment of the present application;

[0036] Figure 7 A schematic diagram of the structure of a digital-to-analog converter including a PMOS transistor and an NMOS transistor provided in an embodiment of the present application;

[0037] Figure 8 A schematic diagram showing how the resistance of PMOS and NMOS varies with HP<9:0> and HN<9:0> provided in an embodiment of the present application;

[0038] Fig. 9 A schematic diagram of the calibration of resistance nonlinearity provided in an embodiment of the present application;

[0039] Fig.10 A schematic diagram of linearity simulation results after OEM calibration and resistance nonlinearity calibration are performed on an 18-bit digital-to-analog converter provided in an embodiment of the present application;

[0040] Fig.11 A schematic diagram of the functional modules of the device for determining the structure of a digital-to-analog converter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0041] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application.

[0042] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0043] Quantum computing is expected to exponentially accelerate the solution of complex problems that are difficult for traditional computers to handle. This process may require the use of thousands or millions of qubits to solve useful problems. The quantum measurement and control system needs to generate high-precision, low-noise electrical signals to manipulate and read the state of qubits and control the interaction between qubits. Qubits need to be in an ultra-low temperature (<100mK) environment to be in a relatively stable state, while the traditional measurement and control system is located in a room temperature (300K) environment, and a large number of signal cables are connected to the qubit chip across the temperature zone to achieve the bias, drive and readout of the qubit. This traditional method cannot be expanded to the future million-qubit computer due to the large number of cables required. In recent years, quantum measurement and control systems are moving from room temperature to low temperature (generally 4K) environments, and are integrated with qubit chips in the near-temperature zone. Near-temperature integration greatly reduces the noise introduced by signal cables across temperature zones, and improves integration and reliability. Therefore, the development of low-temperature quantum measurement and control systems is expected to achieve large-scale expansion of quantum measurement and control arrays.

[0044] The cryogenic quantum measurement and control system consists of three parts: gate pulses, pulse generators, and reflection measurements. Among them, the gate pulse generates a DC pulse through digital control, which is used to set the potential of the quantum gate to control the initial state of a single quantum bit and the coupling state between different quantum bits. The pulse generator and reflection measurement are used for dynamic driving and readout of quantum bits. The core issue in the quantum measurement and control process is to improve the fidelity of the quantum gate, that is, to ensure the consistency of the quantum gate state before and after measurement and control. High-precision, low-noise gate pulses are the primary condition for realizing high-fidelity quantum gates. In addition, since the cooling power of the refrigerator is limited, the gate pulse needs to ensure low power consumption so that it can be used in the measurement and control system of large-scale quantum bit arrays.

[0045] A digital-to-analog converter is an electronic circuit that converts digital signals (such as binary signals) into analog signals (such as voltage, current, etc.). At present, there are three main forms of low-temperature DAC: capacitive DAC, current-steering DAC and resistive DAC.

[0046] Capacitive DAC realizes the digital-to-analog conversion process by charging and discharging capacitors, and has high energy efficiency and low power consumption. However, due to the existence of parasitic capacitance, there is a serious mismatch between capacitors, making it difficult to achieve high precision, and the shot noise and flicker noise of transistors at low temperatures will deteriorate the output noise of the capacitive DAC.

[0047] The current-steering DAC changes the size of the total output current by controlling the on-off of the current source to complete the data conversion process. Its main advantage is that it can drive the resistive load without a buffer and the signal conversion speed is very fast, but the use of a large number of current sources leads to high power consumption. In addition, the thermal noise of the transistors in the current-steering DAC is reduced by 2 to 3 times at low temperatures (compared to room temperature 300K), but the flicker noise is deteriorated by about 10 times, resulting in a deterioration of the overall output noise.

[0048] Resistive DAC achieves digital-to-analog conversion through resistor voltage division, and its output noise is mainly determined by the thermal noise of the resistor, which decreases approximately linearly with decreasing temperature, so the resistive DAC has excellent noise performance at low temperatures. Most high-precision DACs rely on precise resistor arrays to complete data conversion, so their accuracy is very sensitive to the matching degree of the resistor network.

[0049] At present, the room temperature resistor DAC can achieve extremely high accuracy. For example, the 20-bit R-2R DAC realized by ADI (Analog Device Inc.) has an ultra-high accuracy of 19μV and an output noise spectral density of only However, at low temperatures, the accuracy that can be achieved by resistive DACs is greatly reduced. The R-2RDAC used by MIT to control captured particles has a resolution of only 12 bits, and due to the introduction of an amplifier at the output end, the output noise of the DAC is greatly increased.

[0050] In view of this, the present application proposes a method for determining the structure of a digital-to-analog converter, by using a combined resistor segmented resistor structure to set the digital-to-analog converter, because the combined resistor segmentation combines the advantages of the thermometer type structure and the binary coding type structure, it can achieve a compromise between area and accuracy, while reducing the volume of the digital-to-analog converter, while improving the accuracy of the digital-to-analog converter. In addition, by using the directional element matching technology to calibrate the random mismatch of the resistor, because the directional element matching technology only needs to change the decoding method of the thermometer code segment, the calibration cost is very low, which can reduce the cost of determining the structure of the digital-to-analog converter.

[0051] To facilitate understanding of this embodiment, first, an electronic device that executes the method for determining the structure of a digital-to-analog converter disclosed in the embodiment of the present application is introduced in detail.

[0052] like Figure 1 , which is a block diagram of an electronic device. The electronic device 100 may include a memory 111 and a processor 113. A person skilled in the art may understand that Figure 1 The structure shown is only for illustration and does not limit the structure of the electronic device 100. For example, the electronic device 100 may further include Figure 1 More or fewer components as shown, or with Figure 1Different configurations shown.

[0053] The memory 111 and the processor 113 are directly or indirectly electrically connected to each other to achieve data transmission or interaction. For example, these elements can be electrically connected to each other via one or more communication buses or signal lines. The processor 113 is used to execute the executable module stored in the memory.

[0054] The memory 111 may be, but not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), etc. The memory 111 is used to store programs, and the processor 113 executes the program after receiving the execution instruction. The method executed by the electronic device 100 defined by the process disclosed in any embodiment of the present application can be applied to the processor 113, or implemented by the processor 113.

[0055] The processor 113 may be an integrated circuit chip with signal processing capability. The processor 113 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0056] The electronic device 100 in this embodiment can be used to execute each step in each method provided in the embodiments of the present application. The implementation process of the method for determining the structure of a digital-to-analog converter is described in detail below through several embodiments.

[0057] See also Figure 2 , is a flow chart of a method for determining a digital-to-analog converter structure provided by an embodiment of the present application. Figure 2 The specific process shown is described in detail.

[0058] Step 201: when the resistance simulation result does not meet the preset conditions, construct a combined resistance segment.

[0059] Optionally, a Monte Carlo simulation can be used to simulate the resistor. Monte Carlo simulation is a method of simulating a complex system or process by random sampling and estimating the system behavior or characteristics based on these simulation results. It uses a random number (or pseudo-random number) generator to simulate various possible system states or results, and evaluates the probability distribution of system performance or risk based on a large number of simulation results.

[0060] The resistor simulation results here include random mismatches in resistors.

[0061] In one embodiment, before step 201, the method further includes: testing the I / V characteristics of the resistor at 300K and 4K to understand the nonlinear change of the resistor at low temperature.

[0062] For example, Figure 3 As shown, Figure 3 The I / V characteristics of a resistor with a nominal resistance of 110.8kΩ at 300K and 4K are shown in the figure. The specific test structure is: at 300K, the average resistance of the resistor is 112.2kΩ, and the voltage nonlinearity is about 15.5Ω / V; at 4K, the average resistance of the resistor rises to 121.6kΩ (about 12.4% increase), and the voltage nonlinearity is 664Ω / V (about 43 times worse).

[0063] Continuing with the example of a resistor with a nominal resistance of 110.8 kΩ, the Monte Carlo simulation results of this resistor are as follows: Figure 4 As shown, the random mismatch (ie, standard deviation) of the resistors is 134Ω.

[0064] It should be understood that after obtaining the random mismatch and nonlinearity of the resistor, the Verilog-A language can be used to model the resistor at low temperature.

[0065] In this case, considering that the resistance mismatch is aggravated at low temperature, the resistance mismatch is configured as three times the standard deviation. For example, the resistance mismatch of a resistor with a resistance value of 110.8 kΩ is 402 Ω.

[0066] The preset condition here refers to the simulation result range corresponding to each resistance value set in advance. The preset condition can be determined by multiple experiments or by setting a calculation formula. The method for determining the preset condition can be selected according to the actual situation.

[0067] The above-mentioned combined resistance segmentation refers to a resistance structure that uses a binary coding structure at a lower weight bit and a thermometer structure at a higher weight bit. That is, the combined resistance segmentation includes: a higher weight bit and a lower weight bit.

[0068] Among them, the thermometer type structure has good monotonicity, but occupies a large area. The binary coding type structure has the advantage of saving area, but the monotonicity is average. The combined resistor segment combines the advantages of the thermometer type structure and the binary coding type structure to achieve a compromise between area and accuracy.

[0069] Step 202 , performing random mismatch calibration on the combined resistor segments by directional element matching.

[0070] The directional element matching here refers to a method of complementary matching of the resistor pins of each segment so that the matched resistance value is close to the average resistance value of the segment resistor.

[0071] It should be understood that during random mismatch calibration of combined resistor segments, the relative size of each thermometer-type structure resistor pin can be obtained by connecting the resistor pin to a power source and the other resistor pins to ground, and then measuring the output voltage of the digital-to-analog converter.

[0072] Among them, the larger the output voltage is, the smaller the resistance value of the resistor pin is.

[0073] Step 203 : When the random mismatch calibration reaches the set calibration condition, resistance simulation is performed on the combined resistance segment.

[0074] Optionally, the calibration condition may be that each segment of the combined resistor segment reaches complete folding, or that the output voltage of the digital-to-analog converter reaches a set voltage, etc. The calibration condition may be adjusted according to actual conditions.

[0075] The resistance simulation here may adopt the same simulation method as step 201 , or may adopt a simulation method different from step 201 . The simulation method of the resistance simulation may be selected according to actual conditions.

[0076] Step 204: When the simulation result of the resistance simulation does not meet the preset condition, the resistance nonlinearity calibration is performed on the combined resistance segment.

[0077] In one embodiment, a portion of the resistor pins in each region in the higher weight bit is connected to a voltage, and another portion of the resistor pins in each region is grounded; the resistor pins are connected to a PMOS transistor and an NMOS transistor, and the gates of the PMOS transistor and the NMOS transistor are respectively connected to two R-2R digital-to-analog converter biases; the PMOS transistor and the NMOS transistor constitute a complementary transmission gate switch.

[0078] Here the on-resistance is connected to the complementary transmission gate switch.

[0079] The on-resistance of the transmission gate switch can be adjusted by controlling the output voltage of two bias digital-to-analog converters, thereby compensating for the nonlinear change of the resistor pin.

[0080] The above-mentioned resistor nonlinearity calibration configuration is used to improve the accuracy of the digital-to-analog converter.

[0081] Step 205, determining the structure of the digital-to-analog converter by means of the combined resistor segmentation of the resistor nonlinearity calibration.

[0082] The combined resistor segment after the resistor nonlinearity calibration is the resistor structure of the digital-to-analog converter.

[0083] In the above implementation process, the digital-to-analog converter is set by adopting a combined resistor segmented resistor structure. Since the combined resistor segment combines the advantages of the thermometer structure and the binary coding structure, a compromise between area and accuracy can be achieved, and the accuracy of the digital-to-analog converter can be improved while reducing the volume of the digital-to-analog converter. In addition, the random mismatch of the resistor is calibrated by adopting the directional element matching technology. Since the directional element matching technology only needs to change the decoding method of the thermometer code segment, the calibration cost is very low, which can reduce the cost of determining the structure of the digital-to-analog converter.

[0084] In one possible implementation, step 202 includes: sorting all the resistor pins of the thermometer-type structure in the higher weight position according to the resistance value; pairing two symmetrically distributed resistor pins among the resistor pins after the resistance value sorting to obtain a folded higher weight position; repeating from sorting all the resistor pins of the thermometer-type structure in the folded higher weight position according to the resistance value until the iteration termination condition is reached to obtain a completely folded higher weight position.

[0085] The combined resistor segment here includes one or more thermometer-type structures. When performing random mismatch calibration on the combined resistor segment, random mismatch calibration can be performed on each thermometer-type structure respectively.

[0086] Among them, when performing random mismatch calibration on each thermometer-type structure, the resistor pins of the thermometer-type structure are sorted according to the resistance value; two symmetrically distributed resistor pins among the resistor pins after the resistance value sorting are paired to obtain a folded higher weight position; and the process is repeated starting from sorting the resistor pins of all thermometer-type structures in the folded higher weight position according to the resistance value until the iteration termination condition is reached to obtain a completely folded higher weight position.

[0087] For example, if the combined resistor segment includes the H<62:0> segment and the M<2:0> segment thermometer structure. The H<62:0> segment includes 63 thermometer code resistor pins, and the M<2:0> segment includes 3 thermometer code resistor pins. When performing random mismatch calibration, first sort the 63 thermometer code resistor pins of the H<62:0> segment according to their resistance values, and then select the resistor pin with the resistance value closest to the average value Ravg (such as Figure 5 The 63-bit thermometer code is then converted into a 1-bit binary code and a 31-bit thermometer code, completing a "folding". The resistance values ​​of the folded thermometer code resistor pins are all close to 2Ravg. Continue to fold the 31-bit thermometer code further according to the above steps until the 63-bit thermometer code is completely converted into a 6-bit binary code, achieving complete folding of the H<62:0> segment.

[0088] In the same way, the 3-bit thermometer code of the M<2:0> segment is completely converted into a 2-bit binary code.

[0089] Among them, the higher weight bits are fully folded in a binary pattern structure.

[0090] In the above implementation process, the resistor pins of the thermometer type structure are completely folded, which can greatly reduce the random mismatch error between the resistor pins of the thermometer type structure and improve the random mismatch accuracy.

[0091] In a possible implementation, the method further includes: constructing a calibration bit; and setting the calibration bit on a side of the lower weight bit away from the higher weight bit.

[0092] Among them, the calibration bit is configured to reserve calibration space with lower weight.

[0093] It can be understood that since the lower weight bit has a smaller weight in the combined resistor segment, its nonlinearity also contributes little to the nonlinearity of the overall digital-to-analog converter. Therefore, it is usually unnecessary to calibrate the lower weight bit.

[0094] However, in some special cases, for example, when the accuracy and sensitivity of the digital-to-analog converter are more stringent, the lower weight bit needs to be calibrated. By setting the calibration bit on one side of the lower weight bit, calibration space can be reserved for the lower weight bit, so that calibration can be performed when the lower weight bit needs to be calibrated.

[0095] For example, if the main structure of the 18-bit DAC is as follows Figure 6As shown, it includes: a B<9:0> segment of a lower weight bit, an M<2:0> segment of a higher weight bit, and an H<62:0> segment. Among them, the B<9:0> segment of the lower weight bit is provided with a plurality of calibration bit L<2:0> segments on one side of the higher weight bit ( Figure 6 3 are shown).

[0096] In the above implementation process, by setting a calibration bit on the side of the lower weight bit away from the higher weight bit, calibration space can be reserved for the lower weight. When the lower weight bit needs to be calibrated, it can be calibrated through the calibration bit, thereby improving calibration flexibility.

[0097] In a possible implementation, step 204 includes: determining the on-resistance to be adjusted according to the relationship between the output voltage of the combined resistor segment and the preset voltage; and adjusting the on-resistance by controlling the bias of the R-2R digital-to-analog converter.

[0098] The preset voltage here may be the theoretical output voltage of the combined resistor segment.

[0099] In one embodiment, if the output voltage reaches the preset voltage, it means that the nonlinear calibration is in place, and the corresponding on-resistance does not need to be adjusted. If the output voltage does not reach the preset voltage, it means that the nonlinear calibration is not in place, and the corresponding on-resistance needs to be adjusted.

[0100] When adjustment is required, the complementary transmission gate switch is turned off, and when adjustment is not required, the complementary transmission gate switch is turned on.

[0101] The on-resistance configuration bit here compensates for the nonlinear variation of the corresponding resistor pin, so that the nonlinear variation of the sum of the switch resistance and the resistance value of the resistor pin within the output voltage range of the digital-to-analog converter is reduced.

[0102] In the above implementation process, by determining the on-resistance that needs to be adjusted based on the relationship between the output voltage and the preset voltage, and adjusting the on-resistance by controlling the bias of the digital-to-analog converter, the nonlinear change of the corresponding resistor pin can be compensated, so that the nonlinear change of the sum of the switch resistance and the resistance pin within the output voltage range of the digital-to-analog converter is reduced, thereby improving the nonlinear calibration capability.

[0103] In a possible implementation, step 201 includes: constructing a plurality of combined resistance segments according to the digital-to-analog converters; and determining a main combined resistance segment according to the accuracy of the binary coded structure in each combined resistance segment.

[0104] The higher weighted bits in each combined resistor segment adopt a thermometer code structure, and the lower weighted bits in each combined resistor segment adopt a binary code structure.

[0105] The accuracy of the binary coded structures in the above-mentioned various combinational resistor segments may vary.

[0106] The main combined resistor segment here can be a combined resistor segment whose accuracy meets the accuracy requirements of the digital-to-analog converter. For example, the binary coded structures in the combined resistor segment include: 16, 14, 12, 10, 8, 6, 4, 2, etc. Among them, the accuracy of the binary coded structure greater than or equal to 10 meets the accuracy requirements of the digital-to-analog converter, and the combined resistor segment where the binary coded structure of 16, 14, 12, 10 is located can be determined as the main combined resistor segment.

[0107] For example, if the DAC is an 18-bit DAC, then 16-2, 14-4, 12-6, 10-8, etc. segmented combined resistor segments can be constructed, wherein the lower weight bits use an R-2R structure, and the higher weight bits use a thermometer code structure.

[0108] Among them, the linearity simulation results of the digital-to-analog converters with different segment structures can be shown in Table 1.

[0109] Table 1:

[0110]

[0111] As can be seen from Table 1, the more bits the thermometer code structure has, the higher the accuracy of the DAC, but at the same time the required area is larger. A 12-6 segment structure requires 63 thermometer codes, and a 10-8 segment structure requires 255 thermometer codes, and the required area increases exponentially.

[0112] The above-mentioned main body combined type resistor segment configuration is used to construct a digital-to-analog converter.

[0113] In one embodiment, step 202 includes: performing random mismatch calibration on the main body composite resistor segment by directional element matching.

[0114] It should be understood that since the main body combined resistance segment is a combined resistance segment that meets the accuracy requirements of the digital-to-analog converter, when constructing a digital-to-analog converter, the main body combined resistance segment is usually used for configuration. Therefore, when performing random mismatch calibration, only the main body combined resistance segment can be calibrated.

[0115] In the above implementation process, by selecting the main body combined resistor segment according to the accuracy and then constructing the digital-to-analog converter, the main body combined resistor segment that meets the accuracy requirement of the digital-to-analog converter can be determined to improve the accuracy of the digital-to-analog converter.

[0116] In a possible implementation, before step 202, the method further includes: judging whether the main body combination type resistor segment needs to be further segmented according to the occupied area of ​​the thermometer code structure of the main body combination type resistor segment; and further segmenting the thermometer code structure of the main body combination type resistor segment if it is determined that the main body combination type resistor segment needs to be further segmented.

[0117] In one embodiment, when the occupied area of ​​the thermometer code structure of the main body combined type resistor segment is larger than a preset area, it is determined that further segmentation is required.

[0118] The preset area here refers to the optimal occupied area of ​​the set resistor, or may be the maximum occupied area of ​​the set resistor. The preset area may be selected according to actual conditions.

[0119] The further segmentation mentioned above means that the thermometer code structure is further segmented, and the thermometer code structure is divided into a plurality of segments, for example, the thermometer code structure is further divided into 2 segments, the thermometer code structure is further divided into 3 segments, and so on.

[0120] Exemplarily, in order to reduce the area occupied by the thermometer code structure, the thermometer code structure is further divided into two segments: that is, the 8-bit thermometer code structure in the 10-8 segment structure can also be further divided into two segments of 2-6, which are connected in the middle with a bridge resistor. In this way, originally 255 thermometer codes are required, but after further segmentation, only 3+63=66 thermometer codes are needed, which greatly reduces the occupied area.

[0121] In the above implementation process, when the area occupied by the thermometer code pattern structure is relatively large, the thermometer code pattern structure may be further segmented to further reduce the area occupied by the thermometer code pattern structure.

[0122] See also Figure 6 , is a digital-to-analog converter structure provided in an embodiment of the present application, and the digital-to-analog converter structure is determined by the method in the above embodiment.

[0123] In one embodiment, the digital-to-analog converter structure includes: a combined resistance segment.

[0124] The higher weight bits in the combined resistor segment adopt a thermometer code structure, and the lower weight bits in the combined resistor segment adopt a binary coding structure. The combined resistor segment combines the advantages of the thermometer structure and the binary coding structure to achieve a compromise between area and accuracy.

[0125] The higher weighted bits here have a portion of the resistor pins in each region connected to voltage and another portion of the resistor pins in each region connected to ground.

[0126] Optionally, the thermometer code pattern structure includes two thermometer code pattern substructures, and the two thermometer code pattern substructures are connected via a bridge resistor.

[0127] In the above implementation process, a digital-to-analog converter is set by adopting a combined resistor segmented resistor structure. Since the combined resistor segment combines the advantages of a thermometer structure and a binary coding structure, a compromise between area and accuracy can be achieved, thereby reducing the volume of the digital-to-analog converter while improving the accuracy of the digital-to-analog converter.

[0128] In one possible implementation, Figure 7 As shown, the digital-to-analog converter structure further includes: a PMOS transistor and an NMOS transistor.

[0129] Among them, the gates of the PMOS transistor and the NMOS transistor are respectively connected to two R-2R digital-to-analog converter biases; the PMOS transistor and the NMOS transistor constitute a complementary transmission gate switch; the complementary transmission gate switch is connected to the on-resistance; and the R-2R digital-to-analog converter bias is connected to the input of the resistor pin.

[0130] In one embodiment, the PMOS transistor is a W / L=8 μm / 60 nm PMOS transistor, and the NMOS transistor is a W / L=4 μm / 60 nm NMOS transistor.

[0131] The gates of the PMOS and NMOS include two 10-bit R-2R digital-to-analog converter biases respectively.

[0132] Here, the R-2R DAC bias is configured to adjust the on-resistance, and the on-resistance is configured to compensate for the nonlinear variation of the corresponding resistor pin.

[0133] For example, if the DAC is an 8-bit DAC, the entire output range of the 8-bit DAC can be divided into 64 equally spaced regions by H<62:0>, and in each region, i (i=0, 1, ..., 63) resistor pins are connected to the analog voltage, and (63-i) resistor pins are connected to the ground. By controlling the output voltage of the two 10-bit bias DACs, the on-resistance of the transmission gate switch can be adjusted, thereby compensating for the nonlinear change of the resistor pin, so that the nonlinear change of the sum of the switch resistance and the resistance value of the resistor pin within the output voltage range of the DAC is reduced.

[0134] like Figure 8 As shown, Figure 8 The resistance of PMOS and NMOS is shown as a function of HP<9:0> and HN<9:0>: The adjustable range of transistor resistance exceeds Figure 3 The nonlinear resistance variation range shown can compensate and calibrate the nonlinear resistance variation at 4K.

[0135] The calibration of the resistor nonlinearity is as follows: Fig. 9 As shown: With resistor pin H <0> For example, the sum of the resistance of the resistor pin and the switch resistance is RH <0> , the red line is the RH without calibration <0> The black line is the ideal situation without considering the nonlinearity of resistance, and the green line is the RH after nonlinear calibration of 64 regions. <0> It can be seen that the amplitude of nonlinear changes is greatly reduced after calibration, that is, the calibration is effective. In addition, the amplitude of the green line is slightly larger in the front part because the resistance of the transistor changes exponentially with the gate voltage.

[0136] Similarly, the same transmission gate switch can be added after the thermometer-type structure resistor pin of the M<2:0> segment, and the switch resistance is adjusted by two additional 10-bit R-2R digital-to-analog converters (corresponding to MP<9:0> and MN<9:0>). In this way, each of the 64 regions can be further divided into four equally spaced sub-regions, which can further reduce the residual nonlinear changes in each region. In addition, the resistance nonlinear changes of the B<9:0> segment can be compensated and calibrated by the fine calibration bit L<2:0>.

[0137] For example, Fig.10 As shown, Fig.10 The linearity simulation results of the 18-bit DAC after OEM calibration and resistor nonlinearity calibration are shown. That is, the INL is less than 1LSB after calibrating the resistor mismatch and nonlinearity, which can meet the high-precision design requirements.

[0138] In the above implementation process, by designing a complementary transmission gate switch composed of a PMOS transistor and an NMOS transistor and connecting a conduction switch, the nonlinear change of the resistor pin is supplemented by the conduction switch, thereby reducing the nonlinear change of the digital-to-analog converter.

[0139] In a possible implementation, the digital-to-analog converter structure is an 18-bit digital-to-analog converter structure.

[0140] Among them, the combined resistor segmentation is a 10bit-2bit-6bit segmentation structure.

[0141] The low-order 10 bits here are of R-2R structure, and the middle 2 bits and high-order 6 bits are of thermometer code structure.

[0142] It can be understood that if the digital-to-analog converter is an 18-bit structure, the combined resistor segmentation can be 16-2, 14-4, 12-6, and 10-8. Among them, the 16-2 segmentation requires 3 thermometer codes, the 14-4 segmentation requires 15 thermometer codes, the 12-6 segmentation requires 63 thermometer codes, and the 10-8 segmentation requires 255 thermometer codes. It can be seen that the area of ​​the 10-8 segment is too large compared to the area of ​​the 12-6 segment. In this case, the 10-8 segment can be further segmented to obtain 2 2-6 segments, and the structure after further segmentation only requires 3+63=66 thermometer codes. The structure that originally required 255 thermometer codes is reduced to only 66 thermometer codes, achieving a significant reduction in area.

[0143] In the above implementation process, for the 18-bit digital-to-analog converter structure, the combined resistor segment is designed to be a 10-bit-2-bit-6-bit segment structure, which can greatly reduce the area occupied by the combined resistor segment.

[0144] In a possible implementation manner, the digital-to-analog converter further includes: a calibration bit.

[0145] The calibration bit is set at the side of the low 10 bits away from the middle 2 bits.

[0146] The calibration bit configuration here reserves the lower 10 bits of calibration space.

[0147] Optionally, the calibration bit may include one or more, and the number of the calibration bits may be selected according to actual conditions.

[0148] For example, Figure 6 As shown, the calibration bit is divided into three L<2:0> segments.

[0149] In the above implementation process, by setting a calibration bit on the side of the lower weight bit away from the higher weight bit, calibration space can be reserved for the lower weight. When the lower weight bit needs to be calibrated, it can be calibrated through the calibration bit, thereby improving calibration flexibility.

[0150] Based on the same application concept, the embodiment of the present application also provides a digital-to-analog converter structure determination device corresponding to the digital-to-analog converter structure determination method. Since the principle of solving the problem by the device in the embodiment of the present application is similar to that of the aforementioned digital-to-analog converter structure determination method embodiment, the implementation of the device in this embodiment can refer to the description in the embodiment of the above-mentioned method, and the repeated parts will not be repeated.

[0151] See also Fig.11, is a functional module diagram of a digital-to-analog converter structure determination device provided in an embodiment of the present application. Each module in the digital-to-analog converter structure determination device in this embodiment is used to execute each step in the above method embodiment. The digital-to-analog converter structure determination device includes a construction module 301, a first calibration module 302, a simulation module 303, a second calibration module 304, and a determination module 305; wherein,

[0152] The building module 301 is used to build a combined resistance segment when the resistance simulation result does not meet the preset conditions.

[0153] The first calibration module 302 is used to perform random mismatch calibration on the combined resistor segments by directional element matching.

[0154] The simulation module 303 is used to perform resistance simulation on the combined resistance segment when the random mismatch calibration reaches the set calibration condition.

[0155] The second calibration module 304 is used to perform resistance nonlinearity calibration on the combined resistor segment when the simulation result of the resistance simulation does not meet the preset condition.

[0156] The determination module 305 is used to determine the structure of the digital-to-analog converter by means of the combined resistor segmentation of the resistor nonlinearity calibration.

[0157] In one possible implementation, the first calibration module 302 is further used to: sort all the resistance pins of the thermometer-type structure in the higher weight position according to the resistance value; pair two symmetrically distributed resistance pins among the resistance pins after the resistance value sorting to obtain a folded higher weight position; repeat starting from sorting all the resistance pins of the thermometer-type structure in the folded higher weight position according to the resistance value until the iteration termination condition is reached to obtain a completely folded higher weight position; wherein the completely folded higher weight position is a binary code structure.

[0158] In a possible implementation, the digital-to-analog converter structure determination device further includes a setting module for constructing a calibration bit; setting the calibration bit on a side of the lower weight bit away from the higher weight bit; wherein the calibration bit is configured to reserve calibration space for the lower weight.

[0159] In one possible implementation, the second calibration module 304 is specifically used to: determine the on-resistance that needs to be adjusted based on the relationship between the output voltage of the combined resistor segment and the preset voltage; wherein the on-resistance is connected to the complementary transmission gate switch; and adjust the on-resistance by controlling the bias of the R-2R digital-to-analog converter; wherein the on-resistance configuration bit compensates for the nonlinear change of the corresponding resistor pin.

[0160] In a possible implementation, the building module 301 is specifically used to: build a plurality of combined resistance segments according to the digital-to-analog converters; wherein the higher weighted bits in each of the combined resistance segments adopt a thermometer code structure, and the lower weighted bits in each of the combined resistance segments adopt a binary coding structure; determine the main combined resistance segments according to the accuracy of the binary coding structure in each combined resistance segment; the main combined resistance segments are configured to construct the digital-to-analog converter;

[0161] In a possible implementation manner, the first calibration module 302 is specifically configured to perform random mismatch calibration on the main combined resistor segment by directional element matching.

[0162] In a possible implementation, the digital-to-analog converter structure determination device further includes a segmentation module, which is used to determine whether the main body combination type resistor segment needs to be further segmented based on the occupied area of ​​the thermometer code structure of the main body combination type resistor segment; if it is determined that the main body combination type resistor segment needs to be further segmented, the thermometer code structure of the main body combination type resistor segment is further segmented.

[0163] In addition, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method for determining the structure of a digital-to-analog converter described in the above method embodiment are executed.

[0164] The computer program product of the method for determining the structure of a digital-to-analog converter provided in the embodiment of the present application includes a computer-readable storage medium storing program code, and the instructions included in the program code can be used to execute the steps of the method for determining the structure of a digital-to-analog converter described in the above method embodiment. For details, please refer to the above method embodiment, which will not be repeated here.

[0165] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0166] In addition, the functional modules in the various embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.

[0167] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk. It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variation thereof are intended to cover non-exclusive inclusion, so that a process, method, article or apparatus that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or apparatus. In the absence of more restrictions, the elements defined by the sentence "includes..." do not exclude the presence of other identical elements in the process, method, article or apparatus that includes the elements.

[0168] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application. It should be noted that similar numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0169] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for determining a digital-to-analog converter structure, characterized in that: include: When the resistance simulation results do not meet the preset conditions, build a combined resistance segment; performing random mismatch calibration on the combined resistor segments by directional element matching; When the random mismatch calibration reaches the set calibration condition, performing resistance simulation on the combined resistance segment; When the simulation result of the resistance simulation does not meet the preset condition, performing resistance nonlinearity calibration on the combined resistance segment; The structure of the digital-to-analog converter is determined by combining resistor segments for resistor nonlinearity calibration.

2. The method according to claim 1, characterized in that in, The combined resistance segment includes: a higher weight bit and a lower weight bit; The random mismatch calibration of the combined resistor segments by directional element matching includes: Sort the resistor pins of all the thermometer-type structures in the higher weighted position by resistance value; Pair two symmetrically distributed resistor pins among the resistor pins sorted by resistance value to obtain a folded higher weighted bit; Repeating from sorting the resistor pins of all thermometer-type structures in the folded higher weighted bits according to the resistance value until the iteration termination condition is reached, thereby obtaining a completely folded higher weighted bit; Among them, the higher weight bits are fully folded in a binary pattern structure.

3. The method according to claim 2, characterized in that The method further comprises: Construct calibration bits; Setting the calibration bit on a side of the lower weight bit away from the higher weight bit; The calibration bit is configured to reserve the calibration space with the lower weight.

4. The method according to claim 2, characterized in that: in, A portion of the resistor pins in each region of the higher weighted bit is connected to a voltage, and another portion of the resistor pins in each region is grounded; the resistor pins are connected to a PMOS transistor and an NMOS transistor, and the gates of the PMOS transistor and the NMOS transistor are respectively connected to two R-2R digital-to-analog converter biases; the PMOS transistor and the NMOS transistor constitute a complementary transmission gate switch; The step of performing resistance nonlinearity calibration on the combined resistance segment comprises: Determine the on-resistance that needs to be adjusted according to the relationship between the output voltage of the combined resistance segment and the preset voltage; wherein the on-resistance is connected to the complementary transmission gate switch; Adjusting the on-resistance by controlling the bias of the R-2R digital-to-analog converter; The on-resistance configuration bit compensates for nonlinear changes of the corresponding resistance pin.

5. The method according to any one of claims 1 to 4, characterized in that: When the resistance simulation result does not meet the preset conditions, building a combined resistance segmentation includes: A plurality of combined resistance segments are constructed according to the digital-to-analog converters; wherein the higher weighted bits in each of the combined resistance segments adopt a thermometer code structure, and the lower weighted bits in each of the combined resistance segments adopt a binary code structure; Determining a main body of combined resistor segments according to the accuracy of the binary coded structure in each combined resistor segment; the main body of combined resistor segments is configured to construct the digital-to-analog converter; The random mismatch calibration of the combined resistor segments by directional element matching includes: The random mismatch calibration is performed on the main body combined resistor segment through directional element matching.

6. The method according to claim 5, characterized in that Before performing random mismatch calibration on the combined resistor segments by directional element matching, the method further includes: Determining whether the main body combined type resistor segment needs to be further segmented according to the occupied area of ​​the thermometer code structure of the main body combined type resistor segment; In the case where it is determined that the main body combined type resistor segment needs to be further segmented, the thermometer code structure of the main body combined type resistor segment is further segmented.

7. A digital-to-analog converter structure, characterized in that: Determined by any one of the methods of claims 1-6, the digital-to-analog converter structure comprises: a combined resistor segment; Wherein, the higher weighted bits in the combined resistance segment adopt a thermometer code structure, and the lower weighted bits in the combined resistance segment adopt a binary code structure; The thermometer code pattern structure includes two thermometer code pattern substructures, and the two thermometer code pattern substructures are connected via a bridge resistor.

8. The digital-to-analog converter structure according to claim 7, characterized in that: A portion of the resistor pins in each region of the higher weighted bit is connected to a voltage, and another portion of the resistor pins in each region is grounded; The digital-to-analog converter structure also includes: a PMOS transistor and an NMOS transistor; The gates of the PMOS transistor and the NMOS transistor are respectively connected to two R-2R digital-to-analog converter biases; the PMOS transistor and the NMOS transistor constitute a complementary transmission gate switch; The complementary transmission gate switch is connected to an on-resistance; The R-2R digital-to-analog converter bias is connected to the input of the resistor pin; Wherein, the R-2R digital-to-analog converter bias configuration is to adjust the on-resistance, and the on-resistance configuration bit compensates for the nonlinear change of the corresponding resistance pin.

9. The digital-to-analog converter structure according to claim 7, characterized in that: The digital-to-analog converter structure is an 18-bit digital-to-analog converter structure; The combined resistor segmentation is a 10bit-2bit-6bit segmentation structure; Among them, the low-order 10 bits are of R-2R structure, and the middle 2 bits and high-order 6 bits are of thermometer code structure.

10. The digital-to-analog converter structure according to claim 9, characterized in that: Also includes: Calibration bit; The calibration bit is set on the side of the low 10 bits away from the middle 2 bits; The calibration bit is configured to reserve the calibration space of the lower 10 bits.

Images