Industrial Ethernet data transmission method and system

Abstract

The invention discloses an industrial Ethernet data transmission method and system, and belongs to the field of industrial communication. The method comprises the following steps: a first element acquires a first data frame, wherein the first data frame is an Ethernet data frame to be processed; the first element determines information of a data description area in a memory based on the length information of the first data frame; the information of the data description area comprises the number of data cache segments occupied by the first data frame in a data cache area in the memory; the first element stores the first data frame into a first number of data cache segments in the data cache region; the first number is equal to the number of data cache segments occupied by the first data frame; and a second element executes a data reading operation from the data cache region in the memory.

Description

Technical Field

[0001] The present application belongs to the field of industrial communications, and specifically relates to a method and system for transmitting industrial Ethernet data. Background Art

[0002] In the industrial field, Ethernet has been widely used due to its versatility, high-efficiency and security of transmission, and long transmission distance. In order to ensure the reliability of Ethernet data, redundant communication methods have been widely used, which also increases the demand for the number of network interfaces. Therefore, network interfaces are usually expanded through field programmable gate arrays (FPGAs), and data transmission between FPGAs and processors is used to achieve data transmission on multiple Ethernet interfaces.

[0003] When implementing data frame transmission between FPGA and processor, related technology usually dynamically allocates a storage space of corresponding length according to the length of the data frame. However, the length of the data frame is uncertain, which easily leads to waste of storage space. This method has the problem of low utilization of storage space. Summary of the invention

[0004] The embodiments of the present application provide a method and system for transmitting industrial Ethernet data, which can solve the problem of low utilization of storage space in related technologies.

[0005] In a first aspect, an embodiment of the present application provides a method for transmitting industrial Ethernet data, including: The first component obtains a first data frame, where the first data frame is an Ethernet data frame to be processed; The first component determines information of a data description area in a memory based on the length information of the first data frame; the information of the data description area includes the number of data cache segments occupied by the first data frame in a data cache area in the memory; The first component stores the first data frame in a first number of data cache segments in the data cache area; the first number is equal to the number of data cache segments occupied by the first data frame; A second component performs a data read operation from the data buffer area in the memory; Among them, the data description area includes multiple data description segments, the data cache area includes multiple data cache segments, the number of the multiple data description segments is the same as the number of the multiple data cache segments; each of the multiple data description segments corresponds to a data cache segment and includes storage description information associated with the data cache segment.

[0006] In a second aspect, an embodiment of the present application further provides an industrial Ethernet data transmission system, comprising: a first component and a second component; The first component is used to obtain a first data frame, where the first data frame is an Ethernet data frame to be processed; based on the length information of the first data frame, determine the information of the data description area in the memory; the information of the data description area includes the number of data cache segments occupied by the first data frame in the data cache area in the memory; store the first data frame in a first number of data cache segments in the data cache area; the first number is equal to the number of data cache segments occupied by the first data frame; The second element is used to perform a data read operation from the data buffer area in the memory; Among them, the data description area includes multiple data description segments, the data cache area includes multiple data cache segments, the number of the multiple data description segments is the same as the number of the multiple data cache segments; each of the multiple data description segments corresponds to a data cache segment and includes storage description information associated with the data cache segment; the first element is one of the CPU and the FPGA, and the second element is the other of the CPU and the FPGA.

[0007] At least one of the above technical solutions provided in the embodiments of the present application can achieve the following technical effects: In an embodiment of the present application, a first component obtains a first data frame, which is an Ethernet data frame to be processed; the first component determines information of a data description area in a memory based on length information of the first data frame; the information of the data description area includes the number of data cache segments occupied by the first data frame in a data cache area in the memory; the first component stores the first data frame in a first number of data cache segments in the data cache area; the first number is equal to the number of data cache segments occupied by the first data frame; the second component performs a data read operation from the data cache area in the memory; wherein the data description area includes multiple data description segments, the data cache area includes multiple data cache segments, and the number of the multiple data description segments is the same as the number of the multiple data cache segments; each of the multiple data description segments corresponds to a data cache segment and includes storage description information associated with the data cache segment. In this way, the data cache area in the memory includes multiple data cache segments. For the first data frame to be processed obtained by the first component, the first number of data cache segments occupied by the first data frame is determined based on the length information of the first data frame, and according to the first number of data cache segments occupied by the first data frame, the first data frame is stored in the first number of data cache segments in the data cache area in the memory. This method makes full use of the storage space of the memory and solves the problem of low storage space utilization in related technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0009] Figure 1 It is a flow chart of a method for transmitting industrial Ethernet data provided by an embodiment of the present application; Figure 2 is a schematic diagram of storage information of a memory provided in an embodiment of the present application; Figure 3 It is a general concept diagram of an industrial Ethernet data transmission method provided by an embodiment of the present application; Figure 4 is a flow chart of another industrial Ethernet data transmission method provided by an embodiment of the present application; Figure 5 is a flow chart of another industrial Ethernet data transmission method provided by an embodiment of the present application; Figure 6This is a specific flow chart of an industrial Ethernet data transmission method provided by an embodiment of the present application; Figure 7 It is a structural block diagram of an industrial Ethernet data transmission system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0010] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0011] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0012] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] The industrial Ethernet data transmission method provided in the embodiment of the present application is applied to data transmission, and in particular, can be applied to data transmission between a processor and a physical layer chip interface in an Ethernet scenario.

[0014] The industrial Ethernet data transmission method provided in the embodiment of the present application can be executed by a target device including a first element and a second element, wherein the first element is one of a CPU and an FPGA, the second element is the other of the CPU and the FPGA, and the target device can be an electronic device. Specifically, it can be executed by software or hardware installed on the electronic device. The electronic device can be, for example, a terminal device such as a desktop computer, a mobile phone, a laptop computer, a tablet computer, or a server.

[0015] The embodiments of the present application may adopt various processors, including but not limited to domestically developed processors, such as the Loongson 2K1000 series processors, which are usually used as core processors for business processing.

[0016] The following is a detailed description of the industrial Ethernet data transmission method provided by the embodiment of the present application through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0017] See also Figure 1 , Figure 1 1 is a flow chart of a method for transmitting industrial Ethernet data provided by an embodiment of the present application. Figure 1 As shown, the method comprises the following steps: Step 110: The first component obtains a first data frame, where the first data frame is an Ethernet data frame to be processed.

[0018] In the embodiment of the present application, the first data frame may be an Ethernet data frame to be sent by the first component to the second component.

[0019] Step 120: The first component determines information of a data description area in a memory based on the length information of the first data frame; the information of the data description area includes the number of data cache segments occupied by the first data frame in a data cache area in the memory.

[0020] In an embodiment of the present application, after obtaining the length information of the first data frame, the first component can determine the number of data cache segments occupied by the first data frame based on the length information of the first data frame and the segment length of the data cache segment. Specifically, the segment length of the data cache segment can be preset. When the length of the first data frame is less than or equal to the segment length of the data cache segment, the number of data cache segments occupied by the first data frame is 1, and the first data frame is not segmented. When the length of the first data frame is greater than the segment length of the data cache segment, the first data frame is segmented according to the segment length of the data cache segment, and the number of data cache segments occupied by the first data frame is greater than 1.

[0021] For example, the segment length of the data cache segment can be preset to 256 bytes. For an Ethernet data frame (excluding jumbo frames), the minimum length of the Ethernet data frame is 64 bytes and the maximum length is 1518 bytes. If the length of the first data frame is 64 bytes, then the length of the first data frame is less than the segment length of the data cache segment, and the number of data cache segments occupied by the first data frame is 1, that is, the first data frame can be stored using one data cache segment. If the first data frame is 1518 bytes, then the length of the first data frame is greater than the length of 5 data cache segments and less than the length of 6 data cache segments, and it can be determined that the number of data cache segments occupied by the first data frame is 6, that is, the first data frame can be stored using 6 data cache segments.

[0022] After determining the number of data cache segments occupied by the first data frame in the data cache area in the memory, the number of data cache segments occupied by the first data frame may be stored in the data description area in the memory as information of the data description area.

[0023] Step 130: The first component stores the first data frame in a first number of data cache segments in the data cache area; the first number is equal to the number of data cache segments occupied by the first data frame.

[0024] In an embodiment of the present application, after determining the first number of first data frames, that is, after determining the number of data cache segments occupied by the first data frame, it can be determined whether there are free first number of data cache segments in the data cache area. In the case that there are free first number of data cache segments in the data cache area, the first component can store the first data frame in the first number of data cache segments in the data cache area. In the case that there are no free first number of data cache segments in the data cache area, a signal indicating insufficient cache in the data cache area can be returned, and the first data frame can be stored in the first number of data cache segments in the data cache area after waiting until there are free first number of data cache segments in the data cache area.

[0025] Step 140: The second component performs a data read operation from the data cache area in the memory; wherein the data description area includes multiple data description segments, the data cache area includes multiple data cache segments, the number of the multiple data description segments is the same as the number of the multiple data cache segments; each of the multiple data description segments corresponds to a data cache segment and includes storage description information associated with the data cache segment.

[0026] Each of the plurality of data cache segments corresponds to a data description segment. That is, the plurality of data description segments correspond to the plurality of data cache segments one by one. At the same time, each of the plurality of data description segments corresponds to a storage description information, and the storage description information is used to describe the storage situation in the data cache segment corresponding to the data description segment.

[0027] In an embodiment of the present application, the second component can determine the storage situation in the data cache area of ​​the memory based on the storage description information stored in the data description area of ​​the memory, and then determine whether there is a data frame to be read in the data cache area of ​​the memory. When the second component determines that there is a data frame to be read in the data cache area of ​​the memory, it can perform a data read operation from the data cache area of ​​the memory. Specifically, the second component can read the storage description information stored in the data description area in sequence, that is, starting from the first data description segment, traversing the entire data description area, and performing a read operation on the data cache segment when the currently read data description segment indicates that the corresponding data cache segment is to be read.

[0028] In one embodiment of the present application, each of the multiple data description segments includes: a first part, a second part, a third part and a fourth part; the first part indicates whether the data description segment and the data cache segment corresponding to the data description segment are valid; the second part indicates the number of data cache segments occupied by the first data frame; the third part indicates the number of data cache segments occupied by the first data frame; the fourth part indicates the valid data length of the data cache segment corresponding to the data description segment.

[0029] Please refer to Figure 2 , Figure 2 Schematic diagram of storage information of a memory provided in an embodiment of the present application. Figure 2 As shown, label ① (i.e., ID field) is used to indicate the sequence number of n data description segments, label ⑧ (i.e., Data field) is used to indicate the sequence number of n data cache segments, and there is a one-to-one correspondence between n data description segments and n data cache segments. Label ④ (i.e., Flag field) is used to indicate the first part of the data description segment, label ⑤ (i.e., Size field) is used to indicate the second part of the data description segment, label ⑥ (i.e., No. field) is used to indicate the third part of the data description segment, and label ⑦ (i.e., Len field) is used to indicate the fourth part of the data description segment.

[0030] Specifically, the four parts of the data description segment can be allocated according to the preset segment length of the data description segment. Figure 2As shown, the segment length of the data description segment can be 2 bytes, which is divided into 16 bits (0~15 bits) by bit. Among them, bit 15 is used to store the first part of the data description segment (a total of 1 bit), which is used to indicate whether the data description segment and the data cache segment corresponding to the data description segment are valid. When the first part of the data description segment is 1, the first part indicates that the data cache segment corresponding to the data description segment is valid, that is, the corresponding data cache segment stores data. When the first part of the data description segment is 0, the first part indicates that the data cache segment corresponding to the data description segment is invalid, that is, the corresponding data cache segment does not store data. Bits 14~12 are used to store the second part of the data description segment (a total of 3 bits), which are used to indicate the number of data cache segments occupied by the first data frame. Bits 11~9 are used to store the third part of the data description segment (a total of 3 bits), which are used to indicate the number of data cache segments occupied by the first data frame. Bits 8~0 are used to store the fourth part of the data description segment (a total of 9 bits), which are used to indicate the valid data length of the data cache segment corresponding to the data description segment.

[0031] For example, the length of the first data frame is 544 bytes, and the length of the preset data cache segment is 256 bytes. The first number of data cache segments occupied by the first data frame can be determined by dividing the length of the first data frame 544 bytes by the length of the data cache segment 256 bytes, that is, the first number can be determined to be 3, and the effective lengths of the three occupied data cache segments are determined to be 256 bytes, 256 bytes, and 32 bytes, respectively. At this time, the specific information of the four parts of the three data description segments corresponding to the three data cache segments can be determined, and the information can be stored in the corresponding positions of the three data description segments in the data description area.

[0032] Among them, the three data cache segments occupied by the first data frame can be numbered 1, 2 and 3 respectively, the first part of the three data description segments is 1 (indicating that the three data cache segments corresponding to the three data description segments are stored), the second part is 3 (the number of data cache segments occupied by the first data frame), the third part is 1, 2 and 3 respectively (the number of data cache segments occupied by the first data frame), and the fourth part is 256, 256 and 32 respectively (the effective data length of the data cache segment corresponding to the data description segment).

[0033] It should be noted that Figure 2 The allocation method used in the example is only an example, and the length and order of each part can be set flexibly.

[0034] In one embodiment of the present application, the length of each of the multiple data cache segments is the same, the first number of data cache segments in the data cache area is the first number of consecutive data cache segments in the data cache area, and the first number is an integer greater than 1.

[0035] In the embodiments of the present application, Figure 2 As shown, the n data cache segments in the data cache area are aligned, that is, the length of each of the multiple data cache segments is the same. For example, the length of the data cache segment can be preset to 256 bytes, and the length of each of the multiple data cache segments is 256 bytes. In this case, the n data cache segments in the data cache area are aligned with 256 bytes.

[0036] Meanwhile, in the process of storing the first data frame in the data buffer area, the first data frame may be stored in a first number of consecutive data buffer segments in the data buffer area. For example, if the first data frame occupies three data buffer segments, the first data frame may be stored in data buffer segments numbered 1, 2, and 3 in the data buffer area.

[0037] In the embodiment of the present application, by storing the first data frame in a first number of continuous data cache segments in the data cache area, it is convenient for the second component to read the first data frame, and the first data frame can be read from the data cache area in sequence starting from the starting data cache segment in the data cache area occupied by the first data frame. In this way, for a complete frame of network data, the continuity of the data in the memory can be guaranteed, and the data can be segmented. By transmitting each segment of data in sequence, address alignment is guaranteed, and memory alignment operations are avoided during data transmission.

[0038] In one embodiment of the present application, the first element is one of a CPU and an FPGA, and the second element is the other of the CPU and the FPGA; when the first element is the CPU and the second element is the FPGA, the Ethernet data frame to be processed is an Ethernet data frame to be sent by the CPU; the data description area includes a sending data description area, and the data buffer area includes a sending data buffer area; when the first element is the FPGA and the second element is the CPU, the Ethernet data frame to be processed is an Ethernet data frame to be received by the CPU; the data description area includes a receiving data description area, and the data buffer area includes a receiving data buffer area.

[0039] In an embodiment of the present application, when the first element is a CPU and the second element is an FPGA, the first data frame is an Ethernet data frame to be sent by the CPU to the FPGA, and the first data frame is a network data frame received by the CPU from the network protocol stack. The data description area includes a send data description area, and the data buffer area includes a send data buffer area. Specifically, the CPU obtains a first data frame, and the first data frame is an Ethernet data frame to be sent by the CPU; the CPU determines the information of the send data description area in the memory based on the length information of the first data frame; the information of the send data description area includes the number of send data buffer segments occupied by the first data frame in the send data buffer area in the memory; the CPU stores the first data frame in the first number of send data buffer segments in the send data buffer area; the first number is equal to the number of send data buffer segments occupied by the first data frame; the FPGA performs a data read operation from the send data buffer area in the memory.

[0040] In the case where the first element is an FPGA and the second element is a CPU, the first data frame is an Ethernet data frame to be sent by the FPGA to the CPU, the data description area includes a received data description area, and the data buffer area includes a received data buffer area. Specifically, the FPGA obtains a first data frame, which is an Ethernet data frame to be received by the CPU; the FPGA determines the information of the received data description area in the memory based on the length information of the first data frame; the information of the received data description area includes the number of received data buffer segments occupied by the first data frame in the received data buffer area in the memory; the FPGA stores the first data frame in a first number of received data buffer segments in the received data buffer area, and sends a network interrupt signal to the CPU; the first number is equal to the number of received data buffer segments occupied by the first data frame; the CPU performs a data read operation from the received data buffer area in the memory in response to the network interrupt signal sent by the CPU.

[0041] The format of the sending data description area and the receiving data description area can refer to Figure 2 The form of the data description area in the transmission data buffer area and the form of the transmission data buffer area can refer to Figure 2In fact, the first data frame may be a data frame transmitted between the CPU and the peripheral component interconnect express (PCIe) network card extended by the FPGA, which is divided into a sending data area and a receiving data area according to the direction of data frame transmission, and the sending data area is divided into a sending data description area and a sending data buffer area according to the function, and the receiving data area is divided into a receiving data description area and a receiving data buffer area.

[0042] Please refer to Figure 3 , Figure 3 1 is a general concept diagram of an industrial Ethernet data transmission method provided by an embodiment of the present application. Figure 3 As shown, the method involves a processor (such as a Loongson 2K1000 processor, as a host processor), a PCIe network card, a PCIe interface ( Figure 3 The processor includes a processor core and a direct memory access controller (DMA), wherein the PCIe network card is a multi-network card expanded by the FPGA chip, and the PCIe interface is responsible for the physical connection between the processor and the FPGA to ensure the reliability of data transmission.

[0043] like Figure 3 As shown, the memory includes a dedicated memory area allocated to the PCIe network card extended by the FPGA, and the dedicated memory area is used to realize network data transmission between the processor and the PCIe network card extended by the FPGA. Each PCIe network card corresponds to a dedicated memory area (such as Figure 3 Ethernet 0, ..., Ethernet N in the example), the dedicated memory area includes a send data description area (such as Figure 3 Tx description area in the send data buffer (such as Figure 3 Tx buffer area in the receive data description area (such as Figure 3 Rx description area in the receive data buffer (such as Figure 3 The Rx buffer area in the processor can poll to complete the data transmission of N PCIe network cards. The sending data buffer area is used to store the network data to be sent by the processor, the sending data description area is used to store the storage description information of the network data to be sent by the processor (including frame length and segmentation information), the receiving data buffer area is used to store the network data received by the processor, and the receiving data description area is used to store the storage description information of the network data received by the processor (including frame length and segmentation information).

[0044] like Figure 3As shown, for each PCIe network card corresponding to the physical layer (Physical Layer, PHY) chip (such as Figure 3 PHY0, ..., PHY N in the FPGA, management data clock (Management DataClock) data transmission and management data input / output (MDIO) data transmission are performed between the FPGA and the physical layer chip. At the same time, data transmission is also performed between the FPGA and the physical layer chip through a media independent interface (Media Independent interface, MII) interface and a gigabit media independent interface (Gigabit Media Independant Interface, GMII).

[0045] In addition, before data transmission between the CPU and the PCIe network card expanded by the FPGA, an initialization operation can be performed first. Specifically, first, a dedicated memory area is allocated to the PCIe network card according to the number of PCIe network cards expanded by the FPGA, that is, a dedicated memory area is allocated to each PCIe network card, and the dedicated memory area is partitioned (divided into four areas: the sending data description area, the sending data buffer area, the receiving data description area, and the receiving data buffer area). Then, the PCIe DMA window of the configuration processor points the PCIe interface to the dedicated memory area to establish a data transmission channel between the FPGA and the dedicated memory area, which is convenient for subsequent data storage and data reading.

[0046] In one embodiment of the present application, the memory is a memory connected to the CPU.

[0047] In the embodiments of the present application, Figure 3 As shown, the memory may be a memory on the CPU side. Thus, compared with the related art in which Ethernet data is stored in the memory on the FPGA side, this method of storing Ethernet data in the memory on the processor side can reduce the demand for the memory on the FPGA side, and can also increase the reading and writing rate of Ethernet data, further increasing the transmission rate of Ethernet data.

[0048] In an embodiment of the present application, a first component obtains a first data frame, which is an Ethernet data frame to be processed; the first component determines information of a data description area in a memory based on length information of the first data frame; the information of the data description area includes the number of data cache segments occupied by the first data frame in a data cache area in the memory; the first component stores the first data frame in a first number of data cache segments in the data cache area; the first number is equal to the number of data cache segments occupied by the first data frame; the second component performs a data read operation from the data cache area in the memory; wherein the data description area includes multiple data description segments, the data cache area includes multiple data cache segments, and the number of the multiple data description segments is the same as the number of the multiple data cache segments; each of the multiple data description segments corresponds to a data cache segment and includes storage description information associated with the data cache segment. In this way, the data cache area in the memory includes multiple data cache segments. For the first data frame to be processed obtained by the first component, the first number of data cache segments occupied by the first data frame is determined based on the length information of the first data frame, and according to the first number of data cache segments occupied by the first data frame, the first data frame is stored in the first number of data cache segments in the data cache area in the memory. This method makes full use of the storage space of the memory and solves the problem of low storage space utilization in related technologies.

[0049] See also Figure 4 , Figure 4 FIG. 1 is a flow chart of another method for transmitting industrial Ethernet data provided by an embodiment of the present application. Figure 4 As shown, the method comprises the following steps: Step 410: The first component obtains a first data frame, where the first data frame is an Ethernet data frame to be processed.

[0050] Step 420: The first component determines information of a data description area in a memory based on length information of the first data frame; the information of the data description area includes the number of data cache segments occupied by the first data frame in a data cache area in the memory, and the data description area also includes a first serial number for the first component, and the first serial number indicates the serial number of the starting data cache segment for the first component to perform this storage operation.

[0051] In the embodiment of the present application, in order to facilitate the first component to perform a storage operation, the data description area may also include a first serial number for the first component, and the first serial number is used to indicate the serial number of the starting data cache segment for the first component to perform this storage operation. Figure 2 As shown, Figure 2The field shown by sequence number ② is the first serial number of the first element. The field length of the first serial number can be aligned with the length of the data description segment, that is, the field length of the first serial number can be the same as the field length of the data description segment, for example, both can be 2 bytes.

[0052] Step 430: The first component obtains the first serial number from the data description area.

[0053] In the embodiment of the present application, before storing the first data frame in the first number of data cache segments in the data cache area, the first sequence number of the first element can be obtained from the data description area to determine the starting data cache segment storing the first data frame. For example, if the first sequence number is 3, then the sequence number of the starting data cache segment storing the first data frame can be determined to be 3.

[0054] Step 440: The first component stores the first data frame into a first number of data cache segments in the data cache area, starting from the starting data cache segment indicated by the first sequence number.

[0055] In the embodiment of the present application, when storing the first data frame, the first component may start storing from the starting data cache segment, and may sequentially store each segment obtained by dividing the first data frame into a first number of data cache segments in the data cache area. For example, if the first data frame is divided into 3 segments, the first number is 3, and the first sequence number is 3, then the 3 segmented data frames obtained by dividing may be sequentially stored into 3 data cache segments numbered 3, 4, and 5.

[0056] In one embodiment of the present application, after the first component stores the first data frame into a first number of data cache segments in the data cache area starting from the starting data cache segment indicated by the first serial number, the industrial Ethernet data transmission method, in addition to steps 310 to 350, further includes: the first component determines a first update value based on the first serial number, the first number and the total number of data cache segments included in the data cache area; the first component updates the first serial number in the data description area based on the first update value, and the updated first serial number indicates the serial number of the starting data cache segment for the first component to perform the next storage operation.

[0057] In an embodiment of the present application, since the first number of data cache segments starting from the starting data cache segment corresponding to the first serial number has stored the first data frame, the first serial number can be updated so that the first serial number indicates the serial number of the starting data cache segment for the first element to perform the next storage operation. Specifically, the total number of data cache segments contained in the data cache area (including stored and unstored data cache segments) can be obtained, the first serial number and the first number can be summed, and the sum result is modulo the total number of segments to obtain the first update value. After determining the first update value, the first update value can be directly determined as the updated first serial number.

[0058] For example, the data cache area includes 8 data cache segments, the first sequence number is 2, and the first number is 5. In this case, the first data frame divided into 5 segments can be stored in the data cache segments with sequence numbers 2, 3, 4, 5 and 6 respectively. By summing the first sequence number and the first number to obtain 7, the sum result 7 modulo the total number of segments 8 is 7, and then the first sequence number is updated to 7, which just connects to the end point of the current storage (the data cache segment with sequence number 6). In this way, the sequential storage of the data cache area can be realized, and there will be no situation where the position of the current storage of the first data frame is discontinuous with the position of the next storage of the data frame, thereby avoiding the waste of memory caused by discontinuous cache space.

[0059] Step 450: The second component performs a data read operation from the data cache area in the memory.

[0060] In an embodiment of the present application, the data description area also includes a first serial number for indicating the starting data cache segment of the first element to perform this storage operation. By introducing the first serial number, when the first element performs this storage operation, the starting position of storing the first data frame can be directly determined by obtaining the first serial number. There is no need to use other more complicated methods to determine the starting position of storing the first data frame, which can simplify the storage process of the first data frame.

[0061] See also Figure 5 , Figure 5 FIG. 1 is a flow chart of another method for transmitting industrial Ethernet data provided by an embodiment of the present application. Figure 5 As shown, the method comprises the following steps: Step 510: The first component obtains a first data frame, where the first data frame is an Ethernet data frame to be processed.

[0062] Step 520: The first component determines information of a data description area in a memory based on length information of the first data frame; the information of the data description area includes the number of data cache segments occupied by the first data frame in a data cache area in the memory, and the data description area also includes a first serial number for the first component and a second serial number for the second component.

[0063] The first sequence number and the second sequence number are independent of each other; the second sequence number indicates the sequence number of the starting data cache segment for the second element to perform the current read operation.

[0064] In the embodiment of the present application, corresponding to the first serial number, in order to facilitate the second component to perform a read operation from the data cache area, the data description area also includes a second serial number for indicating the starting data cache segment for the second component to perform this read operation. Figure 2 As shown, Figure 2 The field shown by sequence number ③ is the second serial number of the second element. The field length of the second serial number can be aligned with the length of the data description segment, that is, the field length of the second serial number can be the same as the field length of the data description segment, for example, both can be 2 bytes.

[0065] Step 530: The first component obtains the first serial number from the data description area.

[0066] Step 540: The first component stores the first data frame into a first number of data cache segments in the data cache area, starting from the starting data cache segment indicated by the first sequence number.

[0067] Step 550: The second component obtains the second serial number from the data description area.

[0068] In the embodiment of the present application, the first component stores the data frame into the data buffer area and the second component reads the data frame from the data buffer area. The two operations are independent of each other. That is, there may be the following scenario: the first component stores data frame A into the data buffer area, and the second component reads data frame B from the data buffer area.

[0069] Therefore, when the second element performs a read operation, the second serial number of the second element can be obtained from the data description area to determine the starting position of the read data. For example, if the second serial number is 1, it can be determined to start reading from the data cache segment with serial number 1. In addition, before performing the read operation, the storage description information corresponding to the second serial number can be obtained from the data description area to determine whether the data cache segment indicated by the second serial number is valid. If the data cache segment indicated by the second serial number is valid (that is, the first part of the data description segment is 1), the read operation is performed.

[0070] Step 560: The second component starts from the starting data cache segment indicated by the second serial number and reads data stored in at least one data cache segment from the data cache area in the memory.

[0071] In an embodiment of the present application, when performing a read operation, the number of data cache segments to be read can be determined based on the content of the data description segment corresponding to the second serial number, and starting from the starting data cache segment indicated by the second serial number in the data cache area, data of at least one data cache segment can be read from the data cache area.

[0072] For example, if the second sequence number is 2, the first part of the data description segment with sequence number 2 is 1, the second part is 3, the third part is 1, and the fourth part is 256, then it can be determined that this read operation is used to read 3 data cache segments from the data cache area, and first read 256 bytes of data from the data cache segment with sequence number 2. Then, the content of the data description segment with sequence number 3 can be obtained (the first part is 1, the second part is 3, the third part is 2, and the fourth part is 256), and continue to read 256 bytes of data from the data cache segment with sequence number 3. Then, the content of the data description segment with sequence number 4 can be obtained (the first part is 1, the second part is 3, the third part is 3, and the fourth part is 32 bytes), and continue to read 32 bytes of data from the data cache segment with sequence number 4. At this time, the reading of the three data cache segments numbered 1, 2, and 3 is completed, and the current read operation is completed.

[0073] In one embodiment of the present application, after the second element starts from the starting data cache segment indicated by the second serial number and reads the data stored in at least one data cache segment from the data cache area in the memory, the industrial Ethernet data transmission method, in addition to steps 510 to 560, also includes: the second element determines a second update value based on the second serial number, the number of data cache segments read by the second element and the total number of data cache segments included in the data cache area; the second element updates the second serial number in the data description area based on the second update value, and the updated second serial number indicates the serial number of the starting data cache segment for the second element to perform the next read operation.

[0074] In an embodiment of the present application, after executing the current read operation, a clear operation may be performed on at least one data cache segment read by the current read operation in the data cache area, so that the at least one data cache segment can be used for the first component to perform a storage operation. While the clear operation is performed on at least one data cache segment, the second sequence number may be updated, so that the second sequence number indicates the sequence number of the starting data cache segment for the second component to perform the next read operation.

[0075] Specifically, the total number of data cache segments contained in the data cache area (including stored and unstored data cache segments) can be obtained, the second sequence number and the number of data cache segments read by the second element are summed, and the summation result is modulo the total number of segments to obtain the second update value. After determining the second update value, the second update value can be directly determined as the updated second sequence number.

[0076] For example, the data cache area contains 8 data cache segments, the second serial number is 1, and the number of data cache segments read by the second element is 2. In this case, 2 data cache segments corresponding to serial numbers 1 and 2 can be read from the data cache area. By summing the second serial number and the number of data cache segments read by the second element, 3 is obtained, and the sum result 3 is modulo the total number of segments 8 to obtain 3, then the second serial number is updated to 3, which just connects to the end point of the current read operation (the data cache segment with serial number 2). In this way, sequential reading of the data cache area can be achieved, and there will be no discontinuity between the currently read data frame and the next read data frame, further ensuring that the data frames stored in the data cache area are adjacent to each other, avoiding memory waste caused by the non-adjacent data frames stored in the data cache area.

[0077] In an embodiment of the present application, the data description area also includes a second serial number indicating the starting data cache segment for the second element to perform this read operation. By introducing the second serial number, when the second element performs this read operation, the starting position of the read operation can be directly determined by obtaining the second serial number. There is no need to use other more complicated methods to determine the starting position of the read operation, which can simplify the process of the second element performing the read operation.

[0078] See also Figure 6 , Figure 6 This is a specific flow chart of an industrial Ethernet data transmission method provided by an embodiment of the present application. Figure 6 As shown, the method comprises the following steps: Step 610: The first component obtains a first data frame, where the first data frame is an Ethernet data frame to be processed.

[0079] Step 615: The first component determines information of a data description area in a memory based on the length information of the first data frame; the information of the data description area includes the number of data cache segments occupied by the first data frame in a data cache area in the memory, and the data description area also includes a first serial number for the first component and a second serial number for the second component, and the first serial number and the second serial number are independent of each other.

[0080] In an embodiment of the present application, the data description area includes multiple data description segments, and the data cache area includes multiple data cache segments, the number of the multiple data description segments is the same as the number of the multiple data cache segments; each of the multiple data description segments corresponds to a data cache segment and includes storage description information associated with the data cache segment.

[0081] In an embodiment of the present application, each of the multiple data description segments includes: a first part, a second part, a third part and a fourth part; the first part indicates whether the data description segment and the data cache segment corresponding to the data description segment are valid; the second part indicates the number of data cache segments occupied by the first data frame; the third part indicates the number of data cache segments occupied by the first data frame; the fourth part indicates the valid data length of the data cache segment corresponding to the data description segment.

[0082] The length of each of the plurality of data cache segments is the same, the first number of data cache segments in the data cache area is a first number of consecutive data cache segments in the data cache area, and the first number is an integer greater than 1. The memory is a memory connected to the CPU, that is, the memory is a memory on the CPU side.

[0083] In an embodiment of the present application, the first serial number indicates the serial number of the starting data cache segment for the first element to perform this storage operation, and the second serial number indicates the serial number of the starting data cache segment for the second element to perform this read operation.

[0084] Step 620: The first component obtains the first serial number from the data description area.

[0085] Step 625: The first component stores the first data frame into a first number of data cache segments in the data cache area, starting from the starting data cache segment indicated by the first sequence number.

[0086] Step 630: The first component determines a first update value based on the first sequence number, the first number, and the total number of data cache segments included in the data cache area.

[0087] Step 635: The first component updates the first sequence number in the data description area based on the first update value, and the updated first sequence number indicates the sequence number of the starting data cache segment for the first component to perform the next storage operation.

[0088] Step 640: The second component obtains the second serial number from the data description area.

[0089] In the embodiment of the present application, the first element is one of a CPU and an FPGA, and the second element is the other of the CPU and the FPGA.

[0090] In the case where the first component is a CPU and the second component is an FPGA, the Ethernet data frame to be processed is an Ethernet data frame to be sent by the CPU; the data description area includes a send data description area, and the data buffer area includes a send data buffer area. The process of the CPU sending data to the FPGA is as follows: the driver of the Loongson 2K1000 receives a network data frame from the network protocol stack, and determines that the network data frame occupies a segment of the send data buffer segment to store the data to be sent according to the length d of the network data frame divided by the length of the data buffer segment (256 bytes), and records the effective length b of the last send data buffer segment. Check the first part (flag bit) of the data description segment of the continuous segment a corresponding to the operation sequence number c1 of the processor to determine whether there are sufficient idle send data buffer segments for storing the network data frame to be sent. If yes, proceed to the next step, otherwise return to the network protocol stack send buffer is insufficient.

[0091] The network data frame is copied to the continuous a-segment send data cache segment corresponding to the processor's operation sequence number c1, and the first part of the corresponding send data description segment is written as 1 to enable sending, the second part is written as a, the third part of the a-segment send data description segment is written with the segment sequence number 0~a-1 respectively, and the fourth part of the a-segment send data description segment is written with the valid data length 256, 256,..., b. After the storage is completed, the sum of the processor's operation sequence number c1 and a is modulo the total number of segments n to obtain the updated processor's operation sequence number c1, which points to the sequence number of the next send data cache segment to be stored. Then, the FPGA is notified to read the sent network data.

[0092] FPGA reads the continuous multiple send data description segments corresponding to the FPGA operation serial number c2 through the PCIe interface, and determines whether there is data to be sent based on the first part (flag bit) of the send data description segment corresponding to c2. If yes, proceed to the next step. FPGA determines and reads the corresponding send data cache segment a based on the second part of the send data description segment. After the read operation is completed, the first part (flag bit bit15) of the send data description segment a is cleared to clear the send enable, and the sum of the FPGA operation serial number c2 and a is modulo the total number of segments n to obtain the updated processor operation serial number c2, which is the serial number pointing to the next send data cache segment to be read.

[0093] In the case where the first component is an FPGA and the second component is a CPU, the Ethernet data frame to be processed is an Ethernet data frame to be received by the CPU; the data description area includes a receiving data description area, and the data buffer area includes a receiving data buffer area. The process of FPGA sending data to the CPU is as follows: First, the FPGA stores the data to be received by the CPU in the receiving data buffer area, and sends an interrupt signal to the CPU, which is consistent with the CPU storage process and is not repeated here. After the CPU receives the network interrupt, it checks the first part (flag bit) of the receiving data description segment corresponding to the CPU's receiving operation sequence number c3 to determine whether there is network data to be received. If yes, proceed to the next step, otherwise detect the next PCIe network card; determine that the network data occupies the receiving data buffer segment a through the second part (bit14-bit12) of the receiving data description segment, and copy the data from the receiving data buffer area to the network protocol stack according to the sequence number of the third part (bit11-bit9) of the receiving data description segment a and the valid data length of the fourth part (bit8-bit0). Then, clear the first part of a receive data description segment (bit 15 receive flag), take the modulus of the sum of the CPU operation sequence number c3 and a by the total number of segments n, and point to the next receive data description segment to be read. You can continue to check the flag bit of the receive data description segment corresponding to the new CPU operation sequence number to determine whether there is received data. If so, the CPU continues to read the data, otherwise it ends the reading.

[0094] Step 645: The second component starts from the starting data cache segment indicated by the second serial number and reads data stored in at least one data cache segment from the data cache area in the memory.

[0095] Step 650: The second component determines a second update value based on the second serial number, the number of data cache segments read by the second component, and the total number of data cache segments included in the data cache area.

[0096] Step 655: The second component updates the second sequence number in the data description area based on the second update value, and the updated second sequence number indicates the sequence number of the starting data cache segment for the second component to perform the next read operation.

[0097] In an embodiment of the present application, a first component obtains a first data frame, which is an Ethernet data frame to be processed; the first component determines information of a data description area in a memory based on length information of the first data frame; the information of the data description area includes the number of data cache segments occupied by the first data frame in a data cache area in the memory; the first component stores the first data frame in a first number of data cache segments in the data cache area; the first number is equal to the number of data cache segments occupied by the first data frame; the second component performs a data read operation from the data cache area in the memory; wherein the data description area includes multiple data description segments, the data cache area includes multiple data cache segments, and the number of the multiple data description segments is the same as the number of the multiple data cache segments; each of the multiple data description segments corresponds to a data cache segment and includes storage description information associated with the data cache segment. In this way, the data cache area in the memory includes multiple data cache segments. For the first data frame to be processed obtained by the first component, the first number of data cache segments occupied by the first data frame is determined based on the length information of the first data frame, and according to the first number of data cache segments occupied by the first data frame, the first data frame is stored in the first number of data cache segments in the data cache area in the memory. This method makes full use of the storage space of the memory and solves the problem of low storage space utilization in related technologies.

[0098] It is important to understand that Figures 1 to 6 The explanations of the same or corresponding steps in the above may refer to each other. For example, Figure 1 The explanation of step 110 and step 120 in Figure 4 Step 410 and step 420 in .

[0099] At the same time, it should be understood that a method for transmitting industrial Ethernet data provided by an embodiment of the present application can have the following beneficial effects: First, the data description area and data cache area of ​​the PCIe network card are placed in the processor side memory, and the PCIe network card expanded by the FPGA is only used as a control and data transmission channel. The FPGA does not need to provide a storage function, thereby reducing the demand for FPGA memory. At the same time, the data cache area can also be used to cache network data packets. In the process of sending network packets to the protocol stack, when the protocol stack is in a non-idle state, the data cache area can be used to cache network data packets, and the memory demand for the protocol stack is not high, reducing the memory overhead of the protocol stack. Second, the data cache area is segmented, and each segment is fixed to the same byte. An Ethernet data packet can be stored using multiple continuous data cache segments. This can reduce the memory waste caused by the storage of small packet data. At the same time, the aligned memory address avoids the alignment operation during the PCIe transmission process and speeds up the data transmission rate. Third, the solution provided in this application is simple in design. Multiple network ports can be expanded according to actual needs without changing the structure. It supports customizing the content of the data description area to control the data transmission between the processor and multiple network cards expanded by FPGA. Placing the data description area in the memory on the processor side can facilitate the processor's operation and maintenance of the description information. The size of the data cache area can be adjusted according to the designed network card to achieve efficient use of the processor's memory.

[0100] See also Figure 7 , Figure 7 1 is a structural block diagram of an industrial Ethernet data transmission system provided by an embodiment of the present application. Figure 7 As shown, the industrial Ethernet data transmission system 700 includes: a first component 710 and a second component 720 .

[0101] The first component 710 is used to obtain a first data frame, where the first data frame is an Ethernet data frame to be processed; determine information of a data description area in a memory based on length information of the first data frame; the information of the data description area includes the number of data cache segments occupied by the first data frame in a data cache area in the memory; store the first data frame in a first number of data cache segments in the data cache area; the first number is equal to the number of data cache segments occupied by the first data frame; The second element 720 is used to perform a data read operation from the data cache area in the memory; wherein the data description area includes multiple data description segments, the data cache area includes multiple data cache segments, and the number of the multiple data description segments is the same as the number of the multiple data cache segments; each of the multiple data description segments corresponds to a data cache segment and includes storage description information associated with the data cache segment; the first element is one of the CPU and the FPGA, and the second element is the other of the CPU and the FPGA.

[0102] An embodiment of the present application provides an industrial Ethernet data transmission system, comprising: a first element and a second element; wherein the first element is used to obtain a first data frame, the first data frame being an Ethernet data frame to be processed; based on the length information of the first data frame, determining the information of a data description area in a memory; the information of the data description area includes the number of data cache segments occupied by the first data frame in a data cache area in the memory; storing the first data frame in a first number of data cache segments in the data cache area; the first number is equal to the number of data cache segments occupied by the first data frame; the second element is used to perform a data read operation from the data cache area in the memory; wherein the data description area includes multiple data description segments, the data cache area includes multiple data cache segments, and the number of the multiple data description segments is the same as the number of the multiple data cache segments; each of the multiple data description segments corresponds to a data cache segment and includes storage description information associated with the data cache segment; the first element is one of a CPU and an FPGA, and the second element is the other of the CPU and the FPGA. In this way, the data cache area in the memory includes multiple data cache segments. For the first data frame to be processed obtained by the first component, the first number of data cache segments occupied by the first data frame is determined based on the length information of the first data frame, and according to the first number of data cache segments occupied by the first data frame, the first data frame is stored in the first number of data cache segments in the data cache area in the memory. This method makes full use of the storage space of the memory and solves the problem of low storage space utilization in related technologies.

[0103] The industrial Ethernet data transmission system provided in the embodiment of the present application can implement each process implemented in the above method embodiment, and will not be described again here to avoid repetition.

[0104] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of each embodiment of the industrial Ethernet data transmission method are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0105] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0106] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0107] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned method embodiment and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0108] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0109] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0110] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A method for transmitting industrial Ethernet data, characterized in that: include: The first component obtains a first data frame, where the first data frame is an Ethernet data frame to be processed; The first component determines information of a data description area in a memory based on the length information of the first data frame; the information of the data description area includes the number of data cache segments occupied by the first data frame in a data cache area in the memory; The first component stores the first data frame in a first number of data cache segments in the data cache area; The first number is equal to the number of data cache segments occupied by the first data frame; A second component performs a data read operation from the data buffer area in the memory; Among them, the data description area includes multiple data description segments, the data cache area includes multiple data cache segments, the number of the multiple data description segments is the same as the number of the multiple data cache segments; each of the multiple data description segments corresponds to a data cache segment and includes storage description information associated with the data cache segment.

2. The method according to claim 1, characterized in that Each of the multiple data description segments includes: a first part, a second part, a third part and a fourth part; the first part indicates whether the data description segment and the data cache segment corresponding to the data description segment are valid; the second part indicates the number of data cache segments occupied by the first data frame; the third part indicates the number of data cache segments occupied by the first data frame; the fourth part indicates the valid data length of the data cache segment corresponding to the data description segment.

3. The method according to claim 1 or 2, characterized in that: The length of each of the multiple data cache segments is the same, the first number of data cache segments in the data cache area is a first number of consecutive data cache segments in the data cache area, and the first number is an integer greater than 1.

4. The method according to claim 1 or 2, characterized in that: The data description area further includes: a first serial number for the first element; the first serial number indicates the serial number of the starting data cache segment for the first element to perform this storage operation; The first component stores the first data frame in a first number of data cache segments in the data cache area, including: The first component obtains the first serial number from the data description area; The first component stores the first data frame into a first number of data cache segments in the data cache area, starting from the starting data cache segment indicated by the first sequence number.

5. The method according to claim 4, characterized in that After the first component stores the first data frame in a first number of data cache segments in the data cache area, the method further includes: The first component determines a first update value based on the first sequence number, the first number, and a total number of data cache segments included in the data cache area; The first component updates the first sequence number in the data description area based on the first update value, and the updated first sequence number indicates the sequence number of the starting data cache segment for the first component to perform a next storage operation.

6. The method according to claim 4, characterized in that The data description area further includes: a second serial number for the second element, the first serial number and the second serial number are independent of each other; the second serial number indicates the serial number of the starting data cache segment for the second element to perform the current read operation; The second component performs a data read operation from the data buffer area in the memory, including: The second component obtains the second serial number from the data description area; The second component reads data stored in at least one data cache segment from the data cache area in the memory, starting from the starting data cache segment indicated by the second serial number.

7. The method according to claim 6, characterized in that After the second component performs a data read operation from the data buffer area in the memory, the method further includes: The second component determines a second update value based on the second sequence number, the number of data cache segments read by the second component, and the total number of data cache segments included in the data cache area; The second component updates the second sequence number in the data description area based on the second update value, and the updated second sequence number indicates the sequence number of the starting data cache segment for the second component to perform a next read operation.

8. The method according to claim 1, characterized in that The first element is one of a CPU and a field programmable gate array FPGA, and the second element is the other of the CPU and the FPGA; In the case where the first component is a CPU and the second component is an FPGA, the Ethernet data frame to be processed is an Ethernet data frame to be sent by the CPU; the data description area includes a send data description area, and the data buffer area includes a send data buffer area; When the first component is an FPGA and the second component is a CPU, the Ethernet data frame to be processed is an Ethernet data frame to be received by the CPU; the data description area includes a received data description area, and the data buffer area includes a received data buffer area.

9. The method according to claim 8, characterized in that The memory is a memory connected to the CPU.

10. An industrial Ethernet data transmission system, characterized in that: comprising a first element and a second element; The first component is used to obtain a first data frame, where the first data frame is an Ethernet data frame to be processed; determine information of a data description area in a memory based on length information of the first data frame; the information of the data description area includes the number of data cache segments occupied by the first data frame in a data cache area in the memory; and store the first data frame in a first number of data cache segments in the data cache area; The first number is equal to the number of data cache segments occupied by the first data frame; The second element is used to perform a data read operation from the data buffer area in the memory; Among them, the data description area includes multiple data description segments, the data cache area includes multiple data cache segments, the number of the multiple data description segments is the same as the number of the multiple data cache segments; each of the multiple data description segments corresponds to a data cache segment and includes storage description information associated with the data cache segment; the first element is one of a CPU and a field programmable gate array FPGA, and the second element is the other of the CPU and the FPGA.

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