Multipath parallel receiver and device

Abstract

The invention discloses a multi-channel parallel receiver and a multi-channel parallel receiver device. The receiver comprises a frequency hopping multiplexer, N automatic gain control amplification paths, an N * M power synthesis module, M analog-to-digital conversion units and a baseband processing unit, the frequency hopping multiplexer receives N paths of input signals, separates the N paths of input signals into N paths of output signals, and suppresses out-of-band input signals; each path of output signal of the frequency hopping multiplexer is respectively input to each automatic gain amplification path, and the gain is automatically adjusted in the automatic gain amplification path; after each automatic gain control amplification path outputs the output signal, frequency band integration of the output signal is carried out in the N * M paths of power combiners; the output signals after frequency band integration respectively enter the M analog-to-digital conversion units, each analog-to-digital conversion unit samples the output signals according to a set sampling frequency within a frequency band range, and the sampled output signals are demodulated by the baseband processing unit. The receiver can give consideration to both signal receiving dynamic and signal frequency band coverage.

Description

Technical Field

[0001] The present invention relates to the technical field of signal reception, and more specifically, to a multi-channel parallel receiver and device. Background Art

[0002] Multi-channel parallel reception can realize the simultaneous reception of multiple signals, which can improve transmission efficiency and enhance anti-interference ability.

[0003] To ensure sensitivity, traditional multi-channel parallel receivers need to achieve full-band reception. On the one hand, the method of amplifying the signal first and then distributing and filtering the power can be adopted. However, the nonlinear amplification of the front-end amplifier will cause the receiver to have insufficient signal resolution and severely reduce the instantaneous dynamics. On the other hand, a fixed multiplexer can be used for signal separation. Although this can guarantee the resolution of the receiver to a certain extent, it cannot achieve seamless coverage of multiple frequencies of the signal.

[0004] The prior art discloses a broadband dynamic multi-channel parallel receiver, which includes an analog end connected to an antenna and a digital end connected to the analog end; the analog end includes a differential balanced amplifier module, a power inversion module and a cross sampling module connected in sequence; the digital end uses a main control module. The parallel receiver uses a band-stop filter to attenuate the signal with a large amplitude in the parallel received signal, but each band-stop filter can only attenuate a received signal with a large amplitude, and it cannot filter out the interference outside the frequency band. After these interference signals enter the receiver, they will mix with the useful signal, resulting in signal distortion, reduced signal-to-noise ratio and other problems, thereby seriously affecting the normal reception of the receiver. In addition, due to the presence of interference signals, the sensitivity of the receiver may be affected, resulting in a decrease in the performance of the receiver in a weak signal environment. Summary of the invention

[0005] The present invention aims at the defects that the traditional multi-channel parallel receiver cannot take into account both the dynamics of signal reception and the coverage of signal frequency band and has a high noise coefficient, and provides a multi-channel parallel receiver and a device. The multi-channel parallel receiver can take into account both the dynamics of signal reception and the coverage of signal frequency band and has a low noise coefficient.

[0006] The primary purpose of the present invention is to solve the above technical problems. The technical solution of the present invention is as follows: A multi-channel parallel receiver, comprising: a frequency hopping multiplexer, N automatic gain control amplification paths, N×M power synthesis modules, M analog-to-digital conversion units, and a baseband processing unit; The frequency hopping multiplexer receives N input signals, separates the N input signals into N output signals, and suppresses out-of-band input signals; the operating frequency band of the frequency hopping multiplexer is divided into at least 2N bands; Each output signal of the frequency hopping multiplexer is input to each automatic gain control amplification path respectively, and the gain is automatically adjusted in the automatic gain control amplification path; After each automatic gain control amplification path outputs the output signal, the frequency band of the output signal is integrated in the N×M power synthesizers; The output signals after frequency band integration enter M analog-to-digital conversion units respectively. Each analog-to-digital conversion unit samples the output signal within the frequency band according to the set sampling frequency. The sampled output signals are demodulated by the baseband processing unit.

[0007] Furthermore, the isolation between adjacent frequency bands in the at least 2N divided frequency bands is greater than a set value.

[0008] Furthermore, the frequency hopping multiplexer comprises: a phase shifter unit, N inductor-capacitor matching circuits and N sets of filters; The phase shifter unit includes a first phase shifter group and a second phase shifter group, the first phase shifter group includes N first phase shifters, the second phase shifter group includes N second phase shifters, the input end of the first first phase shifter and the input end of the first second phase shifter are both connected to the input signal, the output end of the i-th first phase shifter is respectively connected to the input end of the i+1-th first phase shifter and the input end of the i+1-th second phase shifter; the output end of the N-th first phase shifter is grounded; the output end of the i-th second phase shifter is connected to the input end of the i-th inductor and capacitor matching circuit, the output end of the i-th inductor and capacitor matching circuit is connected to one end of the i-th group of filters, and the other end of the i-th group of filters outputs the output signal, i=1,2,3,…,N.

[0009] Furthermore, the phase shifter in the phase shifter unit is any one of a microstrip line, a stripline, a coaxial line, or an inductor-capacitor phase shifting circuit.

[0010] Furthermore, the LC matching circuit includes: a π-type matching circuit and a T-type matching circuit composed of at least one capacitor and at least one inductor.

[0011] Furthermore, each of the N groups of filters includes at least two filters, and the filters are switched by a radio frequency switch.

[0012] Furthermore, the frequency band of the filter group completely covers the working frequency band of the multi-channel parallel receiver, and the bandwidth of each filter is equal to the bandwidth of the multi-channel parallel receiver in relative bandwidth or absolute bandwidth.

[0013] Furthermore, the analog-to-digital conversion unit adopts a direct radio frequency sampling method, and the sampling frequency of each analog-to-digital conversion unit is greater than 2.5 times the frequency band width of the output signal of the corresponding power synthesis module.

[0014] Furthermore, the baseband processing unit includes a DSP module, an FPGA module, a memory, and a GPP module.

[0015] A multi-channel parallel receiving device comprises a multi-channel parallel receiver.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention sets a frequency hopping multiplexer, and the working frequency band of the frequency hopping multiplexer is divided into at least twice the number of input signal paths, so that the multi-path parallel receiver can effectively separate the multi-path input signals within the frequency band. At the same time, the input signals are respectively input into the automatic gain control amplification path through the frequency hopping multiplexer, and the output signals of the automatic gain control amplification path are integrated, sampled, and demodulated to obtain the final signal, taking into account the signal reception dynamics and signal frequency band coverage; while ensuring the noise coefficient of the receiver, it can achieve high dynamic seamless reception of wide-band signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a structural diagram of a multi-channel parallel receiver provided in Example 1.

[0018] Figure 2 This is a structural diagram of the frequency hopping multiplexer provided in Example 1.

[0019] Figure 3 This is a structural diagram of the inductor and capacitor matching unit provided in Example 3.

[0020] Figure 4 This is a structural diagram of the inductor and capacitor matching unit provided in Example 3.

[0021] Figure 5 This is a structural diagram of the inductor and capacitor matching unit provided in Example 3.

[0022] Figure 6 This is a structural diagram of the inductor and capacitor matching unit provided in Example 3. DETAILED DESCRIPTION

[0023] The drawings are for illustrative purposes only and should not be construed as limiting the present patent; In order to better illustrate the present embodiment, some parts in the drawings may be omitted, enlarged or reduced, and do not represent the size of the actual product; It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0024] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0025] Example 1 like Figure 1As shown, a multi-channel parallel receiver includes: a frequency hopping multiplexer 1, N automatic gain control amplification paths 2, N×M power synthesis modules, M analog-to-digital conversion units, and a baseband processing unit 3; The frequency hopping multiplexer 1 receives N input signals, separates the N input signals into N output signals, and suppresses out-of-band input signals; the operating frequency band of the frequency hopping multiplexer 1 is divided into at least 2N bands; Each output signal of the frequency hopping multiplexer 1 is input to each automatic gain amplification path 2 respectively, and the gain is automatically adjusted in the automatic gain control amplification path 2; After each automatic gain control amplification path 2 outputs the output signal, the frequency band of the output signal is integrated in the N×M power synthesizer; The output signal after frequency band integration enters M analog-to-digital conversion units respectively, and each analog-to-digital conversion unit samples the output signal within the frequency band according to the set sampling frequency. The sampled output signal is demodulated by the baseband processing unit 3.

[0026] It should be noted that, compared with the frequency modulation multiplexer in the prior art, the frequency hopping multiplexer 1 has a wider frequency band coverage and more multiplexing paths.

[0027] Furthermore, the isolation between adjacent frequency bands in the at least 2N divided frequency bands is greater than a set value, and the set value mentioned here is a sufficiently large isolation value.

[0028] Furthermore, if Figure 2 As shown, the frequency hopping multiplexer 1 includes: a phase shifter unit, N inductor and capacitor matching circuits and N sets of filters; The phase shifter unit includes a first phase shifter group and a second phase shifter group, the first phase shifter group includes N first phase shifters, the second phase shifter group includes N second phase shifters, the input end of the first first phase shifter and the input end of the first second phase shifter are both connected to the input signal, the output end of the i-th first phase shifter is respectively connected to the input end of the i+1-th first phase shifter and the input end of the i+1-th second phase shifter; the output end of the N-th first phase shifter is grounded; the output end of the i-th second phase shifter is connected to the input end of the i-th inductor and capacitor matching circuit, the output end of the i-th inductor and capacitor matching circuit is connected to one end of the i-th group of filters, and the other end of the i-th group of filters outputs the output signal, i=1,2,3,…,N.

[0029] In a specific embodiment, the output frequency bands of the filter bank are arranged from small to large according to the serial number i.

[0030] It should be noted that the first phase shifter group makes the impedance from each filter branch to the grounding point the largest, that is, the phase is 90 degrees. The second phase shifter group is used for the ith filter group, and the impedance of other frequency bands is the largest.

[0031] It should be noted that the frequency hopping multiplexer 1 is realized by using a filter switched by a phase shifter and a radio frequency switch, so that the insertion loss of the multi-channel parallel receiver is small and full-band frequency hopping is supported.

[0032] Furthermore, the phase shifter in the phase shifter unit is any one of a microstrip line, a stripline, a coaxial line, or an inductor-capacitor phase shifting circuit.

[0033] Furthermore, the LC matching circuit includes: a π-type matching circuit and a T-type matching circuit composed of at least one capacitor and at least one inductor.

[0034] Furthermore, each of the N groups of filters includes at least two filters, and the filters are switched by a radio frequency switch.

[0035] Furthermore, the frequency band of the filter group completely covers the working frequency band of the multi-channel parallel receiver, and the bandwidth of each filter is equal to the bandwidth of the multi-channel parallel receiver in relative bandwidth or absolute bandwidth.

[0036] Furthermore, the analog-to-digital conversion unit adopts a direct radio frequency sampling method, and the sampling frequency of each analog-to-digital conversion unit is greater than 2.5 times the frequency band width of the output signal of the corresponding power synthesis module.

[0037] Furthermore, the baseband processing unit includes a DSP module, an FPGA module, a memory, and a GPP module.

[0038] It should be noted that the principle of achieving high dynamics of the multi-channel parallel receiver is, on the one hand, that the frequency hopping multiplexer 1 filters and suppresses out-of-band signals, and on the other hand, that the automatic gain control amplification path 2 is used to control in-band signals.

[0039] Example 2 A multi-channel parallel receiving device, a multi-channel parallel receiver proposed in embodiment 1 is applied to the device, comprising: a multi-channel parallel receiver.

[0040] The parallel receiver may include necessary components such as a housing and a signal processing unit, and may also be combined with a communication base station, etc., as a multi-channel parallel receiving device suitable for a communication base station.

[0041] Example 3 Based on the multi-channel parallel receiver described in Example 1, that is, this embodiment adopts the same multi-channel parallel receiver as Example 1.

[0042] like Figure 3 As shown, the inductor-capacitor matching unit includes a first inductor, a second inductor, and a first capacitor; One end of the first inductor is connected to one end of the first capacitor and the output end of the second phase shifter, the other end of the first capacitor is connected to one end of the second inductor and the input end of the RF switch, and the other end of the first inductor and the other end of the second inductor are grounded.

[0043] like Figure 4 As shown, the inductor-capacitor matching unit includes: a third inductor, a second capacitor, and a third capacitor; One end of the third inductor is connected to one end of the second capacitor and the output end of the second phase shifter, the other end of the third inductor is connected to one end of the third capacitor and the input end of the RF switch, and the other end of the second capacitor and the other end of the third capacitor are grounded.

[0044] like Figure 5 As shown, the inductor-capacitor matching unit includes: a fourth capacitor, a fifth capacitor, and a fourth inductor; One end of the fourth capacitor is connected to the output end of the second phase shifter, the other end of the fourth capacitor is connected to one end of the fourth inductor and one end of the fifth capacitor, the other end of the fourth inductor is grounded, and the other end of the fifth capacitor is connected to the input end of the RF switch.

[0045] like Figure 6 As shown, it is characterized in that the inductor-capacitor matching unit includes: a fifth inductor, a sixth inductor, and a sixth capacitor; One end of the fifth inductor is connected to the output end of the second phase shifter, the other end of the fifth inductor is connected to one end of the sixth inductor and one end of the sixth capacitor, the other end of the sixth capacitor is grounded, and the other end of the sixth inductor is connected to the input end of the RF switch.

[0046] A method for designing a frequency hopping multiplexer, the method for designing a multi-channel parallel receiver proposed in Embodiment 1, comprising: S1: Determine the number of filter groups according to the number of parallel receiving paths; S2: Determine the number and bandwidth of filters according to the frequency interval; S3: Determine the filter isolation according to the dynamic reception requirements; S4: Determine the parameters of each phase shifter of 2N according to the frequency of each filter segment; S5: Determine the parameters of the final phase shifter and the specific values ​​of the LC matching network through simulation optimization.

[0047] It should be noted that adjacent frequency bands require a certain degree of isolation to avoid mixing of adjacent signals, but if the isolation is set too high, the filter will be easily damaged.

[0048] In this embodiment, the operating frequency band of the 10-channel parallel receiver is 1300~1700MHz; the signal interval is 40MHz; the maximum receiving signal range is 10dBm, the sensitivity is -100dBm; the ADC sampling rate is up to 800Msps; the ADC demodulation range is -70dBm~+5dBm; the ADC demodulation signal-to-noise ratio is 5dB (QPSK signal with a bandwidth of 1MHz); According to the above conditions, the steps of designing the frequency hopping multiplexer are as follows: For the receiving path, the frequency hopping multiplexer contains 10 filter banks.

[0049] According to the frequency interval requirements, each filter group contains 2 filters, a total of 20. The 1300~1700MHz frequency band is evenly divided into 20 segments, and each filter covers a 20MHz segment.

[0050] In view of the reception signal range requirements and ADC dynamic range, the isolation between adjacent frequency bands of the frequency hopping multiplexer shall not be less than 40dB.

[0051] According to the maximum received signal amplitude, operating frequency band and isolation requirements, the filter adopts a surface acoustic wave filter; the phase shifter is implemented using a microstrip line; and the maximum insertion loss of the frequency hopping multiplexer is expected to be 5.5dB.

[0052] According to the receiver working bandwidth requirements and ADC sampling rate, the ADC adopts two parallel channels, covering the 1300~1500MHz frequency band and the 1500~1700MHz frequency band respectively.

[0053] The power synthesis module realizes 10 inputs and 2 outputs, with an overall insertion loss of 7.5dB.

[0054] According to the receiving dynamics of the analog-to-digital conversion unit and the insertion loss of the multiplexer and power synthesis module, the automatic gain control amplification path 2 gain range is +8dB~﹢48dB, and the noise figure does not exceed 2.5dB.

[0055] The same or similar reference numerals correspond to the same or similar components; The terms used in the drawings to describe positional relationships are only used for illustrative purposes and should not be construed as limiting this patent; Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A multi-channel parallel receiver, characterized in that: include: A frequency hopping multiplexer (1), N automatic gain control amplification paths (2), an N×M power synthesis module, M analog-to-digital conversion units, and a baseband processing unit (3); The frequency hopping multiplexer (1) receives N input signals, separates the N input signals into N output signals, and suppresses out-of-band input signals; The operating frequency band of the frequency hopping multiplexer (1) is divided into at least 2N bands; Each output signal of the frequency hopping multiplexer (1) is input into each automatic gain control amplification path (2) respectively, and the gain is automatically adjusted in the automatic gain control amplification path (2); After each automatic gain control amplification path (2) outputs the output signal, the frequency band of the output signal is integrated in the N×M power synthesizer; The output signals after frequency band integration enter M analog-to-digital conversion units respectively. Each analog-to-digital conversion unit samples the output signal within the frequency band according to a set sampling frequency. The sampled output signals are demodulated by a baseband processing unit (3).

2. A multi-channel parallel receiver according to claim 1, characterized in that: The isolation between adjacent frequency bands in at least 2N divided frequency bands is greater than a set value.

3. A multi-channel parallel receiver according to claim 1, characterized in that: The frequency hopping multiplexer (1) comprises: a phase shifter unit, N inductor and capacitor matching circuits and N sets of filters; The phase shifter unit includes a first phase shifter group and a second phase shifter group, the first phase shifter group includes N first phase shifters, the second phase shifter group includes N second phase shifters, the input end of the first first phase shifter and the input end of the first second phase shifter are both connected to the input signal, the output end of the i-th first phase shifter is respectively connected to the input end of the i+1-th first phase shifter and the input end of the i+1-th second phase shifter; the output end of the N-th first phase shifter is grounded; the output end of the i-th second phase shifter is connected to the input end of the i-th inductor and capacitor matching circuit, the output end of the i-th inductor and capacitor matching circuit is connected to one end of the i-th group of filters, and the other end of the i-th group of filters outputs the output signal, i=1,2,3,…,N.

4. A multi-channel parallel receiver according to claim 3, characterized in that: The phase shifter in the phase shifter unit is any one of a microstrip line, a stripline, a coaxial line, or an inductor-capacitor phase shifting circuit.

5. A multi-channel parallel receiver according to claim 3, characterized in that: The inductor-capacitor matching circuit includes: a π-type matching circuit and a T-type matching circuit composed of at least one capacitor and at least one inductor.

6. A multi-channel parallel receiver according to claim 3, characterized in that: Each filter group in the N filter groups includes at least two filters, and the filters are switched by a radio frequency switch.

7. A multi-channel parallel receiver according to claim 6, characterized in that: The frequency band of the filter group completely covers the working frequency band of the multi-channel parallel receiver, and the bandwidth of each filter is equal to the bandwidth of the multi-channel parallel receiver in relative bandwidth or absolute bandwidth.

8. A multi-channel parallel receiver according to claim 1, characterized in that: The analog-to-digital conversion unit adopts a direct radio frequency sampling method, and the sampling frequency of each analog-to-digital conversion unit is greater than 2.5 times the frequency band width of the output signal of the corresponding power synthesis module.

9. A multi-channel parallel receiver according to claim 1, characterized in that: The baseband processing unit (3) comprises a DSP module, an FPGA module, a memory, and a GPP module.

10. A multi-channel parallel receiving device, characterized in that: It comprises the multi-channel parallel receiver as described in any one of claims 1 to 9.

Images