Semiconductor structure, manufacturing method thereof and memory system

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a storage system. The method for manufacturing the semiconductor structure comprises the following steps of: forming a laminated structure, wherein the laminated structure comprises dielectric layers and sacrificial layers which are alternately stacked; a first initial connecting part extending in the stacking direction of the laminated structure and a second initial connecting part connected with the first initial connecting part and arranged around the first initial connecting part are formed, the second initial connecting part is connected with the sacrificial layer in the first direction, and the first direction intersects with the stacking direction; and replacing the first initial connection part, the second initial connection part and the sacrificial layer with a first connection part, a second connection part and a gate layer respectively.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for manufacturing the semiconductor structure, and a storage system. Background Art

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices, and cloud storage, the requirements for the storage density of semiconductor structures such as three-dimensional semiconductor memory devices are becoming increasingly higher. However, with the increase in the number of stacked layers in the semiconductor structure and the increase in the storage density per unit area, the process steps in the preparation of the three-dimensional semiconductor structure become complicated and lengthy. Therefore, how to simplify the preparation process of the semiconductor structure while taking into account the reliability and overall performance of the semiconductor structure is one of the problems that need to be solved urgently. Summary of the invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0004] The present application provides a method for manufacturing a semiconductor structure. The method includes: forming a stacked structure, the stacked structure including alternately stacked dielectric layers and sacrificial layers; forming a first initial connection portion extending along the stacking direction of the stacked structure, and a second initial connection portion connected to the first initial connection portion and arranged around the first initial connection portion, wherein the second initial connection portion is connected to the sacrificial layer at a preset height along a first direction, and the first direction intersects the stacking direction; and replacing the first initial connection portion, the second initial connection portion, and the sacrificial layer with a first connection portion, a second connection portion, and a gate layer, respectively.

[0005] In one embodiment, the method further includes: forming an isolation portion connected to the first initial connection portion and disposed around the first initial connection portion, wherein the isolation portion is connected to the sacrificial layer at a non-preset height along the first direction.

[0006] In one embodiment, the method includes: forming a first initial lead-out hole of the sacrificial layer extending along the stacking direction to the preset height; removing a portion of the sacrificial layer at the preset height through the first initial lead-out hole to form a first gap; and forming the second initial connection portion in the first gap.

[0007] In one embodiment, the isolation portion includes a first isolation portion located on a first side of the second initial connection portion along the stacking direction, forming a first initial lead-out hole extending along the stacking direction to the sacrificial layer at the preset height, including: forming a second initial lead-out hole extending along the stacking direction to the dielectric layer adjacent to the sacrificial layer at the preset height; removing a portion of the sacrificial layer exposed by the second initial lead-out hole to form a second gap; forming a first isolation portion in the second gap; and extending the second initial lead-out hole along the stacking direction to the sacrificial layer at the preset height to form the first initial lead-out hole.

[0008] In one embodiment, the stacked structure is located on a surface of a substrate, and the method includes: extending the first initial lead-out hole to the substrate along the stacking direction to form a lead-out hole; forming an isolation layer on the side wall of the lead-out hole extending to the substrate; and forming the first initial connection portion in the remaining space of the lead-out hole.

[0009] In one embodiment, the isolation portion includes a second isolation portion located on a second side of the second initial connection portion along the stacking direction and opposite to the first side, and the method includes: removing a portion of the sacrificial layer exposed by the lead-out hole to form a third gap; and forming a second isolation portion in the third gap.

[0010] In one embodiment, at least a portion of the first initial connection portion, the second initial connection portion, and the sacrificial layer are replaced with a first connection portion, a second connection portion, and a gate layer, respectively, including: removing the first initial connection portion, the second initial connection portion, and the sacrificial layer to form a sacrificial gap; forming a blocking layer on the inner wall of the sacrificial gap; and forming the first connection portion, the second connection portion, and the gate layer, respectively, in the remaining space of the sacrificial gap.

[0011] In one embodiment, the method further includes: forming a channel structure penetrating the stacked structure.

[0012] In one embodiment, the method further includes: forming a gate line gap penetrating the stacked structure and extending along the first direction, wherein the second initial connection portion and the sacrificial layer are removed through the gate line gap; and forming a gate line gap structure in the gate line gap.

[0013] On the other hand, the present application provides a semiconductor structure. The semiconductor structure includes: a substrate; a stacked structure located on the surface of the substrate, including alternately stacked dielectric layers and gate layers; and a lead-out structure that penetrates the stacked structure along the stacking direction of the stacked structure and extends to the substrate, wherein the lead-out structure includes a first connecting portion extending along the stacking direction, and the first connecting portion is in direct contact with the gate layer at a preset height.

[0014] In one embodiment, the semiconductor structure further includes: an isolation portion located between the first connection portion and the gate layer at a non-preset height.

[0015] In one embodiment, the materials of the first connection portion and the gate layer both include conductive materials; and the materials of the isolation portion and the dielectric layer both include insulating materials.

[0016] In one embodiment, the semiconductor structure further includes: a blocking layer located between the dielectric layer and the gate layer.

[0017] In one embodiment, the semiconductor structure further includes: a channel structure penetrating the stacked structure; and a gate line gap structure penetrating the stacked structure and extending along a first direction, wherein the first direction intersects with the stacking direction.

[0018] In one embodiment, the first connection portion extends along the stacking direction, and the lead-out structure further includes: a first initial connection portion connected to the first connection portion and extending along the stacking direction to the substrate.

[0019] In one embodiment, the semiconductor structure further includes: an isolation layer located between the first initial connection portion and the substrate.

[0020] On the other hand, the present application provides a storage system, which includes at least one three-dimensional memory, each three-dimensional memory including the semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the three-dimensional memory to store data.

[0021] In one or more embodiments of the present application, by replacing the first initial connection part, the second initial connection part and the sacrificial layer with the first connection part, the second connection part and the gate layer respectively, it is possible to simultaneously form the connected first connection part, the second connection part and the gate layer in one process step, which is beneficial to reduce the process steps and save costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Other features, purposes and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0023] Figure 1 is a flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0024] Figure 2 is a schematic structural diagram of a stacked structure according to an exemplary embodiment of the present application;

[0025] Figure 3 and Figure 4 They are partial structural schematic diagrams of the second initial lead-out hole on a plane formed by the first direction and the stacking direction and a plane formed by the second direction and the stacking direction according to an exemplary embodiment of the present application;

[0026] Figure 5 and Figure 6 They are partial structural schematic diagrams of a second gap on a plane formed by a first direction and a stacking direction and a plane formed by a second direction and a stacking direction according to an exemplary embodiment of the present application;

[0027] Figure 7 and Figure 8 Partial structural schematic diagrams of a first initial lead-out hole and a first isolation portion on a plane formed by a first direction and a stacking direction and a plane formed by a second direction and a stacking direction according to an exemplary embodiment of the present application;

[0028] Fig. 9 and Fig.10 They are partial structural schematic diagrams of a first gap on a plane formed by a first direction and a stacking direction and a plane formed by a second direction and a stacking direction according to an exemplary embodiment of the present application;

[0029] Fig.11 and Fig.12 They are partial structural schematic diagrams of the second initial connection portion according to an exemplary embodiment of the present application on a plane formed by the first direction and the stacking direction and on a plane formed by the second direction and the stacking direction;

[0030] Fig.13 and Fig.14 They are partial structural schematic diagrams of the lead-out hole on a plane formed by the first direction and the stacking direction and a plane formed by the second direction and the stacking direction according to an exemplary embodiment of the present application;

[0031] Fig.15 and Fig.16 Partial structural schematic diagrams of a third gap on a plane formed by a first direction and a stacking direction and a plane formed by a second direction and a stacking direction according to an exemplary embodiment of the present application;

[0032] Fig.17 and Fig.18Partial structural schematic diagrams of a second isolation portion according to an exemplary embodiment of the present application on a plane formed by a first direction and a stacking direction and a plane formed by a second direction and a stacking direction, respectively;

[0033] Fig.19 and Fig. 20 Partial structural schematic diagrams of an isolation layer on a plane formed by a first direction and a stacking direction and a plane formed by a second direction and a stacking direction according to an exemplary embodiment of the present application;

[0034] Fig.21 and Fig. 22 They are partial structural schematic diagrams of a first initial connection portion according to an exemplary embodiment of the present application on a plane formed by a first direction and a stacking direction and a plane formed by a second direction and a stacking direction;

[0035] Fig.23 and Fig.24 They are partial structural schematic diagrams of a semiconductor structure after forming a channel structure according to an exemplary embodiment of the present application on a plane formed by a first direction and a stacking direction and a plane formed by a second direction and a stacking direction;

[0036] Fig.25 and Fig.26 They are partial structural schematic diagrams of a semiconductor structure after forming gate line gaps and sacrificial gaps according to an exemplary embodiment of the present application on a plane formed by a first direction and a stacking direction and a plane formed by a second direction and a stacking direction;

[0037] Figure 27 to Figure 29 Partial structural schematic diagrams of the semiconductor structure after forming the first connection portion, the second connection portion, the gate layer, the barrier layer and the gate line gap structure on the plane formed by the first direction and the stacking direction, the plane formed by the second direction and the stacking direction, and the plane formed by the first direction and the second direction, respectively, according to an exemplary embodiment of the present application;

[0038] Fig.30 is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present application; and

[0039] Fig.31A and Fig.31B is a schematic diagram of a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way.

[0041] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first connection part discussed in this application may also be referred to as the second connection part, and vice versa.

[0042] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0043] In addition, in this document, when describing that one part is located "on" another part, for example, the meaning of "on", "above" and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" does not absolutely mean being above based on the direction of gravity, nor does it only mean the meaning of "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0044] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0045] This document is described with reference to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but include various equivalent structures that can achieve the same functions and shape and size deviations caused by, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0047] As used in this article, the term "layer" refers to a material portion including an area with a height. A layer can be an area of ​​a uniform or non-uniform continuous structure, whose height is less than the height of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it and / or below it. A layer can include multiple layers.

[0048] In addition, in the present application, when “connected” or “coupled” is used, it may indicate that the corresponding components are in direct contact or indirect contact, unless otherwise clearly defined or can be inferred from the context.

[0049] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0050] Figure 1 is a flow chart of a method 1000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0051] like Figure 1 As shown, the method 1000 for manufacturing a semiconductor structure may include: S1100, forming a stacked structure, the stacked structure including alternately stacked dielectric layers and sacrificial layers; S1200, forming a first initial connection portion extending along the stacking direction of the stacked structure, and a second initial connection portion connected to the first initial connection portion and arranged around the first initial connection portion, wherein the second initial connection portion is connected to the sacrificial layer at a preset height along a first direction, and the first direction intersects the stacking direction; and S1300, replacing the first initial connection portion, the second initial connection portion, and the sacrificial layer with the first connection portion, the second connection portion, and the gate layer, respectively. Steps S1100 to S1300 will be described in detail below.

[0052] In the exemplary embodiment of the present application, Figure 2As shown, a stacked structure 1100 may be formed, wherein the stacked structure 1100 may include alternately stacked dielectric layers 1110 and sacrificial layers 1120. The dielectric layers 1110 and sacrificial layers 1120 may extend in a first direction X and a second direction Y, and may be alternately arranged in a stacking direction Z of the stacked structure 1100.

[0053] For example, the dielectric layer 1110 and the sacrificial layer 1120 may be sequentially stacked by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the stacked structure 1100. It should be understood that the number and thickness of the dielectric layer 1110 and the sacrificial layer 1120 are not limited to Figure 2 The number and thickness shown in the figure, without departing from the concept of the present application, those skilled in the art can set any number and thickness of dielectric layer 1110 and sacrificial layer 1120 as needed. In addition, the materials of dielectric layer 1110 and sacrificial layer 1120 can be selected from suitable materials known in the art, for example, the material of dielectric layer 1110 can include oxide such as silicon oxide, and the material of sacrificial layer 1120 can include nitride such as silicon nitride.

[0054] The preparation method of a single stacked structure is described above. As the storage capacity demand of the semiconductor structure continues to increase, the storage stack gradually increases. In the present application, a double stacking technology or a multi-stack technology can also be used to form a stacked structure by stacking multiple sub-stacked structures sequentially in the direction of the thickness of the stacked structure, wherein each sub-stacked structure may include a plurality of dielectric layers and sacrificial layers that are alternately stacked. The number of layers of each sub-stacked structure may be the same or different. Since the content and structure involved in the preparation process of the single stacked structure described above can be fully or partially applied to the stacked structure formed by multiple sub-stacked structures described here, the content related or similar thereto will not be repeated. However, it can be understood by those skilled in the art that the subsequent preparation process can be carried out on the basis of a multi-stacked structure or a single stacked structure.

[0055] For example, Figure 2As shown, a stacked structure 1100 can be formed on a substrate 100. The substrate 100 can be used to support the stacked structure 1100 thereon, and can be removed in a subsequent process. The material of the substrate 100 includes at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The substrate 100 can be a single-layer structure such as a silicon substrate, a germanium substrate, or a silicon germanium substrate, or a multi-layer structure such as a polycrystalline silicon layer, an oxide layer, and a metal silicon layer. Exemplarily, a plurality of layers prepared from different materials can be sequentially arranged by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the substrate 100.

[0056] In the exemplary embodiment of the present application, Fig.21 and Fig. 22 As shown, a first initial connection portion 1210 extending along the stacking direction Z of the stacked structure 1100 and a second initial connection portion 1310 connected to the first initial connection portion 1210 and disposed around the first initial connection portion 1210 may be formed. Exemplarily, the second initial connection portion 1310 may be connected to the sacrificial layer 1120 at a preset height along the first direction X, and the first direction X intersects the stacking direction Z.

[0057] In the exemplary embodiment of the present application, Fig.21 and Fig. 22 As shown, an isolation portion 1400 connected to the first initial connection portion 1210 and disposed around the first initial connection portion 1210 may also be formed. Exemplarily, the isolation portion 1400 may be connected to the sacrificial layer 1120 at a non-preset height along the first direction X. The isolation portion 1400 may include a first isolation portion 1410 and a second isolation portion 1420. The first isolation portion 1410 may be located at a first side of the second initial connection portion 1310 along the stacking direction Z. The second isolation portion 1420 may be located at a second side of the second initial connection portion 1310 opposite to the first side along the stacking direction Z.

[0058] Figures 3 to 22 1 is a process step diagram for forming a first initial connection portion 1210 and a second initial connection portion 1310 according to an exemplary embodiment of the present application.

[0059] Figure 7 and Figure 8 They are partial structural schematic diagrams of the semiconductor structure after forming the first initial lead-out hole 210 and the first isolation portion 1410 according to an exemplary embodiment of the present application on a plane formed by the first direction X and the stacking direction Z and a plane formed by the second direction Y and the stacking direction Z. Figure 7 and Figure 8As shown, a first initial lead-out hole 210 extending along the stacking direction Z to the sacrificial layer 1120 at a preset height may be formed.

[0060] like Figure 7 and Figure 8 As shown, a plurality of first initial lead-out holes 210 extending to the sacrificial layer 1120 at different heights may be formed. In other words, a plurality of first initial lead-out holes 210 may be formed, wherein the plurality of first initial lead-out holes 210 may extend to the sacrificial layer 1120 at different heights, respectively, and the sacrificial layer to which each first initial lead-out hole 210 extends may be a sacrificial layer at a preset height corresponding to the first initial lead-out hole 210. It should be understood that the present application does not specifically limit the number of layers of the sacrificial layer 1120 and the number of the first initial lead-out holes 210, and the number of layers of the sacrificial layer 1120 and the number of the first initial lead-out holes 210 may be adjusted as needed, depending on the size of the semiconductor structure. In order to avoid redundancy, the following will be described by taking the formation of a first initial lead-out hole 210 as an example.

[0061] For example, Figures 3 to 10 1 is a process diagram of forming a first initial lead-out hole 210 according to an exemplary embodiment of the present application.

[0062] Figure 3 and Figure 4 They are partial structural schematic diagrams of the semiconductor structure after the second initial lead-out hole 220 is formed according to an exemplary embodiment of the present application on a plane formed by the first direction X and the stacking direction Z and a plane formed by the second direction Y and the stacking direction Z. For example, Figure 3 and Figure 4 As shown, a second initial lead-out hole 220 extending along the stacking direction Z to the dielectric layer 1110 adjacent to the sacrificial layer 1120 at a predetermined height may be formed.

[0063] By way of example, the second initial extraction hole 220 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, may also be performed. By way of example, the etching depth may be controlled by controlling, for example, the etching time, so as to form a plurality of second initial extraction holes 220 extending to the dielectric layer 1110 at different heights.

[0064] Figure 5 and Figure 6 They are partial structural schematic diagrams of the semiconductor structure after the second gap 320 is formed according to an exemplary embodiment of the present application on a plane formed by the first direction X and the stacking direction Z and a plane formed by the second direction Y and the stacking direction Z. For example, Figure 5 and Figure 6As shown, a portion of the sacrificial layer 1120 exposed by the second initial lead-out hole 220 may be removed to form a second gap 320. For example, the second gap 320 may be formed by, for example, an etch-back process.

[0065] For example, Figure 7 and Figure 8 As shown, a first isolation portion 1410 may be formed in the second gap 320. Specifically, a filling dielectric layer may be formed in the second initial lead-out hole 220 and the second gap 320 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Then, the filling dielectric layer in the second initial lead-out hole 220 and the dielectric layer below the second initial lead-out hole 220 may be removed along the stacking direction Z by, for example, a downward etching process, so as to extend the second initial lead-out hole 220 to the sacrificial layer 1120 at a preset height along the stacking direction Z, thereby forming the first initial lead-out hole 210, wherein the filling dielectric layer in the second gap 320 that is not removed is formed as the first isolation portion 1410.

[0066] Exemplarily, the material of the filling dielectric layer may have a smaller etching selectivity with the material of the dielectric layer 1110, so that a portion of the dielectric layer 1110 may also be removed during the process of removing the filling dielectric layer, thereby allowing the second initial lead-out hole 220 to extend to the sacrificial layer 1120 at a preset height to form the first initial lead-out hole 210. That is, the material of the first isolation portion 1410 may have a smaller etching selectivity with the material of the dielectric layer 1110, for example, the material of the first isolation portion 1410 may include an oxide such as silicon oxide.

[0067] Fig. 9 and Fig.10 They are partial structural schematic diagrams of the semiconductor structure after the first gap 310 is formed according to an exemplary embodiment of the present application on a plane formed by the first direction X and the stacking direction Z and on a plane formed by the second direction Y and the stacking direction Z. For example, Fig. 9 and Fig.10 As shown, a portion of the sacrificial layer 1120 at a preset height may be removed through the first initial lead-out hole 210 to form the first gap 310. Exemplarily, the first gap 310 may be formed by removing a portion of the sacrificial layer 1120 through, for example, an etch-back process.

[0068] Fig.11 and Fig.12 They are partial structural schematic diagrams of the semiconductor structure after forming the second initial connection portion 1310 according to an exemplary embodiment of the present application on a plane formed by the first direction X and the stacking direction Z and a plane formed by the second direction Y and the stacking direction Z. For example, Fig.11 and Fig.12As shown, a second initial connection portion 1310 may be formed in the first gap 310 .

[0069] Specifically, a filling material layer may be formed in the first preliminary lead-out hole 210 and the first gap 310 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Then, the filling material layer in the first preliminary lead-out hole 210 may be removed along the stacking direction Z by, for example, a downward etching process, wherein the filling material layer not removed in the first gap 310 is formed as the second preliminary connection portion 1310.

[0070] For example, the material of the filling material layer (i.e., the material of the second initial connection portion 1310) may have a smaller etching selectivity ratio with the material of the sacrificial layer 1120, so that the second initial connection portion 1310 and the sacrificial layer 1120 can be removed in the same process later. For example, the material of the second initial connection portion 1310 may include at least one of polysilicon, a carbon material, and the like.

[0071] Fig.13 and Fig.14 They are partial structural schematic diagrams of the semiconductor structure after forming the lead-out hole 200 according to an exemplary embodiment of the present application on a plane formed by the first direction X and the stacking direction Z and a plane formed by the second direction Y and the stacking direction Z. For example, Fig.13 and Fig.14 As shown, the first initial lead-out hole 210 may be extended to the substrate 100 along the stacking direction Z to form the lead-out hole 200 .

[0072] For example, the lead-out hole 200 may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, may also be performed. For example, the etching depth may be controlled by controlling, for example, the etching time, so that the lead-out hole 200 extends to the substrate 100.

[0073] Fig.15 and Fig.16 They are partial structural schematic diagrams of the semiconductor structure after the third gap 330 is formed according to an exemplary embodiment of the present application on a plane formed by the first direction X and the stacking direction Z and a plane formed by the second direction Y and the stacking direction Z. For example, Fig.15 and Fig.16 As shown, a portion of the sacrificial layer 1120 exposed by the lead-out hole 200 may be removed to form a third gap 330. For example, the third gap 330 may be formed by, for example, an etch-back process.

[0074] Fig.17 and Fig.1814 and 15 are partial structural schematic diagrams of the semiconductor structure after forming the second isolation portion 1420 according to an exemplary embodiment of the present application on a plane formed by the first direction X and the stacking direction Z and a plane formed by the second direction Y and the stacking direction Z. For example, Fig.17 and Fig.18 As shown, a second isolation portion 1420 may be formed in the third gap 330 .

[0075] Specifically, a filling dielectric layer may be formed in the lead-out hole 200 and the third gap 330 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Then, the filling dielectric layer in the lead-out hole 200 may be removed along the stacking direction Z by, for example, a downward etching process, wherein the filling dielectric layer not removed in the third gap 330 is formed as the second isolation portion 1420.

[0076] For example, the material of the second isolation portion 1420 may be the same as that of the first isolation portion 1410 , and may include an oxide such as silicon oxide. The first isolation portion 1410 and the second isolation portion 1420 may be located at both sides of the second initial connection portion 1310 , respectively.

[0077] Fig.19 and Fig. 20 They are partial structural schematic diagrams of the semiconductor structure after forming the isolation layer 1500 according to an exemplary embodiment of the present application on a plane formed by the first direction X and the stacking direction Z and a plane formed by the second direction Y and the stacking direction Z. For example, Fig.19 and Fig. 20 As shown, an isolation layer 1500 may be formed on the sidewall of the lead-out hole 200 extending to the substrate 100 .

[0078] By way of example, the isolation layer 1500 may be formed by oxidizing a portion of the substrate 100 exposed by the lead-out hole 200 through a thermal oxidation process, so as to form the isolation layer 1500 on the sidewall of the lead-out hole 200 extending to the substrate 100. By way of example, the material of the isolation layer 1500 may include, for example, oxide, so as to electrically insulate the first initial connection portion 1800 subsequently formed in the lead-out hole 200 from the substrate 100.

[0079] Fig.21 and Fig. 22 They are partial structural schematic diagrams of the semiconductor structure after forming the first initial connection portion 1210 according to an exemplary embodiment of the present application on a plane formed by the first direction X and the stacking direction Z and a plane formed by the second direction Y and the stacking direction Z. For example, Fig.21 and Fig. 22 As shown, a first initial connection portion 1210 may be formed in the remaining space of the lead-out hole 200 .

[0080] Exemplarily, the first preliminary connection portion 1210 may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The material of the first preliminary connection portion 1210 may be the same as or similar to the material of the second preliminary connection portion 1310 and may have a smaller etching selectivity ratio with the material of the sacrificial layer 1120, so that the first preliminary connection portion 1210, the second preliminary connection portion 1310, and the sacrificial layer 1120 may be removed in the same process later. For example, the material of the first preliminary connection portion 1210 may include at least one of polysilicon, a carbon material, and the like.

[0081] Fig.23 and Fig.24 They are partial structural schematic diagrams of the semiconductor structure after forming the channel structure 1600 according to an exemplary embodiment of the present application on a plane formed by the first direction X and the stacking direction Z and a plane formed by the second direction Y and the stacking direction Z. For example, Fig.23 As shown, a channel structure 1600 penetrating the stacked structure 1100 may be formed.

[0082] Specifically, a channel hole (not shown) penetrating the stacked structure 1100 may be formed; and a channel structure 1600 may be formed in the channel hole. Exemplarily, the channel hole may be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, may also be performed. The channel hole may have a cylindrical or columnar shape extending in the stacking direction Z in the stacked structure 1100. As an option, the channel hole may extend into the substrate 100.

[0083] A dummy channel structure (not shown) may also be formed during the process of forming the channel structure 1600. It should be understood that the dummy channel structure may have a structure that is the same as or similar to the channel structure 1600, and may play a supporting role, so as to reduce the risk of structural bending of the stacked structure 1100, for example, during the subsequent process of removing the first initial connection portion 1210, the second initial connection portion 1310, and the sacrificial layer 1120, and improve the structural stability of the semiconductor structure.

[0084] Exemplarily, forming the channel structure 1600 in the channel hole may include: sequentially forming a functional layer (not shown) and a channel layer (not shown) from outside to inside in the channel hole; and forming a channel plug (not shown) and a channel filling dielectric layer (not shown).

[0085] The functional layer may include a blocking layer (not shown) formed on the inner wall of the channel hole to block the outflow of charges, a charge trapping layer (not shown) formed on the surface of the blocking layer to store charges during operation of the semiconductor structure, and a tunneling layer (not shown) formed on the surface of the charge trapping layer.

[0086] In some embodiments, the functional layer may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer may have a structure different from the ONO configuration. The channel layer may be formed on the surface of the tunneling layer and can be used to transport the required charges (electrons or holes).

[0087] For example, as an option, according to one embodiment of the present application, a functional layer can be formed on the inner wall and bottom surface of the channel hole, and a channel layer can be formed on the surface of the tunneling layer of the functional layer by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0088] In addition, the channel structure 1600 also includes a channel plug formed at one end of the functional layer away from the substrate 100 (which can be understood as the top of the channel structure 1600). Specifically, after the functional layer and the channel layer are formed, the channel hole can be filled with a channel filling dielectric layer. The channel filling dielectric layer may include an oxidizing dielectric layer, such as silicon oxide. Further, during the filling process, a plurality of insulating gaps can be formed in the channel filling dielectric layer by controlling the channel filling process to reduce structural stress. Then, a channel plug is formed in the portion of the channel filling dielectric layer located at the top of the channel hole. The material of the channel plug can be prepared using the same material as the channel layer, such as N-type doped or P-type doped polysilicon. The channel plug is connected to the channel layer.

[0089] After forming the channel structure 1600 , a dummy channel structure penetrating the stacked structure 1100 may be formed in the same manner as described above, and related or similar contents will not be described in detail herein.

[0090] In addition, as an option, based on the virtual channel structure not having a storage function, generally, in a virtual channel hole (not shown) of the virtual channel structure, only an insulating dielectric material layer such as a silicon oxide layer can be filled by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Similarly, by controlling the channel filling process, a plurality of insulating gaps can be formed in the insulating dielectric material layer to reduce the structural stress of the virtual channel structure.

[0091] In the exemplary embodiment of the present application, Fig. 27 and Fig.28As shown, the first initial connection part 1210 , the second initial connection part 1310 , and the sacrificial layer 1120 may be replaced by the first connection part 1200 , the second connection part 1300 , and the gate layer 1130 , respectively.

[0092] Figure 25 to Figure 28 1 is a process step diagram for forming a first connection portion 1200 , a second connection portion 1300 , and a gate layer 1130 according to an exemplary embodiment of the present application.

[0093] Fig.25 and Fig.26 They are partial structural schematic diagrams of the semiconductor structure after the gate line gap 1710 and the sacrificial gap 300 are formed according to an exemplary embodiment of the present application on a plane formed by the first direction X and the stacking direction Z and a plane formed by the second direction Y and the stacking direction Z. For example, Fig.26 As shown, a gate line gap 1710 penetrating the stacked structure 1100 and extending along the first direction X may be formed.

[0094] The gate line gap 1710 can be used as a passage for providing an etchant. For example, the gate line gap 1710 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes. The gate line gap 1710 can pass through the stacked structure 1100 along the stacking direction Z and extend in the first direction X. As an option, as Fig.26 As shown, the gate line gap 1710 may pass through the stacked layer structure 1100 along the stacking direction Z and extend to the substrate 100 .

[0095] Exemplarily, at least a portion of the first initial connection portion 1210, the second initial connection portion 1310, and the sacrificial layer 1120 may be removed to form the sacrificial gap 300. It should be understood that in the present application, in the process of forming the sacrificial gap 300, the first initial connection portion 1210 may be completely removed, or only a portion of the first initial connection portion 1210 may be removed. The gap formed after removing the first initial connection portion 1210 may be subsequently used to form the first connection portion 1200.

[0096] For example, a portion of the first initial connection portion 1210 is removed. Fig.25 and Fig.26 As shown, a portion of the first initial connection portion 1210, the second initial connection portion 1310, and the sacrificial layer 1120 may be removed to form a sacrificial gap 300. For example, a portion of the first initial connection portion 1210, the second initial connection portion 1310, and the sacrificial layer 1120 may be removed through the gate line gap 1710. It should be understood that a portion of the first initial connection portion 1210, the second initial connection portion 1310, and the sacrificial layer 1120 may also be removed through the surface exposed by the first initial connection portion 1210.

[0097] For example, Fig.25 and Fig.26 As shown, the first initial connection part 1210 connected to the first isolation part 1410 and the second initial connection part 1310 may be removed, and the first initial connection part 1210 connected to the second isolation part 1420 may be retained. In other words, the first initial connection part 1210 located on the first side of the second initial connection part 1310 may be removed, and the first initial connection part 1210 located on the second side of the second initial connection part 1310 may be retained.

[0098] In the present application, by removing the first initial connection portion 1210 located on the first side of the second initial connection portion 1310, the formed sacrificial gap can be connected in the stacking direction Z and the first direction X, so as to facilitate the subsequent formation of the first connection portion 1200, the second connection portion 1300 and the gate layer 1130. In addition, by retaining the first initial connection portion 1210 located on the second side of the second initial connection portion 1310, the retained first initial connection portion 1210 can provide a certain support effect, reduce the risk of bending of the stacked structure 1100 in the process of forming the sacrificial gap 300, and improve the stability of the semiconductor structure. Exemplarily, the etching depth can be controlled by controlling, for example, the etching time to retain part of the first initial connection portion 1210.

[0099] Figure 27 to Figure 29 Schematic diagrams of partial structures of the semiconductor structure on a plane formed by a first direction X and a stacking direction Z, a plane formed by a second direction Y and a stacking direction Z, and a plane formed by the first direction X and the second direction Y after forming a first connecting portion 1200, a second connecting portion 1300, a gate layer 1130, a barrier layer 1800, and a gate line gap structure 1700 according to an exemplary embodiment of the present application. Fig. 27 yes Fig.29 Schematic diagram of a partial cross section along the AA direction, Fig.28 yes Fig.29 Schematic diagram of a partial cross section along direction BB.

[0100] For example, Fig. 27 and Fig.28As shown, a barrier layer 1800 may be formed on the inner wall of the sacrificial gap 300; and a first connection portion 1200, a second connection portion 1300 and a gate layer 1130 may be formed in the remaining space of the sacrificial gap 300, respectively. The first connection portion 1200, the second connection portion 1300 and the gate layer 1130 may be connected to each other. It should be understood that the second connection portion 1300 and the gate layer 1130 may be integrally formed, and the gate layer 1130 may be a portion of the second connection portion 1300 extending along the first direction X. In other words, the second connection portion 1300 may be approximately understood as a portion of the gate layer 1130 extending along the first direction X, or the gate layer 1130 may be approximately understood as a portion of the second connection portion 1300 extending along the first direction X. The first connection portion 1200 may be connected to the gate layer 1130 through the second connection portion 1300.

[0101] Illustratively, the blocking layer 1800, the first connection portion 1200, the second connection portion 1300, and the gate layer 1130 may be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0102] The blocking layer 1800 may be formed of one or more high dielectric constant materials such as hafnium dioxide, lanthanum oxide, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium oxide silicate, silicon oxide, silicon nitride, zirconium dioxide, strontium titanate or zirconium oxide silicate. The blocking layer 1800 may effectively prevent the charges in the gate layer 1130 from diffusing into the dielectric layer 1110. On the other hand, the blocking layer 1800 may increase the dielectric constant between the gate layer 1130 and the dielectric layer 1110, thereby enhancing the control capability of the gate layer 1130.

[0103] The first connection part 1200, the second connection part 1300 and the gate layer 1130 may be formed of one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), etc. The first connection part 1200, the second connection part 1300 and the gate layer 1130 may be formed by the same process, which is conducive to simplifying the process flow of preparing the semiconductor structure and reducing the cost of preparing the semiconductor structure.

[0104] For example, Fig.28 and Fig.29As shown, a gate line gap structure 1700 may be formed in the gate line gap 1710. Specifically, the gate line gap 1710 may be filled to form the gate line gap structure 1700. Specifically, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof may be used to fill a dielectric filling layer in the gate line gap 1710 to form the gate line gap structure 1700. The dielectric filling layer may be made of insulating dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride, or may be made of semiconductor materials such as polysilicon, which is not limited in the present application.

[0105] For example, Fig.29 As shown, the gate line gap structure 1700 may extend from the core region C of the stacked structure 1100 to the connection region D of the stacked structure 1100. The first connection portion 1200 and the second connection portion 1300 may be located in the connection region D. The dummy channel structure 1600' may be located in the connection region D. The channel structure 1600 may be located in the core region C. The external circuit may achieve signal transmission efficiency between the gate layer 1120 and the external circuit via the second connection portion by applying an electrical signal to the first connection structure 1200.

[0106] Figure 27 to Figure 29 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment of the present application. Figure 27 to Figure 29 Schematic diagrams of partial structures of a semiconductor structure according to an exemplary embodiment of the present application on a plane formed by a first direction X and a stacking direction Z, a plane formed by a second direction Y and a stacking direction Z, and a plane formed by the first direction X and the second direction Y. Fig. 27 yes Fig.29 Schematic diagram of a partial cross section along the AA direction, Fig.28 yes Fig.29 Schematic diagram of a partial cross section along direction BB.

[0107] The semiconductor structure may include a substrate 100 , a stacked structure 1100 , and a lead-out structure (including a first connection portion 1200 extending along a stacking direction Z).

[0108] The material of the substrate 100 includes at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. The substrate 100 may be a single-layer structure such as a silicon substrate, a germanium substrate, or a silicon germanium substrate, or a multi-layer structure such as a polycrystalline silicon layer, an oxide layer, and a metal silicon layer. Exemplarily, a plurality of layers made of different materials may be sequentially arranged by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the substrate 100.

[0109] The stacked structure 1100 may be located on a surface of a substrate 100, wherein the substrate 100 may be used to support the stacked structure 1100 thereon. The stacked structure 1100 may include dielectric layers 1110 and gate layers 1130 that are alternately stacked. The dielectric layers 1110 and the gate layers 1130 may extend in a first direction X and a second direction Y, and may be alternately arranged in a stacking direction Z of the stacked structure 1100. It should be understood that the number and thickness of the dielectric layers 1110 and the gate layers 1130 are not limited to Fig. 27 The number and thickness shown in , without departing from the concept of the present application, those skilled in the art can set any number and thickness of dielectric layer 1110 and gate layer 1130 as needed. In addition, the materials of dielectric layer 1110 and gate layer 1130 can be selected from suitable materials known in the art, for example, the material of dielectric layer 1110 can include oxide such as silicon oxide, and the material of gate layer 1130 can include conductive material.

[0110] The lead-out structure may penetrate the stacked structure 1100 along the stacking direction Z of the stacked structure 1100 and extend to the substrate 100. The lead-out structure may include a first connection portion 1200 extending along the stacking direction Z, wherein the first connection portion 1200 may directly contact the gate layer 1130 at a preset height. In other words, the gate layer 1130 may surround the first connection portion 1200, and the first connection portion 1200 may directly contact the gate layer 1130 at a preset height along the first direction X, and the first direction X intersects the stacking direction Z.

[0111] For example, a portion of the gate layer 1130 at a preset height that is in direct contact with the first connection portion 1200 may be regarded as the second connection portion 1300. The second connection portion 1300 may surround the first connection portion 1200. The first connection portion 1200 may be connected to the gate layer 1130 at a preset height through the second connection portion 1300.

[0112] The first connection portion 1200 and the gate layer 1130 may be formed of one or more conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), etc. The first connection portion 1200 and the gate layer 1130 may be formed by the same process, which is conducive to simplifying the process flow of preparing the semiconductor structure and reducing the cost of preparing the semiconductor structure.

[0113] The semiconductor structure provided in the present application may include a plurality of first connection portions 1200. The plurality of first connection portions 1200 may extend to the gate layer 1130 at different heights, respectively, and the gate layer 1130 to which each first connection portion 1200 extends may be the gate layer 1130 at a preset height corresponding to the first connection portion 1200. It should be understood that the present application does not specifically limit the number of layers of the gate layer 1130 and the number of the first connection portions 1200, and the number of layers of the gate layer 1130 and the number of the first connection portions 1200 may be adjusted as needed, depending on the size of the semiconductor structure. In order to avoid redundancy, the following will be described by taking the formation of a first connection portion 1200 as an example.

[0114] The lead-out structure may further include a first initial connection portion 1210. The first initial connection portion 1210 may be connected to the first connection portion 1200 along the stacking direction Z, and the first initial connection portion 1210 may extend to the substrate 100. The material of the first initial connection portion 1210 may include at least one of polysilicon, carbon material, etc. The first initial connection portion 1210 may provide a certain support effect to reduce the risk of bending of the stacked structure 1100 during the formation of the semiconductor structure, thereby improving the stability of the semiconductor structure.

[0115] In an exemplary embodiment of the present application, the semiconductor structure may further include an isolation portion 1400. The isolation portion 1400 may be located between the first connection portion 1200 and the gate layer 1300 at a non-preset height. In other words, the isolation portion 1400 may be connected to the first connection portion 1200 and disposed around the first connection portion 1200, wherein the isolation portion 1400 may be connected to the gate layer 1130 at a non-preset height along the first direction X. Exemplarily, the isolation portion 1400 may include a first isolation portion 1410 and a second isolation portion 1420. The first isolation portion 1410 may be located on a first side of the second connection portion 1300 along the stacking direction Z. The second isolation portion 1420 may be located on a second side of the second connection portion 1300 opposite to the first side along the stacking direction Z. The first isolation portion 1410 and the second isolation portion 1420 may be connected to the first connection portion 1200 and disposed around the first connection portion 1200 , wherein the first isolation portion 1410 and the second isolation portion 1420 may be connected to the gate layer 1130 at a non-preset height along the first direction X.

[0116] The material of the first isolation portion 1410 may have a smaller etching selectivity than the material of the dielectric layer 1110. For example, the material of the first isolation portion 1410 may include an oxide such as silicon oxide. The material of the second isolation portion 1420 may be the same as that of the first isolation portion 1410. For example, it may include an oxide such as silicon oxide.

[0117] In an exemplary embodiment of the present application, the semiconductor structure may further include an isolation layer 1500. The isolation layer 1500 may be located between the first initial connection portion 1210 and the substrate 100, for example, the isolation layer 1500 may be located on the sidewall of the first initial connection portion 1210 extending to the substrate 100. For example, the material of the isolation layer 1500 may include, for example, oxide, so as to electrically insulate the first initial connection portion 1210 from the substrate 100.

[0118] In an exemplary embodiment of the present application, the semiconductor structure may further include a barrier layer 1800. The barrier layer 1800 may be located between the dielectric layer 1100 and the gate layer 1130. For example, the barrier layer 1800 may also be located between the first connection portion 1200 and the isolation portion 1400.

[0119] The blocking layer 1800 may be formed of one or more high dielectric constant materials such as hafnium dioxide, lanthanum oxide, aluminum oxide, tantalum pentoxide, yttrium oxide, hafnium oxide silicate, silicon oxide, silicon nitride, zirconium dioxide, strontium titanate or zirconium oxide silicate. The blocking layer 1800 may effectively prevent the charges in the gate layer 1130 from diffusing into the dielectric layer 1110. On the other hand, the blocking layer 1800 may increase the dielectric constant between the gate layer 1130 and the dielectric layer 1110, thereby enhancing the control capability of the gate layer 1130.

[0120] In an exemplary embodiment of the present application, the semiconductor structure may further include a channel structure 1600 and a dummy channel structure 1600'. The channel structure 1600 and the dummy channel structure 1600' may penetrate the stacked structure 1100. The channel structure 1600 and / or the dummy channel structure 1600' may have a cylindrical or columnar shape extending along the stacking direction Z in the stacked structure 1100. As an option, the channel structure 1600 and / or the dummy channel structure 1600' may extend into the substrate 100.

[0121] It should be understood that the dummy channel structure 1600 ′ can play a supporting role to reduce the risk of structural bending of the stacked structure 1100 during the formation of the first connection portion 1200 , the second connection portion 1300 and the gate layer 1130 , thereby improving the structural stability of the semiconductor structure.

[0122] For example, the channel structure 1600 may sequentially form a functional layer (not shown) and a channel layer (not shown) from the outside to the inside; and form a channel plug (not shown) and a channel filling dielectric layer (not shown). The functional layer may include a blocking layer (not shown) extending along the stacking direction Z to block the outflow of charges, a charge trapping layer (not shown) formed on the surface of the blocking layer to store charges during the operation of the semiconductor structure, and a tunneling layer (not shown) formed on the surface of the charge trapping layer.

[0123] In some embodiments, the functional layer may include an oxide-nitride-oxide (ONO) structure. However, in some other embodiments, the functional layer may have a structure different from the ONO configuration. The channel layer may be formed on the surface of the tunneling layer and can be used to transport the required charges (electrons or holes).

[0124] In addition, the channel structure 1600 also includes a channel plug formed at one end of the functional layer away from the substrate 100 (which can be understood as the top of the channel structure 1600). The material of the channel plug can be made of the same material as the channel layer, such as N-type doped or P-type doped polysilicon. The channel plug is connected to the channel layer.

[0125] In an exemplary embodiment of the present application, the semiconductor structure may further include a gate line gap structure 1700. The gate line gap structure 1700 may penetrate the stacked structure 1100 and extend along the first direction X. The gate line gap structure 1700 may extend from the core region C of the stacked structure 1100 to the connection region D of the stacked structure 1100. The first connection portion 1200 and the second connection portion 1300 may be located in the connection region D. The dummy channel structure 1600' may be located in the connection region D. The channel structure 1600 may be located in the core region C. The external circuit may achieve signal transmission efficiency between the gate layer 1120 and the external circuit via the second connection portion by applying an electrical signal to the first connection structure 1200.

[0126] Since the contents and structures involved in the method 1000 for manufacturing a semiconductor structure described above may be fully or partially applicable to the semiconductor structure described herein, the contents related or similar thereto will not be described in detail herein.

[0127] Although the exemplary structure and method of making the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced or added from the method of making the semiconductor structure. In addition, the illustrated layers and materials thereof are merely exemplary.

[0128] Fig.30 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0129] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having the storage system 12 located therein). Fig.30As shown, the system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0130] The three-dimensional memory 14 may include a semiconductor structure described in any embodiment of the present application. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate function may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol. For example, the controller 16 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0131] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig.31AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Fig.30 The host 18 in the memory card connector 24 is coupled. Fig.31B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Fig.30 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0132] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a stacked structure comprising alternately stacked dielectric layers and sacrificial layers; forming a first initial connection portion extending along a stacking direction of the stacked structure, and a second initial connection portion connected to the first initial connection portion and arranged around the first initial connection portion, wherein the second initial connection portion is connected to the sacrificial layer at a preset height along a first direction intersecting the stacking direction; and The first initial connection portion, the second initial connection portion, and the sacrificial layer are replaced with a first connection portion, a second connection portion, and a gate layer, respectively.

2. The method according to claim 1, characterized in that The method further comprises: An isolation portion connected to the first initial connection portion and disposed around the first initial connection portion is formed, wherein the isolation portion is connected to the sacrificial layer at a non-preset height along the first direction.

3. The method according to claim 2, characterized in that The method comprises: forming a first initial lead-out hole of the sacrificial layer extending along the stacking direction to the preset height; removing a portion of the sacrificial layer at the preset height through the first initial lead-out hole to form a first gap; and The second initial connection portion is formed in the first gap.

4. The method according to claim 3, characterized in that The isolation portion includes a first isolation portion located at a first side of the second initial connection portion along the stacking direction, and forms a first initial lead-out hole of the sacrificial layer extending along the stacking direction to the preset height, including: forming a second initial lead-out hole extending along the stacking direction to the dielectric layer adjacent to the sacrificial layer at the preset height; removing a portion of the sacrificial layer exposed by the second initial lead-out hole to form a second gap; forming a first isolation portion in the second gap; and The second initial lead-out hole is extended along the stacking direction to the sacrificial layer at the preset height to form the first initial lead-out hole.

5. The method according to claim 4, characterized in that The stacked structure is located on a surface of a substrate, and the method comprises: Extending the first initial lead-out hole to the substrate along the stacking direction to form a lead-out hole; forming an isolation layer on a side wall of the lead-out hole extending to the substrate; and The first initial connection portion is formed in the remaining space of the lead-out hole.

6. The method according to claim 5, characterized in that The isolating portion includes a second isolating portion located at a second side of the second initial connecting portion opposite to the first side along the stacking direction, and the method includes: removing a portion of the sacrificial layer exposed by the lead-out hole to form a third gap; A second isolation portion is formed in the third gap.

7. The method according to claim 1, characterized in that Replacing the first initial connection portion, the second initial connection portion, and the sacrificial layer with a first connection portion, a second connection portion, and a gate layer, respectively, comprises: removing at least a portion of the first initial connection portion, the second initial connection portion, and the sacrificial layer to form a sacrificial gap; forming a barrier layer on an inner wall of the sacrificial gap; and The first connection portion, the second connection portion, and the gate layer are respectively formed in remaining spaces of the sacrificial gap.

8. The method according to any one of claims 1 to 7, characterized in that The method further comprises: A channel structure is formed penetrating the stacked structure.

9. The method according to claim 7, characterized in that: The method further comprises: forming a gate line gap penetrating the stacked structure and extending along the first direction, wherein the second initial connection portion and the sacrificial layer are removed through the gate line gap; and A gate line gap structure is formed in the gate line gap.

10. A semiconductor structure, characterized in that: include: substrate; A stacked structure, located on the surface of the substrate, comprising alternately stacked dielectric layers and gate layers; as well as A lead-out structure penetrates the stacked structure along a stacking direction of the stacked structure and extends to the substrate, wherein the lead-out structure includes a first connecting portion extending along the stacking direction, and the first connecting portion directly contacts the gate layer at a preset height.

11. The semiconductor structure according to claim 10, characterized in that: The semiconductor structure further comprises: The isolation portion is located between the first connection portion and the gate layer at a non-preset height.

12. The semiconductor structure according to claim 11, characterized in that: The materials of the first connection portion and the gate layer both include conductive materials; and The materials of the isolation part and the dielectric layer both include insulating materials.

13. The semiconductor structure according to claim 10, characterized in that: The semiconductor structure further comprises: The barrier layer is located between the dielectric layer and the gate layer.

14. The semiconductor structure according to claim 10, characterized in that The semiconductor structure further comprises: a channel structure penetrating the stacked structure; and The gate line gap structure penetrates the stacked structure and extends along a first direction, wherein the first direction intersects with the stacking direction.

15. The semiconductor structure according to claim 10, characterized in that The first connection portion extends along the stacking direction, and the lead-out structure further includes: The first initial connection portion is connected to the first connection portion and extends to the substrate along the stacking direction.

16. The semiconductor structure according to claim 15, characterized in that The semiconductor structure further comprises: An isolation layer is located between the first initial connection portion and the substrate.

17. A storage system, characterized in that: include: At least one three-dimensional memory, each of the three-dimensional memory comprising a semiconductor structure as claimed in any one of claims 10 to 16; as well as The controller is coupled to the semiconductor structure and is used for controlling the three-dimensional memory to store data.

Images