Double ferroelectric enhanced ferroelectric field effect transistor and preparation method and application thereof
By adopting a dual ferroelectric enhanced structural design in the ferroelectric field effect transistor, the mutual coupling between the ferroelectric dielectric layer and the ferroelectric semiconductor channel layer is solved, and the existing ferroelectric field effect transistors are achieved with a longer ferroelectric retention time and higher storage performance.
Patent Information
- Application Number
- CN202411692999.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-25
- Publication Date
- 2025-03-11
AI Technical Summary
Existing ferroelectric field effect transistors have challenges in reliability, durability, retention, and crosstalk problems in arrays, especially ferroelectric oxide-based devices.
The structural design of a dual ferroelectric enhanced ferroelectric field effect transistor is adopted, including a gate layer, a ferrodielectric layer, a buffer layer and a ferroelectric semiconductor channel layer formed on the substrate, and is prepared by laser pulse deposition, atomic layer deposition method and transfer alignment method.
It significantly improves the ferroelectric retention performance, extends the ferroelectric retention time, and has better performance than single ferroelectric field effect transistors, which can maintain efficient storage performance at high temperatures.
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Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of inorganic semiconductor nanomaterials, and specifically relates to a dual ferroelectric enhanced ferroelectric field effect transistor and a preparation method and application thereof. Background Art
[0002] Ferroelectric field-effect transistors (FFETs) have attracted widespread attention for their potential applications in non-volatile memory. These devices use the polarization state of ferroelectric materials to store information and have the advantages of low power consumption, high access speed, high read / write times, and high storage density. However, commercial mass production of FFETs still faces challenges under the current state of the art, especially in terms of reliability, durability, retention, and crosstalk issues in arrays.
[0003] In the early research of ferroelectric field effect transistors, ferroelectric films were directly prepared on silicon substrates to form a metal-ferroelectric-semiconductor structure. However, the long-term charge retention performance of this structure is poor, which limits further performance improvement. In order to improve this problem, researchers introduced an insulating buffer layer between the ferroelectric film and the silicon substrate to form a metal-ferroelectric-insulating-semiconductor structure. This structure can not only prevent the interface reaction and mutual diffusion between the silicon substrate and the ferroelectric film at high temperatures, but also provide a higher potential barrier to reduce the charge injection from the silicon substrate to the ferroelectric film, greatly improving the long-term stability and reliability of the device.
[0004] Nevertheless, the reliability of FFETs remains a challenge, especially those based on ferroelectric oxides, which face reliability issues that affect retention, endurance, and variability.
[0005] In order to further improve the ferroelectric retention performance of ferroelectric field effect transistors, the coupling of ferroelectric dielectric layers and ferroelectric semiconductors in structural design is the key to improving the ferroelectric retention performance. Summary of the invention
[0006] In view of the problems and shortcomings in the prior art, the purpose of the present invention is to provide a dual ferroelectric enhancement mode ferroelectric field effect transistor and a preparation method and application thereof, which can be used as a non-volatile memory device in electronic equipment.
[0007] To achieve the purpose of the invention, the technical solution adopted by the present invention is as follows:
[0008] The first aspect of the present invention provides a dual ferroelectric enhancement mode ferroelectric field effect transistor, comprising: a substrate; a gate layer formed on the substrate; a ferroelectric dielectric layer formed on the gate layer; a buffer layer formed on the ferroelectric dielectric layer; and a ferroelectric semiconductor channel layer formed on the buffer layer.
[0009] Preferably, the material of the ferroelectric dielectric layer is bismuth ferrite, and the thickness of the ferroelectric dielectric layer is 140-160 nm.
[0010] Preferably, the material of the ferroelectric semiconductor channel layer is indium triselenide, and the thickness of the ferroelectric semiconductor channel layer is 45-50 nm.
[0011] Preferably, the dual ferroelectric enhancement mode ferroelectric field effect transistor further comprises a source and a drain formed on the ferroelectric semiconductor channel layer, and the source and the drain are symmetrically formed at two ends of the ferroelectric semiconductor channel layer.
[0012] Preferably, the material of the buffer layer is hafnium-based ferroelectric oxide or aluminum oxide; the thickness of the buffer layer is 10-15 nm.
[0013] More preferably, the material of the buffer layer is hafnium-based ferroelectric oxide; most preferably hafnium dioxide.
[0014] Preferably, the material of the gate layer is strontium ruthenate; and the thickness of the gate layer is 10-20 nm.
[0015] Preferably, the substrate material is strontium titanate; the source electrode is any one of chromium / gold and titanium / gold; and the drain electrode is any one of chromium / gold and titanium / gold.
[0016] The second aspect of the present invention provides a method for preparing the dual ferroelectric enhancement mode ferroelectric field effect transistor as described in the first aspect, comprising the following steps:
[0017] (1) preparing a gate layer on a substrate by laser pulse deposition;
[0018] (2) depositing a dielectric material on the gate layer described in step (1) by laser pulse deposition and performing annealing to prepare a ferroelectric dielectric layer;
[0019] (3) preparing a buffer layer on the ferroelectric dielectric layer described in step (2) by atomic layer deposition;
[0020] (4) Preparing a ferroelectric semiconductor channel layer on the buffer layer described in step (3) by a transfer alignment method.
[0021] Preferably, the method further comprises: preparing a source electrode and a drain electrode on the ferroelectric semiconductor channel layer.
[0022] More preferably, the source and drain are prepared on the ferroelectric semiconductor channel layer by standard electronic book exposure and metal deposition, the source is any one of chromium / gold and titanium / gold, and the drain is any one of chromium / gold and titanium / gold; the order of metal deposition is chromium, gold or titanium, gold; the thickness of the chromium or titanium is preferably 10nm, and the thickness of the gold is preferably 15nm.
[0023] More preferably, the material of the substrate is strontium titanate; the material of the gate layer is strontium ruthenate; the dielectric material is bismuth ferrite; the material of the buffer layer is hafnium-based oxide or aluminum oxide, most preferably hafnium dioxide; and the material of the ferroelectric semiconductor channel layer is indium triselenide.
[0024] More preferably, the annealing treatment is carried out at a temperature of 450° C. and for 10 minutes.
[0025] The third aspect of the present invention further provides an application of the dual ferroelectric enhancement mode ferroelectric field effect transistor described in the first aspect in a ferroelectric memory.
[0026] Compared with the prior art, the present invention has the following beneficial effects:
[0027] 1. The present invention prepares a ferroelectric field effect transistor electronic device based on strontium ruthenate / bismuth ferrite / hafnium dioxide / indium triselenide, wherein strontium ruthenate is used as a gate, bismuth ferrite is used as a ferroelectric dielectric layer, hafnium dioxide is used as a buffer layer, indium triselenide is used as a ferroelectric semiconductor channel, and chromium and gold are used as source and drain electrode materials. The main purpose of the dual ferroelectric field effect transistor prepared by the present invention is to utilize the mutual coupling between the ferroelectric polarization of the channel material indium triselenide and the dielectric material bismuth ferrite to enhance the ferroelectric retention performance of the ferroelectric field effect transistor and improve the non-volatile storage capacity.
[0028] 2. Compared with a single ferroelectric field effect transistor (only the dielectric layer is a ferroelectric material or only the channel material is a ferroelectric material), the dual ferroelectric field effect transistor prepared by the present invention can have a longer ferroelectric retention time. For example, the current values of the high and low resistance states can withstand a 1000-second test, and its performance is significantly better than that of a single ferroelectric field effect transistor (the high and low resistance state retention time is less than 100 seconds). BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 This is a schematic structural diagram of a dual ferroelectric enhancement mode ferroelectric field effect transistor according to Embodiment 1 of the present invention;
[0030] Figure 2 This is an atomic force microscope image of the dual ferroelectric enhancement mode ferroelectric field effect transistor prepared in Example 1 of the present invention;
[0031] Figure 3 The thickness curve of indium triselenide in the dual ferroelectric enhancement mode ferroelectric field effect transistor prepared in Example 1 of the present invention;
[0032] Figure 4 A schematic diagram of the structure of a single ferroelectric molybdenum disulfide field effect transistor prepared in Comparative Example 1 of the present invention;
[0033] Figure 5A schematic diagram of the structure of a single ferroelectric indium selenide field effect transistor prepared in Comparative Example 2 of the present invention;
[0034] Figure 6 The transfer curve diagram of the source-drain current versus gate voltage of the dual ferroelectric enhancement mode ferroelectric field effect transistor prepared in Example 1 of the present invention within different gate voltage scanning ranges;
[0035] Figure 7 The transfer curve diagram of the source-drain current versus gate voltage of the single ferroelectric molybdenum disulfide field effect transistor prepared in Comparative Example 1 of the present invention within different gate voltage scanning ranges;
[0036] Figure 8 The graph of the high and low resistance state currents of the dual ferroelectric field effect transistor of Example 1 at room temperature (25° C.) versus time;
[0037] Fig. 9 It is a graph showing the change of high and low resistance state currents of the dual ferroelectric field effect transistor of Example 1 with time at high temperature (105° C.);
[0038] Fig.10 A comparison diagram of the high and low resistance states of the ferroelectric field effect transistors prepared in Example 1 and Comparative Example 2 changing with time;
[0039] Fig.11 The graph shows the change of the switching ratio of the ferroelectric field effect transistors prepared in Example 1 and Comparative Examples 1-2 over time. DETAILED DESCRIPTION
[0040] The following examples are only for further explanation of the present invention. It should be noted that all technical and scientific terms used in the present invention have the same meanings as in the technical field to which the present invention belongs unless otherwise specified. The experimental methods in the following examples without specifying specific conditions are all based on conventional techniques in the technical field, or according to the conditions recommended by the manufacturer; the reagents or instruments used without specifying the manufacturer are all conventional products that can be purchased commercially.
[0041] In order to enable those skilled in the art to more clearly understand the technical solution of the present invention, the technical solution of the present invention will be described in detail below in conjunction with specific embodiments.
[0042] Example 1
[0043] A dual ferroelectric enhancement type ferroelectric field effect transistor comprises a substrate, a gate layer formed on the substrate, a ferroelectric dielectric layer formed on the gate layer, a buffer layer formed on the ferroelectric dielectric layer, a ferroelectric semiconductor channel layer formed on the buffer layer, a source and a drain formed on the ferroelectric semiconductor channel layer, wherein the source and the drain are symmetrically formed at both ends of the ferroelectric semiconductor channel layer.
[0044] More specifically, the structure of the dual ferroelectric enhancement mode ferroelectric field effect transistor of this embodiment is as follows: Figure 1 As shown, the substrate material is strontium titanate, the gate layer material is strontium ruthenate, the ferroelectric dielectric layer material is bismuth titanate, the buffer layer material is hafnium dioxide, the ferroelectric semiconductor channel layer material is indium triselenide, and the source and drain are chromium / gold.
[0045] This embodiment also provides a method for preparing the above-mentioned dual ferroelectric enhancement mode ferroelectric field effect transistor, comprising the following steps:
[0046] (1) using strontium ruthenate as a target material, a strontium ruthenate conductive film with a thickness of 15 nm is deposited and grown on a strontium titanate substrate by a laser pulse deposition method to form a gate layer;
[0047] (2) using bismuth ferrite as a target material, a 150 nm thick bismuth ferrite film is deposited on the gate layer by laser pulse deposition, and then annealed at 400° C. for 10 min to form a ferroelectric dielectric layer;
[0048] (3) depositing hafnium dioxide with a thickness of 10 nm on the ferroelectric dielectric layer by atomic layer deposition to form a buffer layer;
[0049] (4) peeling the indium triselenide nanosheets onto a polydimethylsiloxane (PDMS) support film for standby use; then fixing the strontium titanate / strontium ruthenate / bismuth ferrite / hafnium dioxide substrate obtained in step (3) on a transfer table, and attaching the PMDS support film carrying indium triselenide to the surface of hafnium dioxide with the help of an optical microscope, then heating the substrate to 50° C. and lifting the PMDS film, and transferring the indium triselenide nanosheets (50 nm thick) to the surface of hafnium dioxide to form a ferroelectric semiconductor channel layer, thereby obtaining a strontium titanate / strontium ruthenate / bismuth ferrite / hafnium dioxide / indium triselenide having a vertical structure;
[0050] (5) Prepare a source electrode and a drain electrode on the ferroelectric semiconductor channel layer formed in step (4) by standard electron beam exposure and metal deposition, and the source electrode and the drain electrode are symmetrically formed at both ends of the ferroelectric semiconductor channel layer. The source electrode and the drain electrode are both chromium / gold, and the order of metal deposition is chromium with a thickness of 10nm and gold with a thickness of 50nm, so as to obtain the dual ferroelectric enhancement mode ferroelectric field effect transistor.
[0051] Figure 2 This is an atomic force microscope image of the dual ferroelectric enhancement mode ferroelectric field effect transistor prepared in Example 1. Figure 3 This is a thickness curve of indium triselenide in the dual ferroelectric enhancement mode ferroelectric field effect transistor prepared in Example 1.
[0052] Example 2
[0053] A dual ferroelectric enhancement type ferroelectric field effect transistor comprises a substrate, a gate layer formed on the substrate, a ferroelectric dielectric layer formed on the gate layer, a buffer layer formed on the ferroelectric dielectric layer, a ferroelectric semiconductor channel layer formed on the buffer layer, a source and a drain formed on the ferroelectric semiconductor channel layer, wherein the source and the drain are symmetrically formed at both ends of the ferroelectric semiconductor channel layer.
[0054] More specifically, the substrate material is strontium titanate, the gate layer material is strontium ruthenate, the ferroelectric dielectric layer material is bismuth titanate, the buffer layer material is aluminum oxide, the ferroelectric semiconductor channel layer material is indium triselenide, and the source and drain are chromium / gold.
[0055] This embodiment also provides a method for preparing the above-mentioned dual ferroelectric enhancement mode ferroelectric field effect transistor, comprising the following steps:
[0056] (1) using strontium ruthenate as a target material, a strontium ruthenate conductive film with a thickness of 10 nm is deposited and grown on a strontium titanate substrate by a laser pulse deposition method to form a gate layer;
[0057] (2) using bismuth ferrite as a target material, a 160 nm thick bismuth ferrite film is deposited on the gate layer by laser pulse deposition, and then annealed at 400° C. for 10 min to form a ferroelectric dielectric layer;
[0058] (3) depositing aluminum oxide with a thickness of 15 nm on the ferroelectric dielectric layer by atomic layer deposition to form a buffer layer;
[0059] (4) peeling the indium triselenide nanosheets onto a polydimethylsiloxane (PDMS) support film for standby use; then fixing the strontium titanate / strontium ruthenate / bismuth ferrite / hafnium dioxide substrate obtained in step (3) on a transfer table, and attaching the PMDS support film carrying indium triselenide to the surface of hafnium dioxide with the help of an optical microscope, then heating the substrate to 50° C. and lifting the PMDS film, and transferring the indium triselenide nanosheets (thickness 48 nm) to the surface of hafnium dioxide to form a ferroelectric semiconductor channel layer, thereby obtaining a strontium titanate / strontium ruthenate / bismuth ferrite / hafnium dioxide / indium triselenide having a vertical structure;
[0060] (5) Prepare a source electrode and a drain electrode on the ferroelectric semiconductor channel layer formed in step (4) by standard electron beam exposure and metal deposition, and the source electrode and the drain electrode are symmetrically formed at both ends of the ferroelectric semiconductor channel layer. The source electrode and the drain electrode are both chromium / gold, and the order of metal deposition is chromium with a thickness of 10nm and gold with a thickness of 50nm, so as to obtain the dual ferroelectric enhancement mode ferroelectric field effect transistor.
[0061] Example 3
[0062] A dual ferroelectric enhancement type ferroelectric field effect transistor comprises a substrate, a gate layer formed on the substrate, a ferroelectric dielectric layer formed on the gate layer, a buffer layer formed on the ferroelectric dielectric layer, a ferroelectric semiconductor channel layer formed on the buffer layer, a source and a drain formed on the ferroelectric semiconductor channel layer, wherein the source and the drain are symmetrically formed at both ends of the ferroelectric semiconductor channel layer.
[0063] The substrate material is strontium titanate, the gate layer material is strontium ruthenate, the ferroelectric dielectric layer material is bismuth titanate, the buffer layer material is hafnium dioxide, the ferroelectric semiconductor channel layer material is indium selenide, and the source and drain are titanium / gold.
[0064] This embodiment also provides a method for preparing the above-mentioned dual ferroelectric enhancement mode ferroelectric field effect transistor, comprising the following steps:
[0065] (1) using strontium ruthenate as a target material, a strontium ruthenate conductive film with a thickness of 12 nm is deposited and grown on a strontium titanate substrate by a laser pulse deposition method to form a gate layer;
[0066] (2) using bismuth ferrite as a target material, a 140 nm thick bismuth ferrite film is deposited on the gate layer by laser pulse deposition, and then annealed at 400° C. for 10 min to form a ferroelectric dielectric layer;
[0067] (3) depositing hafnium dioxide with a thickness of 12 nm on the ferroelectric dielectric layer by atomic layer deposition to form a buffer layer;
[0068] (4) peeling the indium triselenide nanosheets onto a polydimethylsiloxane (PDMS) support film for standby use; then fixing the strontium titanate / strontium ruthenate / bismuth ferrite / hafnium dioxide substrate obtained in step (3) on a transfer table, and attaching the PMDS support film carrying indium triselenide to the surface of hafnium dioxide with the help of an optical microscope, then heating the substrate to 50° C. and lifting the PMDS film, and transferring the indium triselenide nanosheets (thickness of 45 nm) to the surface of hafnium dioxide to form a ferroelectric semiconductor channel layer, thereby obtaining a strontium titanate / strontium ruthenate / bismuth ferrite / hafnium dioxide / indium triselenide having a vertical structure;
[0069] (5) Prepare a source electrode and a drain electrode on the ferroelectric semiconductor channel layer formed in step (4) by standard electron beam exposure and metal deposition, and the source electrode and the drain electrode are symmetrically formed at both ends of the ferroelectric semiconductor channel layer. The source electrode and the drain electrode are both titanium / gold, and the order of metal deposition is titanium with a thickness of 10nm and gold with a thickness of 50nm, so as to obtain the dual ferroelectric enhancement mode ferroelectric field effect transistor.
[0070] Comparative Example 1
[0071] A single ferroelectric molybdenum disulfide field effect transistor, the device structure is as follows Figure 4 As shown, the difference from Example 1 is that the ferroelectric semiconductor channel layer material in Example 1 is replaced by molybdenum disulfide instead of indium triselenide.
[0072] Comparative Example 2
[0073] A single ferroelectric indium selenide field effect transistor, the device structure is as follows Figure 5 As shown, it includes a P-type heavily doped silicon substrate, hafnium dioxide as a ferroelectric dielectric layer, indium triselenide as a semiconductor channel layer and source and drain electrodes.
[0074] Performance Testing
[0075] 1. The transfer curves of the source-drain current and gate voltage of the ferroelectric field effect transistors prepared in Example 1 and Comparative Example 1 are as follows: Figure 6 and Figure 7 shown.
[0076] from Figure 6 and Figure 7 It can be seen that as the gate voltage scanning range increases, the storage window of the dual ferroelectric field effect transistor device prepared in Example 1 also increases, while the leakage current remains basically unchanged. Compared with the device in Example 1, the storage window of the transfer curve of the device obtained in Comparative Example 1 is significantly reduced. The above results show that compared with a single ferroelectric field effect transistor, the dual ferroelectric field effect transistor prepared by the present invention has a significant improvement in storage performance.
[0077] 2. The high and low resistance currents of the dual ferroelectric enhanced field effect transistors prepared in Example 1 and Comparative Example 2 were tested over time at room temperature and high temperature. The results are as follows Figure 8 , Fig. 9 and Fig.10 shown.
[0078] Figure 8 The high and low resistance states of the dual ferroelectric field effect transistor change with time at room temperature (25°C), where the high and low resistance states are achieved by applying gate voltage pulses of 3V / / 1s and -3V / / 1s, respectively. Fig. 9 The high and low resistance states of the dual ferroelectric field effect transistor change with time at high temperature (105°C), where the high and low resistance states are achieved by applying gate voltage pulses of 3V / / 1s and -3V / / 1s, respectively. Fig.10 1 is a comparison diagram of the high and low resistance states of the ferroelectric field effect transistors of Example 1 and Comparative Example 2 changing with time. Figure 8-10It can be seen that at room temperature and high temperature, the high and low resistance states of the dual ferroelectric field effect transistor in Example 1 are still separated from each other after 1000s of testing, while the high and low resistance states of the single ferroelectric field effect transistor prepared in Comparative Example 2 overlap after less than 100 seconds of testing. The above results prove that the dual ferroelectric field effect transistor prepared by the present invention has higher ferroelectric retention performance.
[0079] 3. The change of the switching ratio of the ferroelectric field effect transistors obtained in Example 1 and Comparative Examples 1-2 over time was tested. The results are as follows: Fig.11 shown.
[0080] from Fig.11 It can be seen that the storage windows of the single ferroelectric field effect transistors prepared in Comparative Examples 1 and 2 disappear after 100 seconds, and only the dual ferroelectric field effect transistor prepared in Example 1 still has a storage window after 1000 seconds. The above results prove that compared with the single ferroelectric field effect transistor, the dual ferroelectric field effect transistor prepared in the present invention has obvious advantages in the performance of non-volatile storage.
[0081] The above embodiments are specific implementation methods of the present invention, but the implementation methods of the present invention are not limited to the above embodiments. Any other combination, change, modification, substitution and simplification that does not exceed the design concept of the present invention shall fall within the protection scope of the present invention.
Claims
1. A dual ferroelectric enhancement mode ferroelectric field effect transistor, characterized in that: include: A substrate; a gate layer formed on the substrate; a ferroelectric dielectric layer formed on the gate layer; a buffer layer formed on the ferroelectric dielectric layer; A ferroelectric semiconductor channel layer is formed on the buffer layer.
2. The dual ferroelectric enhancement mode ferroelectric field effect transistor according to claim 1, characterized in that: The material of the ferroelectric dielectric layer is bismuth ferrite, and the thickness of the ferroelectric dielectric layer is 140-160 nm.
3. The dual ferroelectric enhancement mode ferroelectric field effect transistor according to claim 1, characterized in that: The material of the ferroelectric semiconductor channel layer is indium triselenide, and the thickness of the ferroelectric semiconductor channel layer is 45-50 nm.
4. The dual ferroelectric enhancement mode ferroelectric field effect transistor according to claim 1, characterized in that: The dual ferroelectric enhancement mode ferroelectric field effect transistor further comprises a source and a drain formed on the ferroelectric semiconductor channel layer, wherein the source and the drain are symmetrically formed at two ends of the ferroelectric semiconductor channel layer.
5. The dual ferroelectric enhancement mode ferroelectric field effect transistor according to claim 1, characterized in that: The material of the buffer layer is hafnium-based ferroelectric oxide or aluminum oxide; the thickness of the buffer layer is 10-15 nm.
6. The dual ferroelectric enhancement mode ferroelectric field effect transistor according to claim 1, characterized in that: The material of the gate layer is strontium ruthenate; the thickness of the gate layer is 10-20nm.
7. The dual ferroelectric enhancement mode ferroelectric field effect transistor according to claim 4, characterized in that: The substrate material is strontium titanate; the source electrode is any one of chromium / gold and titanium / gold; and the drain electrode is any one of chromium / gold and titanium / gold.
8. A method for preparing a dual ferroelectric enhancement mode ferroelectric field effect transistor as claimed in claim 1, characterized in that: The following steps are involved: (1) preparing a gate layer on a substrate by laser pulse deposition; (2) depositing a dielectric material on the gate layer described in step (1) by laser pulse deposition and performing annealing to prepare a ferroelectric dielectric layer; (3) preparing a buffer layer on the ferroelectric dielectric layer described in step (2) by atomic layer deposition; (4) Preparing a ferroelectric semiconductor channel layer on the buffer layer described in step (3) by a transfer alignment method.
9. The method for preparing a dual ferroelectric enhancement mode ferroelectric field effect transistor according to claim 8, characterized in that: Also includes: A source electrode and a drain electrode are prepared on the ferroelectric semiconductor channel layer.
10. Application of the dual ferroelectric enhancement mode ferroelectric field effect transistor according to any one of claims 1 to 7 in a ferroelectric memory.