Cross-shaped silicon carbide device and preparation method thereof
By adopting a cross-shaped layout structure design in SiC MOSFET devices, increasing the area of the channel region and the density of the flow path, the problem of insufficient flow capacity of the SiC MOSFET device is solved and better conduction performance is achieved.
Patent Information
- Application Number
- CN202411899253.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-03-11
AI Technical Summary
How to improve the channel region density and flow capacity per unit area of SiC MOSFET devices, and solve the problem that traditional SiC-based devices are difficult to improve their performance.
The planar gate SiC MOSFET device designed with a cross-shaped layout structure increases the area of the channel region and the density of the flow path by forming the P-body region, NP region and PP region of the cross-shaped structure on the SiC Drift layer, and forming a gate oxide layer, a Poly layer, an isolation dielectric layer and an ohmic contact alloy layer thereon.
This greatly increases the channel area density of the device, improves the flow capacity per unit area of SiC MOSFET device, and improves the on-off performance of the device.
Smart Images
Figure CN119604009A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a cross-shaped silicon carbide device and a preparation method thereof. Background Art
[0002] With the rapid development of society, the whole world is calling for energy conservation and environmental protection, which has also led to the rapid development of new energy vehicles, clean energy and other fields under the impetus of society, such as the 800V platform of new energy vehicles, high-power applications of photovoltaic energy storage inverters, etc., which also promote the development of power electronics technology. End customers have begun to put forward more stringent requirements on the performance and reliability of power devices. However, traditional Si-based devices are currently unable to perform better. Therefore, the third-generation semiconductor devices represented by SiC benefit from the excellent characteristics of the material itself. While exerting higher system efficiency, they can also reduce system volume and size to achieve cost reduction.
[0003] Among SiC power devices, SiC MOSFET is the most core product. It not only benefits from the material properties, but also has the switching advantages of MOSFET unipolar structure devices. Therefore, compared with the most commonly used Si MOSFET and SiIGBT switching devices on the market, its performance is more outstanding. However, since SiC was developed later and is not mature enough compared to Si-based devices, how to increase the channel density of SiC MOSFET devices and improve the current capacity per unit area of SiC MOSFET devices is a technical problem that technicians in this field need to solve urgently. Summary of the invention
[0004] In view of the above problems, the present invention designs a cross-shaped planar gate SiC MOSFET device, which greatly increases the channel region density of the device and improves the current carrying capacity per unit area of the SiC MOSFET device.
[0005] The technical solution of the present invention is: A method for preparing a cross-shaped silicon carbide device comprises the following steps: S100, growing a SiC Drift layer on the top surface of the SiC Sub layer; S200, forming a cross-shaped P-body region, a cross-shaped NP region and a PP region in sequence on the top surface of the SiC Drift layer by ion implantation, and activating the implanted regions of the P-body region, the NP region and the PP region by high temperature annealing; S300, a gate oxide layer is formed by dry oxygen oxidation growth on the top surfaces of the SiC Drift layer, the P-body region and both ends of the NP region, and NO annealing is introduced during the process; S400, forming a Poly layer on the top surface of the gate oxide layer by Poly deposition to serve as a gate electrode of the device; S500, forming an isolation dielectric layer on the top surface of the NP region and the Poly layer by oxide deposition, serving as a dielectric for isolating the gate electrode and the source electrode at the source of the device; S600, forming an ohmic contact alloy layer on the top surface of the NP region, and finally forming a front electrode metal layer after metal sputtering or evaporation.
[0006] Specifically, in step S100 , the conductivity types of the SiC Sub layer and the SiC Drift layer are both N-type.
[0007] Specifically, in step S200, the bottom depth of the P-body region is 0.6um-2um, and the doping concentration is 1E17-3E18cm -2 .
[0008] Specifically, in step S200, the bottom depth of the NP region is 0.3um-1.6um, and the doping concentration is 1E18-3E19cm -2 .
[0009] Specifically, in step S200, the bottom depth of the PP region is 0.3um-1.8um, and the doping concentration is 1E18-3E19cm -2 .
[0010] Specifically, the high temperature annealing temperature condition in step S200 is 1600°C-1900°C.
[0011] Specifically, in step S300 , the thickness of the gate oxide layer is 40 nm-70 nm.
[0012] Specifically, in step S400, the thickness of the Poly layer is 300nm-800nm.
[0013] A cross-shaped silicon carbide device comprises a SiC Sub layer, a SiC Drift layer, an ohmic contact alloy layer and a front electrode metal layer arranged in sequence from bottom to top; The SiC Drift layer is provided with: The P-body region is provided with a plurality of P-body regions which are spaced apart and extend downward from the top surface of the SiC Drift layer, respectively, in a cross-shaped structure; A plurality of NP regions are provided, each extending downward from the top surface of the P-body region, and a gap is provided between the bottom surface of the NP region and the bottom surface of the P-body region; the gap between the side surface of the NP region and the side surface of the P-body region forms a channel region; A PP region extends downward from the top surface of the NP region adjacent to the parasitic body diode and is connected to the P-body region; the depth of the PP region extending downward is not less than the depth of the NP region extending downward; A gate oxide layer, located on the top surface between adjacent NP regions, and having a bottom surface connected to the NP region, the P-body region and the SiCDrift layer respectively; A Poly layer, disposed on the top surface of the gate oxide layer; The isolation dielectric layer is located on the top surface of the Poly layer, and its side portion extends downward to the top surface of the NP region.
[0014] Specifically, the ohmic contact alloy layer is located between adjacent isolation dielectric layers, and the bottom surface is connected to the NP region.
[0015] The P-body region and NP region of the present invention adopt a cross-shaped layout structure design, which can increase the area of the channel region in the device by 20%-30% compared with the traditional strip-shaped layout, thereby increasing the density of the channel region of the current path, resulting in a significant improvement in the current capacity per unit area of the SiCMOSFET device, and achieving better device conduction performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 1 is a top view of the cross-shaped planar gate SiC MOSFET of the present invention, in which the gate oxide layer 6, the Poly layer 7, the isolation dielectric layer 8, the ohmic contact alloy layer 9 and the front electrode metal layer 10 are hidden; Figure 2 This is a top view of a conventional strip-shaped planar gate SiC MOSFET; Figure 3 yes Figure 1 The structural diagram of the AA section in the X direction; Figure 4 yes Figure 1 Structural diagram of the BB section in the Y direction; In the figure, 1 is SiC Sub layer, 2 is SiCDrift layer, 3 is P-body region, 4 is NP region, 5 is PP region, 6 is gate oxide layer, 7 is Poly layer, 8 is isolation dielectric layer, 9 is ohmic contact alloy layer, and 10 is front electrode metal layer. DETAILED DESCRIPTION
[0017] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.
[0018] A cross-shaped silicon carbide device comprises the following steps: S100, growing a SiC Drift layer 2 on the top surface of the SiC Sub layer 1 by epitaxial deposition, wherein the SiC Sub layer 1 serves as a support and the SiC Drift layer 2 serves as a protection; In step S100 , the conductivity types of the SiC Sub layer 1 and the SiC Drift layer 2 are both N-type.
[0019] S200, forming a cross-shaped P-body region 3 on the top surface of the SiC Drift layer 2 by Al ion implantation; The bottom depth of the P-body region 3 in step S200 is 0.6um-2um, and the doping concentration is 1E17-3E18cm -2 .
[0020] S300, forming a cross-shaped NP region 4 on the top surface of the P-body region 3 by N ion implantation; The bottom depth of the NP region 4 in step S300 is 0.3um-1.6um, and the doping concentration is 1E18-3E19cm -2 .
[0021] S400, forming a PP region 5 on the top surface of the NP region 4 by Al ion implantation; The bottom depth of the PP region 5 in step S400 is 0.3um-1.8um, and the doping concentration is 1E18-3E19cm -2 .
[0022] S500, through high temperature annealing, the P-body region 3, the NP region 4 and the PP region 5 are activated and formed; The high temperature annealing temperature in step S500 is 1600°C-1900°C.
[0023] S600, a gate oxide layer 6 is formed on the top surfaces of both ends of the NP region 4 by dry oxygen oxidation growth, and NO annealing is introduced during the process to improve the quality of the gate oxide layer; The thickness of the gate oxide layer 6 in step S600 is 40 nm-70 nm.
[0024] S700, forming a Poly layer 7 on the top surface of the gate oxide layer 6 by Poly deposition, which serves as the gate electrode of the device; The thickness of the Poly layer 7 in step S700 is 300nm-800nm.
[0025] S800, forming an isolation dielectric layer 8 on the top surface of the NP region 4 and the Poly layer 7 by oxide deposition, serving as a dielectric for isolating the gate electrode and the source electrode at the source of the device to prevent the two from being short-circuited; S900, forming an ohmic contact alloy layer 9 connected to the NP region 4 on the side of the isolation dielectric layer 8 by sputtering or depositing Ni metal and then performing rapid thermal annealing; The thickness of the Ni metal in step S900 is 100nm-300nm.
[0026] S1000, forming a front electrode metal layer 10 on the top surface of the isolation dielectric layer 8 and the ohmic contact alloy layer 9 by sputtering or evaporating Ti and AlCu metals; The thickness of the Ti metal in step S1000 is 0.1um-0.6um, and the thickness of the AlCu metal is 2um-5um.
[0027] A cross-shaped silicon carbide device comprises a SiC Sub layer 1, a SiC Drift layer 2, an Ohmic contact alloy layer 9 and a front electrode metal layer 10 arranged in sequence from bottom to top; The SiC Drift layer 2 is provided with: A plurality of P-body regions 3 are provided, which are arranged at intervals and extend downward from the top surface of the SiC Drift layer 2 respectively; The NP region 4 is provided with a plurality of NP regions, each extending downward from the top surface of the P-body region (3), and having a gap between its bottom surface and the bottom surface of the P-body region (3); the gap between the side surface of the NP region (4) and the side surface of the P-body region 3 forms a channel region; A PP region (5) extends downward from the top surface of the NP region (4) adjacent to the parasitic body diode and is connected to the P-body region (3); the depth of the downward extension of the PP region (5) is not less than the depth of the downward extension of the NP region 4; A gate oxide layer (6), located on the top surface between adjacent NP regions (4), and having a bottom surface connected to the NP region (4), the P-body region (3) and the SiC Drift layer (2); A Poly layer (7) disposed on the top surface of the gate oxide layer (6); An isolation dielectric layer (8) is located on the top surface of the Poly layer (7), with a side portion extending downward to the top surface of the NP region (4).
[0028] The ohmic contact alloy layer (9) is located between adjacent isolation dielectric layers (8), and its bottom surface is connected to the NP region (4).
[0029] The bottom surface of the front electrode metal layer (10) is respectively connected to the isolation dielectric layer (8) and the ohmic contact alloy layer (9).
[0030] The present invention adopts a cross-shaped layout structure design for SiCMOSFET. Compared with the traditional strip-shaped layout, this design can increase the area of the channel region in the device by 20%-30%, thereby improving the current carrying capacity of the device by nearly 20%. Currently, most planar gate SiC MOSFET devices on the market adopt a strip-shaped cell layout, with the channel region only being formed in one of the horizontal or vertical directions. However, the cross-shaped layout presents a meandering layout of the channel region, with the channel region formed in both the horizontal and vertical directions, thereby greatly increasing the channel region density of the device. The increase in the density of the channel region as a current carrying path will greatly increase the current carrying capacity per unit area of the SiCMOSFET device, and the device has better conduction performance.
Claims
1. A method for preparing a cross-shaped silicon carbide device, characterized in that: The steps include: S100, growing a SiC Drift layer (2) on the top surface of the SiC Sub layer (1); S200, forming a cross-shaped P-body region (3), a cross-shaped NP region (4) and a PP region (5) in sequence on the top surface of the SiC Drift layer (2) by ion implantation, and activating the implanted regions of the P-body region (3), the NP region (4) and the PP region (5) by high temperature annealing; S300, forming a gate oxide layer (6) on the top surfaces of the SiC Drift layer (2), the P-body region (3) and the NP region (4) by dry oxygen oxidation growth, and NO annealing is introduced during the process; S400, forming a Poly layer (7) on the top surface of the gate oxide layer (6) by Poly deposition to serve as a gate electrode of the device; S500, forming an isolation dielectric layer (8) by oxide deposition on the top surface of the NP region (4) and the Poly layer (7), which serves as a dielectric for isolating the gate electrode and the source electrode at the source of the device; S600, forming an ohmic contact alloy layer (9) on the top surface of the NP region (4), and finally forming a front electrode metal layer (10) by metal sputtering or evaporation.
2. A method for preparing a cross-shaped silicon carbide device according to claim 1, characterized in that: In step S100 , the conductivity types of the SiC Sub layer (1) and the SiC Drift layer (2) are both N-type.
3. The method for preparing a cross-shaped silicon carbide device according to claim 1, characterized in that: In step S200, the bottom depth of the P-body region (3) is 0.6um-2um, and the doping concentration is 1E17-3E18cm -2 .
4. The method for preparing a cross-shaped silicon carbide device according to claim 1, characterized in that: In step S200, the bottom depth of the NP region (4) is 0.3um-1.6um, and the doping concentration is 1E18-3E19cm -2 .
5. The method for preparing a cross-shaped silicon carbide device according to claim 1, characterized in that: In step S200, the bottom depth of the PP region (5) is 0.3um-1.8um, and the doping concentration is 1E18-3E19cm -2 .
6. The method for preparing a cross-shaped silicon carbide device according to claim 1, characterized in that: The high temperature annealing temperature condition in step S200 is 1600°C-1900°C.
7. The method for preparing a cross-shaped silicon carbide device according to claim 1, characterized in that: In step S300, the thickness of the gate oxide layer (6) is 40nm-70nm.
8. The method for preparing a cross-shaped silicon carbide device according to claim 1, characterized in that: In step S400, the thickness of the Poly layer (7) is 300nm-800nm.
9. A cross-shaped silicon carbide device, prepared by the method for preparing a cross-shaped silicon carbide device according to any one of claims 1 to 10, characterized in that: It comprises a SiC Sub layer (1), a SiC Drift layer (2), an Ohmic contact alloy layer (9) and a front electrode metal layer (10) which are arranged in sequence from bottom to top; The SiC Drift layer (2) is provided with: A plurality of P-body regions (3) are provided, which are arranged at intervals and extend downward from the top surface of the SiC Drift layer (2) to form a cross-shaped structure; The NP region (4) is provided with a plurality of NP regions, each extending downward from the top surface of the P-body region (3), and having a gap between its bottom surface and the bottom surface of the P-body region (3); the gap between the side surface of the NP region (4) and the side surface of the P-body region (3) forms a channel region; A PP region (5) extends downward from the top surface of the NP region (4) at a position adjacent to the parasitic body diode and is connected to the P-body region (3); the depth of the downward extension of the PP region (5) is not less than the depth of the downward extension of the NP region (4); A gate oxide layer (6), located on the top surface between adjacent NP regions (4), and having a bottom surface connected to the NP region (4), the P-body region (3) and the SiC Drift layer (2); A Poly layer (7) disposed on the top surface of the gate oxide layer (6); An isolation dielectric layer (8) is located on the top surface of the Poly layer (7), with a side portion extending downward to the top surface of the NP region (4).
10. The cross-shaped silicon carbide device according to claim 9, characterized in that: The ohmic contact alloy layer (9) is located between adjacent isolation dielectric layers (8), and its bottom surface is connected to the NP region (4).