Semiconductor device and preparation method thereof

Abstract

The invention relates to a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate, an active layer, a gate structure and a variable resistor. The active layer is disposed on the substrate. The active layer comprises an active region and a non-active region which are arranged at an interval. The active region includes a source region, a drain region, and a channel region. The gate structure is disposed over the active region. A variable resistor is disposed over the inactive region.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a method for preparing the same. Background Art

[0002] Radio frequency (RF) devices play a vital role in the field of wireless communications. The maximum power (P max ) directly affects the performance and efficiency of RF devices. In order to increase the maximum power of these RF components, AC floating bias technology is usually used in related technologies to control voltage. This technology achieves voltage control by externally attaching a resistor in front of the gate of the MOS tube or between the source and drain.

[0003] However, in the related art, only one external resistor with a fixed resistance value can be formed on each wafer, and the resistance value cannot be flexibly adjusted. This not only increases the design and testing costs of RF components, but also limits the further optimization of their performance.

[0004] Therefore, how to improve the flexibility and accuracy of external resistor regulation has become an urgent problem to be solved in the current technical field. Summary of the invention

[0005] The present application provides a semiconductor device and a method for manufacturing the same, so as to improve the flexibility and precision of regulating an external resistor.

[0006] To achieve the above technical objectives, the first aspect of the present application provides a semiconductor device. The semiconductor device includes: a substrate, an active layer, a gate structure and a variable resistor. The active layer is arranged on the substrate. The active layer includes an active area and an inactive area arranged at intervals. The active area includes a source area, a drain area and a channel area. The gate structure is arranged above the active area. The variable resistor is arranged above the inactive area.

[0007] To achieve the above technical objectives, the second aspect of the present application provides a method for preparing a semiconductor device. The method comprises: providing a substrate; forming an active layer above the substrate, and defining an active area and an inactive area spaced apart in the active layer; making a gate structure above the active area; and making a variable resistor above the inactive area.

[0008] In the present application, the semiconductor device includes: a substrate, an active layer, a gate structure and a variable resistor. The active layer is arranged on the substrate. The active layer includes an active area and an inactive area arranged at intervals. The active area includes a source area, a drain area and a channel area. The gate structure is arranged above the active area. The variable resistor is arranged above the inactive area. By arranging the variable resistor above the inactive area, the relationship between different resistance values ​​and the maximum power allowable by the radio frequency component can be tested on a single test key (Test Key). Furthermore, by arranging the variable resistor above the inactive area, the direct influence of the variable resistor on the performance of the active area can be avoided, and the signal interference and heating effect of the resistance value regulation process of the variable resistor on other parts of the radio frequency component can be reduced. In this way, the technical solution of the present application can reduce the design, development and testing costs of the radio frequency component, and facilitate further optimization of the performance of the radio frequency component. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present application will illustrate the implementation methods in conjunction with the accompanying drawings. The accompanying drawings of the present application are only used to describe the embodiments for the purpose of demonstration. Without departing from the principles of the present application, those skilled in the art can easily make other embodiments according to the steps described below through the following description.

[0010] Figure 1 is a circuit diagram of a semiconductor device according to some embodiments of the present application;

[0011] Figure 2 is a schematic structural diagram of a semiconductor device according to some embodiments of the present application;

[0012] Figure 3 is a schematic top view of a semiconductor device according to some embodiments of the present application;

[0013] Figure 4 is a schematic top view of a variable resistor according to some embodiments of the present application;

[0014] Figure 5 According to some embodiments of the present application, the variable resistor Figure 4 Schematic diagram of the cross section of AA;

[0015] Figure 6 is a flow chart of a method for preparing a semiconductor device according to some embodiments of the present application;

[0016] Figure 7 According to some embodiments of the present application Figure 6 Flow chart of operation S40;

[0017] Figure 8 According to some embodiments of the present application, in a gate-last process, Figure 6 Flowchart of operations S30 and S40 in FIG.

[0018] Fig. 9 is a schematic structural diagram of a semiconductor device after operation S81 is performed according to some embodiments of the present application;

[0019] Fig.10 According to some embodiments of the present application Figure 8 Flow chart of operation S81 in FIG.

[0020] Fig.11 is a schematic diagram of disposing a photoresist on a first polysilicon structure according to some embodiments of the present application;

[0021] Fig.12 is a schematic structural diagram of a semiconductor device after operation S82 is performed according to some embodiments of the present application;

[0022] Fig.13 is a schematic structural diagram of a semiconductor device after operation S83 is performed according to some embodiments of the present application. DETAILED DESCRIPTION

[0023] The scheme of the embodiment of the present application is described in detail below in conjunction with the drawings of the specification.

[0024] In the following description, for the purpose of explanation rather than limitation, specific details such as specific system structures, interfaces, and technologies are provided to facilitate a thorough understanding of the present application.

[0025] The term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship. In addition, "many" in this article means two or more than two.

[0026] The terms "first", "second", and "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", and "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise specified in some embodiments. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products, or devices.

[0027] refer to Figure 1 , Figure 1 is a circuit diagram of a semiconductor device 1 according to some embodiments of the present application. Figure 1 As an example, the semiconductor device 1 is shown as a transistor 20 including a variable resistor 30. The transistor 20 is, for example, a MOS tube. Those skilled in the art should understand that the semiconductor device 1 can also be a switch tube, a tuner or other radio frequency components or other semiconductor devices 1 including the structure of the transistor 20, and the present application does not make specific restrictions on this.

[0028] like Figure 1 As shown, the semiconductor device 1 may include a transistor 20 and at least one of a first variable resistor 31 and a second variable resistor 32. The first variable resistor 31 is connected in series to the gate of the transistor 20. Specifically, one end of the first variable resistor 31 is connected to the gate, and the other end is connected to the gate control terminal 242. The second variable resistor 32 is connected between the source and the drain of the transistor 20. Specifically, one end of the second variable resistor 32 is connected to the source of the transistor 20, and the other end of the second variable resistor 32 is connected to the drain of the transistor 20.

[0029] Hereinafter, the first variable resistor 31 and the second variable resistor 32 may be collectively referred to as a variable resistor 30 or an external resistor. The semiconductor device 1 may be a semiconductor device 1 made based on a bulk silicon (Bulk Silicon) or SOI (Silicon On Insulator) platform, etc., and this application does not make specific restrictions on this. The semiconductor device 1 may be, for example, a test key (Test Key). The variable resistor 30 and the transistor 20 may be arranged on the same wafer.

[0030] In the present application, by setting a variable resistor 30 with a variable resistance value on the wafer, the voltage regulation efficiency and effect of the RF components such as the switch tube or the tuner can be improved. Furthermore, the technical solution of the present application can test the relationship between different external resistor values ​​and the maximum power of the RF component through a single semiconductor device 1, thereby improving the research and development efficiency of the semiconductor device 1.

[0031] refer to Figure 2 , Figure 2 1 is a schematic diagram of the structure of a semiconductor device 1 according to some embodiments of the present application. Figure 2 As shown, the semiconductor device 1 includes: a substrate, an active layer 10 , a gate structure 24 and a variable resistor 30 .

[0032] The substrate may be configured to provide support for other structures of the semiconductor device 1. The substrate may be, for example, a bulk silicon substrate, an SOI substrate, etc., and the present application does not impose any specific limitation on this.

[0033] The active layer 10 is disposed on the substrate. Specifically, the active layer 10 includes an active area 12 (Active Area) and a non-active area 14 (Non-Active Area) disposed at intervals.

[0034] The active region 12 may be a working region of a device such as a transistor 20. The active region 12 may include a source region 21 of the transistor 20 (see Figure 3 ), the drain region 22 (reference Figure 3 ) and channel region, etc.

[0035] The gate structure 24 is the gate of the transistor 20 and is disposed above the active region 12. The gate structure 24 and the source region 21, the drain region 22 and the channel region in the active region 12 constitute the main structure of the transistor 20, which will not be described in detail.

[0036] The variable resistor 30 is disposed above the inactive region 14. The variable resistor 30 may include the first variable resistor 31 and / or the second variable resistor 32 described above.

[0037] Specific reference Figure 2 and Figure 3 , Figure 3 is a schematic top view of a semiconductor device 1 according to some embodiments of the present application. Figure 3 As shown, the first variable resistor 31 is connected to the gate structure 24, and the gate control terminal 242 is connected to the gate structure 24 of the transistor 20 via the first variable resistor 31. The second variable resistor 32 is connected between the source region 21 and the drain region 22.

[0038] Continue to refer Figure 2, the non-active area 14 may include a shallow trench isolation (STI) structure. The variable resistors 30 such as the first variable resistor 31 and / or the second variable resistor 32 may be respectively arranged above the shallow trench isolation structure 141. The shallow trench isolation structure 141 is a shallow trench etched in the active layer 10, and is filled with an insulating material such as silicon dioxide. By arranging the variable resistor 30 above the shallow trench isolation structure, the variable resistor 30 can be effectively isolated from the active area 12 of the transistor 20, reducing the influence of the current leakage, parasitic capacitance, voltage change and heat generation of the variable resistor 30 on the active area 12 of the transistor 20, thereby improving the reliability of the RF component design.

[0039] like Figure 2 As shown, the gate structure 24 of the transistor 20 and the variable resistor 30 are located in the same material layer of the semiconductor device 1. In an embodiment where the gate structure 24 is made by a gate-last process, the electrode portion 340 of the variable resistor 30 can be made together with the gate structure 24 by a gate-last process, which is described in detail below.

[0040] refer to Figure 4 and Figure 5 , Figure 4 is a schematic top view of a variable resistor 30 according to some embodiments of the present application, Figure 5 According to some embodiments of the present application, the variable resistor 30 is Figure 4 Schematic diagram of the cross section of AA.

[0041] like Figure 4 and Figure 5 As shown, the variable resistor includes a semiconductor resistor portion 330 and an electrode portion 340. The electrode portion 340 is disposed adjacent to the semiconductor resistor portion 330. The electrode portion 340 receives an adjustment voltage and generates a corresponding electric field based on the adjustment voltage to adjust the size of a depletion region 342 in the semiconductor resistor portion 330 near the electrode portion 340, thereby changing the resistance of the semiconductor resistor portion 330.

[0042] In some embodiments, the semiconductor resistor 330 may be a resistor based on polysilicon. The semiconductor resistor 330 may, for example, include N-type doped polysilicon or P-type doped polysilicon. That is, the required resistor is obtained by N-type doping or P-type doping of polysilicon. The use of polysilicon for doping to obtain the resistor allows the semiconductor resistor 330 to be formed in the same process step as the pseudo gate structure in the gate-last process, thereby saving the preparation cost of the variable resistor 30 and improving its preparation efficiency.

[0043] The electrode portion 340 is disposed adjacent to the semiconductor resistor portion 330 . Figure 4 and Figure 5As shown in FIG. 1 , the electrode portion includes two electrode portions 340 respectively disposed on both sides of the semiconductor resistor portion 330 .

[0044] The electrode portion 340 may also include a single electrode portion 340 disposed on one side of the semiconductor resistor portion 330 , or more than two electrode portions 340 disposed around the semiconductor resistor portion 330 , and the present application does not impose any specific limitation on this.

[0045] The electrode portion 340 may be a conductive material disposed in the accommodating cavity 50, such as a metal electrode material. The variable resistor 30 may further include a gate isolation dielectric layer disposed between the semiconductor resistor portion 330 and the electrode portion 340. The gate isolation dielectric layer includes an interfacial layer 66 (IL) and a gate oxide layer composed of a high-κ dielectric layer 332. Specifically, the accommodating cavity 50 is filled with the interfacial layer 66, the high-κ dielectric layer 332, and the conductive material 61 (see FIG. 1 ). Fig.13 ). The interface layer 66 is composed of materials such as silicon dioxide (SiO2). The high-κ dielectric layer 332 is disposed between the conductive material 61 and the interface layer 66, and covers the bottom wall and side walls of the conductive material 61. The high-κ dielectric layer 332 may include HfO2 or the like.

[0046] The variable resistor 30 in this application is a voltage-controlled resistor. Figure 4 and Figure 5 As shown, the electrode portion 340 of the variable resistor 30 is connected to the variable resistor adjustment terminal through the contact hole 71 or the contact window metal. The variable resistor adjustment terminal can be configured to determine the adjustment voltage to be provided to the variable resistor 30 according to the required resistance value of the variable resistor 30. After receiving the adjustment voltage, the electrode portion 340 generates a corresponding bias electric field to adjust the size of the depletion region 342 near the electrode portion 340 in the semiconductor resistor portion 330.

[0047] In some embodiments, when the semiconductor resistor section 330 is N-type doped polysilicon, the main carriers of the semiconductor resistor section 330 are electrons. In response to the voltage of the electrode section 340 being a negative voltage, the electrons of the semiconductor resistor section 330 can be repelled away from the electrode section 340 by the bias electric field generated by the electrode section 340, thereby generating a depletion region 342 in a portion close to the electrode section 340. At this time, the entire cross-sectional area of ​​the semiconductor resistor section 330 includes the area of ​​the depletion region 342 and the remaining conductive cross-sectional area. Increasing the negative voltage value of the bias electric field can increase the depletion region 342, thereby reducing the conductive cross-sectional area to increase the resistance value of the semiconductor resistor section 330. Conversely, reducing the negative voltage value of the bias electric field can reduce the depletion region 342, thereby increasing the conductive cross-sectional area to reduce the resistance value of the semiconductor resistor section 330.

[0048] In other embodiments, when the semiconductor resistor portion 330 is P-type doped polysilicon, the main carriers of the semiconductor resistor portion 330 are holes. In response to the positive voltage of the electrode portion 340, the holes of the semiconductor resistor portion 330 can be repelled away from the electrode portion 340 by the bias electric field, thereby generating a depletion region 342 in the portion close to the electrode portion 340. Increasing the positive voltage value of the bias electric field can increase the depletion region 342, thereby reducing the conductive cross-sectional area to increase the resistance of the semiconductor resistor portion 330. Conversely, reducing the positive voltage value of the bias electric field can reduce the depletion region 342, thereby increasing the conductive cross-sectional area to reduce the resistance of the semiconductor resistor portion 330.

[0049] In an embodiment where the electrode portion 340 includes two electrode portions 340 respectively arranged on both sides of the semiconductor resistor portion 330, the two electrode portions 340 can be symmetrically arranged on both sides of at least a portion of the semiconductor resistor portion 330 to simultaneously adjust the conductive cross-sectional area of ​​the semiconductor resistor portion 330 from both sides, thereby enhancing the efficiency of resistance value adjustment.

[0050] In summary, when the semiconductor resistor 330 is an N-type semiconductor, the corresponding adjustment voltage is a negative voltage. When the semiconductor resistor 330 is a P-type semiconductor, the corresponding adjustment voltage is a positive voltage. Increasing the absolute value of the adjustment voltage can increase the resistance of the variable resistor 30. Conversely, decreasing the absolute value of the adjustment voltage can decrease the resistance of the variable resistor 30.

[0051] In some embodiments, the semiconductor device 1 may further include an outer periphery surrounding the variable resistor 30 (eg, Figure 4 The spacer 62 is formed on the periphery of the semiconductor resistor 330 and the electrode 340. The spacer 62 may include one or more dielectric layers as a wall, such as an ONO (Oxide-Nitride-Oxide, silicon oxide-silicon nitride-silicon oxide) structure. In the preparation process of the semiconductor device 1 of the present application, the spacer 62 can play an isolation and protection role.

[0052] refer to Figure 6 , Figure 6 1 is a flow chart of a method for preparing a semiconductor device 1 according to some embodiments of the present application. Figures 2 to 5 The specific operations of the method for preparing the semiconductor device 1 are as follows.

[0053] S10: providing a substrate.

[0054] Specifically, the substrate may be configured to provide support for other structures of the semiconductor device 1. The substrate may be, for example, a bulk silicon substrate, an SOI substrate, etc., and the present application does not impose any specific limitation on this.

[0055] S20 : ​​forming an active layer 10 on a substrate, and defining an active region 12 and an inactive region 14 spaced apart from each other in the active layer 10 .

[0056] In some embodiments, the non-active region 14 includes a shallow trench isolation structure 141 .

[0057] In some embodiments, a shallow trench may be prepared on the substrate by photolithography and etching processes, and an insulating material such as silicon dioxide may be filled in the shallow trench by chemical vapor deposition or the like, and then excess insulating material may be removed by chemical mechanical polishing (CMP) to planarize the shallow trench isolation structure 141. In this way, a non-active region 14 including the shallow trench isolation structure 141 may be defined in the active layer 10.

[0058] In some embodiments, the active region 12 may include a source region 21, a drain region 22, and a channel region of the transistor 20. Depending on the specific process flow, these regions may be prepared before, after, or alternately with the gate structure 24 of the transistor 20 and / or the variable resistor 30, and the present application does not impose any specific limitation on this.

[0059] S30 : forming a gate structure 24 on the active region 12 .

[0060] The gate structure 24 may be manufactured by a gate-first process or a gate-last process, and the present application does not impose any specific limitation thereto.

[0061] The present application does not limit the number of gate structures 24 .

[0062] S40 : forming a variable resistor 30 on the inactive region 14 .

[0063] In some embodiments, the variable resistor 30 is disposed above the shallow trench isolation structure 141 .

[0064] In some embodiments, the variable resistor 30 is a voltage-controlled resistor. As described above, the variable resistor 30 includes a semiconductor resistor portion 330 and an electrode portion 340. The electrode portion 340 is disposed adjacent to the semiconductor resistor portion 330, and the electrode portion 340 receives an adjustment voltage and generates a corresponding electric field based on the adjustment voltage to adjust the size of a depletion region 342 in the semiconductor resistor portion 330 near the electrode portion 340, thereby changing the resistance of the semiconductor resistor portion 330.

[0065] Those skilled in the art should understand that, in the case where there is no conflict in the process, the present application does not limit the order of the operations. For example, operation S30 may be performed before or after operation S40, and operations S30 and S40 may also be performed in the same process. For example, in an embodiment in which the gate structure 24 is prepared by a gate-last process, operations S30 and S40 may be performed simultaneously.

[0066] In the preparation method of the present application, by setting the variable resistor 30 above the inactive area 14, the variable resistor 30 can be set on the same wafer as the transistor 20. By setting the variable resistor 30 with a variable resistance value on the wafer, the voltage regulation efficiency and effect of a switch tube or a tuner can be improved. Furthermore, the technical solution of the present application can test the relationship between different external resistor values ​​and the maximum power of the radio frequency component through a single semiconductor device 1, thereby improving the research and development efficiency of the semiconductor device 1.

[0067] refer to Figure 7 , Figure 7 According to some embodiments of the present application Figure 6 Flow chart of operation S40.

[0068] Specifically, Figure 7 As shown, combined with Figures 2 to 5 The operation of manufacturing the variable resistor 30 on the inactive region 14 in step S40 may include the following operations.

[0069] S410 : forming a source region 21 , a drain region 22 and a channel region in the active region 12 .

[0070] The source region 21 , the drain region 22 and the channel region are different structures of the same transistor 20 , and the preparation methods thereof will not be described in detail in this application.

[0071] S420 : manufacturing a first variable resistor 31 and / or a second variable resistor 32 on the inactive region 14 .

[0072] In some embodiments, the inactive region 14 includes a shallow trench isolation structure 141 . The first variable resistor 31 and / or the second variable resistor 32 are fabricated above the shallow trench isolation structure 141 .

[0073] S430 : connecting the first variable resistor 31 to the gate structure 24 , and connecting the second variable resistor 32 between the source region 21 and the drain region 22 .

[0074] In some embodiments, the first variable resistor 31 may be connected to the gate structure 24 of the transistor 20 through a contact hole 71 or a contact window metal, and the second variable resistor 32 may be connected between the source region 21 and the drain region 22 of the transistor 20 .

[0075] Specifically, a contact window may be formed in the intermediate dielectric layer above the active layer 10, and metal may be filled in the contact window to form a contact hole 71. The contact hole 71 is configured to respectively connect the first variable resistor 31 and the second variable resistor 32 to the metal interconnection 72. The metal interconnection 72 may be formed by a BEOL (Back End of Line) process.

[0076] Specifically, the contact hole 71 and the metal interconnection 72 are configured to connect the first end of the first variable resistor 31 to the gate control terminal 242, and connect the second end of the first variable resistor 31 to the gate structure 24 of the transistor 20. The contact hole 71 and the metal interconnection 72 are configured to connect the first end of the second variable resistor 32 to the source region 21 of the transistor 20, and connect the second end of the second variable resistor 32 to the drain region 22 of the transistor 20.

[0077] refer to Figure 8 , Figure 8 The flowchart shows that in the gate-last process, operation S30 is to form the gate structure 24 above the active area 12, and operation S40 is to form the variable resistor 30 above the inactive area 14. In the gate-last process, the gate structure 24 and the variable resistor 30 can be formed in the same process, thereby saving the preparation time and cost of the variable resistor 30. Specifically, the preparation process of the gate structure 24 and the variable resistor 30 includes the following steps.

[0078] S81 : forming at least one first polysilicon structure 41 on the non-active region 14 , and forming a second polysilicon structure 42 on the active region 12 .

[0079] Also refer to Fig. 9 and Fig.10 , Fig. 9 is a schematic structural diagram of a semiconductor device 1 after operation S81 is performed according to some embodiments of the present application, Fig.10 According to some embodiments of the present application Figure 8 Schematic diagram of the flow chart of operation S81 in .

[0080] like Fig.10 As shown, operation S81 includes the following operations.

[0081] S811 : forming a channel region in the active region 12 .

[0082] The present application does not limit the method for forming the channel region.

[0083] S812 : depositing a polysilicon layer on the active layer 10 , and patterning the polysilicon layer to obtain at least one first polysilicon structure 41 and a second polysilicon structure 42 .

[0084] In some embodiments, a polysilicon layer is deposited on the active layer 10 by a process such as chemical vapor deposition, and then the polysilicon layer is patterned by mask lithography and etching processes to obtain at least one first polysilicon structure 41 and a second polysilicon structure 42. The first polysilicon structure 41 can be used to form the variable resistor 30 later, and the second polysilicon structure 42 can be used to form the gate structure 24 of the transistor 20 later.

[0085] In some embodiments, during the photolithography process, a hard mask 63 may be used to transfer the pattern of the mask, and the hard mask 63 may include, for example, silicon nitride or silicon oxide, etc. After obtaining at least one first polysilicon structure 41 and a second polysilicon structure 42, the corresponding hard mask 63 may continue to remain on the corresponding polysilicon structure to continue to be used to protect the corresponding polysilicon structure in subsequent processes.

[0086] S813 : forming a sidewall 62 surrounding at least one of the first polysilicon structure 41 and the second polysilicon structure 42 .

[0087] In some embodiments, the sidewall 62 may include one or more dielectric layers as a wall, such as an ONO (Oxide-Nitride-Oxide, silicon oxide-silicon nitride-silicon oxide) structure. In the preparation process of the semiconductor device 1 of the present application, the sidewall 62 may play a role in isolating and protecting the polysilicon structure.

[0088] S814 : doping at least one first polysilicon structure 41 .

[0089] In some embodiments, at least one of the first polysilicon structure 41 and the second polysilicon structure 42 is doped. Specifically, the first polysilicon structure 41 may be doped with N-type or P-type, and / or the second polysilicon structure 42 may be doped with N-type. The doping types of the first polysilicon structure 41 and the second polysilicon structure 42 may be opposite, for example, the first polysilicon structure 41 is doped with P-type, and the second polysilicon structure 42 is doped with N-type.

[0090] In some implementations, during the doping process, dopants may pass through the hard mask 63 and enter the corresponding polysilicon structure.

[0091] In some embodiments, in operation S814 , the active region 12 in the active layer 10 may be doped to form a source region 21 and a drain region 22 of the transistor 20 .

[0092] S815 : forming an interlayer dielectric layer 64 .

[0093] The interlayer dielectric layer (ILD) 64 is also called a dielectric layer. As an example but not limitation, the interlayer dielectric layer 64 may include a silicon oxide and / or silicon nitride dielectric layer.

[0094] In some embodiments, an interlayer dielectric layer 64 is formed on the active layer 10 by deposition, coating, etc. The interlayer dielectric layer 64 may be located between at least one first polysilicon structure 41 and a second polysilicon structure 42 .

[0095] like Fig. 9As shown, the semiconductor device 1 at this time includes an interlayer dielectric layer 64 above the active layer 10. At least one first polysilicon structure 41 and a second polysilicon structure 42 are respectively located in the interlayer dielectric layer 64. The first polysilicon structure 41 is located above the non-active area 14, and the second polysilicon structure 42 is located above the active area 12. The source region 21, the drain region 22 and the channel region (not shown) of the transistor 20 have been formed in the active area 12. The first polysilicon structure 41 and the second polysilicon structure 42 are respectively surrounded by sidewalls 62. The first polysilicon structure 41 and the second polysilicon structure 42 are also covered with hard masks 63 respectively.

[0096] In the gate-last process, the second polysilicon structure 42 is also called a dummy gate structure.

[0097] S82 : removing a portion of the first polysilicon structure 41 to form at least one first accommodation cavity 51 , and removing the second polysilicon structure 42 to form a second accommodation cavity 52 .

[0098] In some embodiments, a portion of the polysilicon of the first polysilicon structure 41 may be removed by photolithography and etching to define the first accommodation cavity 51. Meanwhile, all of the polysilicon of the second polysilicon structure 42 may be removed by photolithography and etching to define the second accommodation cavity 52.

[0099] In some embodiments, removing a portion of the first polysilicon structure 41 to form at least one first accommodation cavity 51 includes: removing portions on both sides of the first polysilicon structure 41 to form two first accommodation cavities 51 .

[0100] refer to Fig.11 and Fig.12 , Fig.11 is a schematic diagram of disposing a photoresist 65 on the first polysilicon structure 41 according to some embodiments of the present application, Fig.12 is a schematic structural diagram of the semiconductor device 1 after operation S82 is performed according to some embodiments of the present application.

[0101] like Fig.11 As shown, a photoresist 65 may be provided in the middle portion of the first polysilicon structure 41 to allow etching of the polysilicon portions on both sides of the first polysilicon structure 41 while retaining the middle portion of the first polysilicon structure 41, thereby forming two first accommodating cavities 51 separated by the remaining first polysilicon portions.

[0102] like Fig.12 As shown, after etching, the semiconductor device 1 is now defined by two first accommodating cavities 51 between the remaining polysilicon portion of the first polysilicon structure 41 and the sidewall 62, and a second accommodating cavity 52 at the position of the original dummy gate structure 24. The second accommodating cavity 52 is also surrounded by the sidewall 62.

[0103] S83 : filling the at least one first accommodation cavity 51 with a conductive material 61 to form the electrode portion 340 of the variable resistor 30 , and filling the second accommodation cavity 52 with a conductive material 61 to form the gate structure 24 .

[0104] In some embodiments, a gate isolation dielectric layer is deposited on the cavity wall of the first accommodating cavity 51, and then a conductive material 61 is filled in the first accommodating cavity 51 as the electrode portion 340. Depositing the gate isolation dielectric layer on the cavity wall of the first accommodating cavity 51 may include sequentially depositing an interface layer 66 and a high-κ dielectric layer 332 on the cavity wall of the first accommodating cavity 51.

[0105] In some embodiments, the conductive material 61 may be, for example, a metallic conductive material.

[0106] refer to Fig.13 , Fig.13 is a schematic structural diagram of the semiconductor device 1 after operation S83 is performed according to some embodiments of the present application.

[0107] like Fig.13 As shown, the first accommodation cavity 51 is filled with the electrode portion 340 of the variable resistor 30. The two electrode portions 340 are respectively arranged on both sides of the semiconductor resistor portion 330. The semiconductor resistor portion 330 of the variable resistor 30 is the remaining portion after etching the first polysilicon structure 41. The second accommodation cavity 52 is filled with the conductive structure of the gate structure 24.

[0108] In some embodiments, the deposited high-κ dielectric layer 332 , interface layer 66 , and / or conductive material 61 layer may then be CMP planarized to remove excess material.

[0109] After the contact hole 71 is formed, the electrode portion 340 may receive an adjustment voltage and generate a corresponding electric field based on the adjustment voltage to adjust the size of the depletion region 342 near the electrode portion 340 in the semiconductor resistor portion 330 and change the resistance of the semiconductor resistor portion 330 .

[0110] In the above method, the preparation of the electrode portion 340 can be performed simultaneously with the preparation of the gate structure 24 , thereby reducing the manufacturing cost of the variable resistor 30 and improving its manufacturing efficiency.

[0111] The above description of various embodiments tends to emphasize the differences between the various embodiments. The same or similar aspects can be referenced to each other, and for the sake of brevity, they will not be repeated herein.

Claims

1. A semiconductor device, comprising: substrate; An active layer is disposed on the substrate, the active layer comprises an active region and an inactive region which are arranged at intervals, the active region comprises a source region, a drain region and a channel region; A gate structure, disposed above the active area; The variable resistor is arranged above the inactive area.

2. The semiconductor device according to claim 1, wherein: The variable resistor includes a first variable resistor and / or a second variable resistor, The first variable resistor is connected to the gate structure, and the second variable resistor is connected between the source region and the drain region.

3. The semiconductor device according to claim 2, characterized in that The non-active area includes a shallow trench isolation structure, The first variable resistor and the second variable resistor are respectively disposed above the shallow trench isolation structure.

4. The semiconductor device according to claim 1, wherein: The variable resistor includes a semiconductor resistor portion and an electrode portion. The electrode portion is disposed adjacent to the semiconductor resistor portion, and the electrode portion receives an adjustment voltage and generates a corresponding electric field based on the adjustment voltage to adjust the size of a depletion region in the semiconductor resistor portion close to the electrode portion, thereby changing the resistance of the semiconductor resistor portion.

5. The semiconductor device according to claim 4, characterized in that The semiconductor resistor portion includes N-type doped polysilicon or P-type doped polysilicon.

6. The semiconductor device according to claim 4, characterized in that The electrode portion includes two electrode portions respectively disposed on both sides of the semiconductor resistor portion.

7. The semiconductor device according to claim 4, characterized in that The variable resistor includes a gate isolation dielectric layer disposed between the semiconductor resistor portion and the electrode portion.

8. The semiconductor device according to claim 7, characterized in that The electrode portion is a metal electrode manufactured by a gate-last process.

9. A method for preparing a semiconductor device, characterized in that: providing a substrate; An active layer is formed on the substrate, and active regions and inactive regions are defined in the active layer. forming a gate structure above the active area; and A variable resistor is fabricated over the inactive region.

10. The method according to claim 9, characterized in that The step of fabricating a variable resistor above the inactive region comprises: forming a source region, a drain region and a channel region in the active region; Fabricating a first variable resistor and / or a second variable resistor on the inactive region; and The first variable resistor is connected to the gate structure, and the second variable resistor is connected between the source region and the drain region.

11. The method according to claim 10, characterized in that The non-active area includes a shallow trench isolation structure, The step of manufacturing the first variable resistor and / or the second variable resistor above the inactive region comprises: The first variable resistor and / or the second variable resistor are manufactured above the shallow trench isolation structure.

12. The method according to claim 9, characterized in that The step of fabricating a gate structure above the active area and fabricating a variable resistor above the inactive area comprises: forming at least one first polysilicon structure over the inactive region, and forming a second polysilicon structure over the active region; removing a portion of the first polysilicon structure to form at least one first accommodation cavity, and removing the second polysilicon structure to form a second accommodation cavity; A conductive material is filled in the at least one first accommodating cavity to form an electrode portion of the variable resistor, and a conductive material is filled in the second accommodating cavity to form a gate structure, wherein the remaining portion of the first polysilicon structure serves as a semiconductor resistor portion of the variable resistor, and the electrode portion receives an adjustment voltage and generates a corresponding electric field based on the adjustment voltage to adjust the size of a depletion region in the semiconductor resistor portion close to the electrode portion, thereby changing the resistance of the semiconductor resistor portion.

13. The method according to claim 12, characterized in that The removing a portion of the first polysilicon structure to form at least one first accommodating cavity comprises: Portions on both sides of the first polysilicon structure are removed to form two first accommodating cavities.

14. The method according to claim 12, characterized in that The electrode portion for filling the at least one first accommodating cavity with a conductive material to form the variable resistor includes: A gate isolation dielectric layer is deposited on the cavity wall of the first accommodating cavity, and then a conductive material is filled in the first accommodating cavity as the electrode portion.

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