Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention discloses a solar cell, a preparation method thereof and a photovoltaic module. The preparation method comprises the following steps: providing a silicon wafer; forming a doping structure on the surface of the silicon wafer; forming a patterned mask on the doped structure; forming a dielectric layer on the surface of the doping structure and the surface of the mask; the mask and the dielectric layer on the surface of the mask are removed, and a window penetrating to the doping structure in the thickness direction of the silicon wafer is formed in the dielectric layer; and preparing an electrode in contact with the doping structure at the window of the dielectric layer. According to the method, the patterned mask is prepared firstly, then the dielectric layer is deposited, and the mask is removed to form the window, so that the damage caused by windowing of the dielectric layer by adopting processes such as laser can be remarkably reduced, the growth of a subsequent electrode is ensured, a metalized structure with excellent electrical performance can be obtained, and the battery efficiency and the module power are improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cells, and in particular relates to a solar cell, a preparation method thereof and a photovoltaic module. Background Art

[0002] With the rapid development of the photovoltaic industry, the performance and efficiency requirements of solar cells in the domestic and foreign photovoltaic markets are also constantly increasing, and industry manufacturers have focused on the research and development of high-efficiency batteries. Electrode metallization is one of the important processes of crystalline silicon solar cells.

[0003] In the existing metallization process, the dielectric layer is usually prepared first, then the dielectric layer is patterned (i.e., the window opening process), and finally the electrode is prepared in the window. The patterning process usually uses high-temperature processes such as lasers to form windows. During the patterning process, the silicon wafer will inevitably be damaged, thereby affecting the subsequent growth of the electrode at the window, resulting in excessive contact resistance and significantly reducing the fill factor of the battery, resulting in reduced battery efficiency and component efficiency.

[0004] Therefore, in view of the above technical problems, it is necessary to provide a solar cell, a preparation method thereof and a photovoltaic module. Summary of the invention

[0005] The object of the present invention is to provide a solar cell, a preparation method thereof and a photovoltaic module, so as to obtain a metallized structure with excellent electrical performance and improve the cell efficiency and module power.

[0006] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows: A method for preparing a solar cell, the method comprising the following steps: Provide silicon wafers; forming a doping structure on the surface of the silicon wafer; forming a patterned mask on the doped structure; forming a dielectric layer on the surface of the doping structure and the surface of the mask; Removing the mask and the dielectric layer on the surface of the mask, and forming a window in the dielectric layer that penetrates the doping structure along the thickness direction of the silicon wafer; An electrode in contact with the doping structure is prepared at the window of the dielectric layer.

[0007] In one embodiment, the width of the mask gradually decreases from the surface of the doping structure toward the outside along the thickness direction of the silicon wafer.

[0008] In one embodiment, the mask includes a mask bottom surface in contact with the surface of the doping structure, a mask top surface located above the mask, and two mask side surfaces connecting the mask top surface and the mask bottom surface, the width L1 of the mask top surface is smaller than the width L2 of the mask bottom surface, and the projection of the mask top surface on the plane where the mask bottom surface is located is located within the mask bottom surface area.

[0009] In one embodiment, the top surface of the mask is a plane; or, the top surface of the mask is a curved surface that is bent away from the doping structure.

[0010] In one embodiment, the side surface of the mask is a plane; or, the side surface of the mask is a curved surface.

[0011] In one embodiment, the mask is a paraffin mask.

[0012] In one embodiment, the paraffin mask is formed by inkjet printing or screen printing; and, The paraffin mask is removed by alkaline washing with an alkaline solution, and the alkaline washing temperature is 60° C. to 80° C.

[0013] In one embodiment, the width of the window gradually decreases from the bottom of the window to the top of the window.

[0014] In one embodiment, the width L3 of the top of the window is smaller than the width L4 of the bottom of the window, and the projection of the top of the window on the surface of the doping structure is located within the bottom area of ​​the window.

[0015] In one embodiment, the mask includes a mask bottom surface in contact with the surface of the doping structure, a mask top surface located above the mask, and two mask side surfaces connecting the mask top surface and the mask bottom surface, the width L1 of the mask top surface is 3μm to 20μm, and the width L2 of the mask bottom surface is 8μm to 30μm; and / or, The height of the mask is 1 μm to 5 μm; and / or, The width L3 of the top of the window is 5 μm to 25 μm, and the width L4 of the bottom of the window is 8 μm to 30 μm; and / or, The depth of the window is 30nm~100nm.

[0016] In one embodiment, the dielectric layer is deposited by hot wire CVD process, and the deposition temperature is 25° C. to 60° C.; and / or, The deposition thickness of the dielectric layer is smaller than the height of the mask.

[0017] In one embodiment, the dielectric layer includes SiN X 、SiO X 、SiNO X, Al2O3, ZrO2, MgF2, and the thickness of the dielectric layer is 30nm~100nm.

[0018] In one embodiment, the dielectric layer includes an outer dielectric layer and an inner dielectric layer, and the refractive index of the inner dielectric layer is greater than or equal to the refractive index of the outer dielectric layer.

[0019] In one embodiment, the preparation method further comprises: The silicon wafer after removing the mask is annealed at a temperature of 180° C. to 220° C. for a time of 10 min to 30 min.

[0020] In one embodiment, the electrode is partially located in the window, and partially located outside the window and extending onto the surface of the dielectric layer.

[0021] In one embodiment, the solar cell is any one of a HJT cell, a PERC cell, a TOPCon cell, and an IBC cell.

[0022] In one embodiment, the doping structure includes an intrinsic layer, a doping layer and a transparent conductive layer stacked in sequence on the surface of the silicon wafer, the window penetrates the transparent conductive layer along the thickness direction of the silicon wafer, and the electrode contacts the transparent conductive layer.

[0023] In one embodiment, the thickness of the transparent conductive layer is 15nm to 150nm; and / or, The transparent conductive layer is a combination of one or more of ITO, VTTO, IWO, HITO, VTZO, AMTO and TTO.

[0024] In one embodiment, the preparation of the electrode includes: A seed layer is prepared at the window of the dielectric layer by using an electroplating or chemical plating process; The first metal layer is prepared on the outer side of the seed layer by electroplating or chemical plating.

[0025] In one embodiment, the preparation of the electrode further comprises: The second metal layer is prepared on the outer sides of the seed layer and the first metal layer by using an electroplating or chemical plating process.

[0026] In one embodiment, the material of the seed layer and the first metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, and Sn; and / or, The total thickness of the seed layer and the first metal layer is 1 μm to 15 μm; and / or, The thickness of the seed layer is 100nm to 500nm; and / or, The thickness of the seed layer is greater than or equal to the thickness of the dielectric layer.

[0027] In one embodiment, the material of the second metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, and Sn; and / or, The thickness of the second metal layer is 1 μm to 5 μm.

[0028] Another embodiment of the present invention provides a technical solution as follows: A solar cell, comprising a silicon wafer and a doping structure located on a surface of the silicon wafer, the solar cell further comprising a dielectric layer stacked on the doping structure and an electrode in contact with the doping structure, a window penetrating the doping structure along the thickness direction of the silicon wafer is formed on the dielectric layer, the width L3 of at least one of the tops of the window is smaller than the width L4 of the bottom of the window, and the projection of the top of the window on the surface of the doping structure is located within the bottom region of the window.

[0029] In one embodiment, a width of at least one of the windows gradually decreases from the bottom of the window to the top of the window.

[0030] In one embodiment, the electrode includes a first electrode portion located in the window and in contact with the doping structure, the top surface of the first electrode portion is flush with the top of the window, and the bottom surface of the first electrode portion is flush with the bottom of the window.

[0031] In one embodiment, the width of the top surface of the first electrode portion is smaller than the width of the bottom surface of the first electrode portion, and the projection of the top surface of the first electrode portion on the plane where the bottom surface of the first electrode portion is located is located within the bottom surface area of ​​the first electrode portion.

[0032] In one embodiment, the first electrode portion is located in all of the windows.

[0033] In one embodiment, the electrode further includes a second electrode portion located above the first electrode portion and extending to the surface of the dielectric layer, and a maximum width of the second electrode portion is greater than a maximum width of the first electrode portion.

[0034] In one embodiment, the width of the top surface of the second electrode portion is smaller than the width of the bottom surface of the second electrode portion, and the projection of the top surface of the second electrode portion on the plane where the bottom surface of the second electrode portion is located is located within the bottom surface area of ​​the second electrode portion.

[0035] In one embodiment, the side wall of the window is a plane; or, the side wall of the window is a curved surface.

[0036] In one embodiment, the bottom surface of the first electrode portion is flush with the surface of the doping structure; or, A groove is formed on the surface of the doping structure away from the silicon wafer, and the bottom surface of the first electrode portion is lower than the bottom surface of the dielectric layer and contacts with the bottom surface of the groove.

[0037] In one embodiment, the width L3 of the top of the window is 5 μm to 25 μm, and the width L4 of the bottom of the window is 8 μm to 30 μm; and / or, The depth of the window is 30nm ~ 100nm.

[0038] In one embodiment, the dielectric layer includes SiN X 、SiO X 、SiNO X , Al2O3, ZrO2, MgF2, and the thickness of the dielectric layer is 30nm ~ 100nm.

[0039] In one embodiment, the dielectric layer includes an outer dielectric layer and an inner dielectric layer, and the refractive index of the inner dielectric layer is greater than or equal to the refractive index of the outer dielectric layer.

[0040] In one embodiment, the distance between two adjacent electrodes on the same side of the silicon wafer is 500 μm to 1000 μm; and / or, The total thickness of the electrode is 5 μm to 20 μm.

[0041] In one embodiment, the electrode includes a seed layer at least partially located in the dielectric layer and a first metal layer located outside the seed layer, and the total thickness of the seed layer and the first metal layer is 1 μm to 15 μm.

[0042] In one embodiment, the seed layer has a thickness of 100 nm to 500 nm; and / or, The thickness of the seed layer is greater than or equal to the thickness of the dielectric layer; and / or, The material of the seed layer and the first metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, and Sn.

[0043] In one embodiment, the electrode also includes a seed layer coated on the outside of the window and a second metal layer outside the first metal layer, the material of the second metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, and Sn, and the thickness of the second metal layer is 1μm ~ 5μm.

[0044] In one embodiment, the solar cell is any one of a HJT cell, a PERC cell, a TOPCon cell, and an IBC cell.

[0045] In one embodiment, the doping structure includes an intrinsic layer, a doping layer and a transparent conductive layer stacked in sequence on the surface of the silicon wafer, the window penetrates the transparent conductive layer along the thickness direction of the silicon wafer, and the electrode contacts the transparent conductive layer.

[0046] In one embodiment, the thickness of the transparent conductive layer is 15nm to 150nm; and / or, The transparent conductive layer is a combination of one or more of ITO, VTTO, IWO, HITO, VTZO, AMTO and TTO.

[0047] Another embodiment of the present invention provides a technical solution as follows: A photovoltaic component comprises the above-mentioned solar cell.

[0048] Compared with the prior art, the present invention has the following beneficial effects: The present invention prepares a patterned mask first, then deposits a dielectric layer and removes the mask to form a window, which can significantly reduce the damage caused by using laser and other processes to open the window in the dielectric layer, ensure the subsequent growth of the electrode, and obtain a metallized structure with excellent electrical properties, thereby improving the battery efficiency and component power. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 This is a schematic diagram of the structure of a heterojunction battery in Comparative Example 1 of the present invention; Figure 2 Schematic diagram of the structure of a heterojunction battery in Example 1 of the present invention; Figure 3 for Figure 2 A partial enlarged schematic diagram of the M in the middle; Figure 4 is a schematic structural diagram of the first dielectric layer and the first mask in Embodiment 1 of the present invention; Figure 5 is a schematic structural diagram of the first transparent conductive layer and the first dielectric layer in Example 1 of the present invention; Figure 6 is a schematic structural diagram of the first electrode in Example 1 of the present invention; Figure 7 is another structural schematic diagram of the first electrode in Example 1 of the present invention; Figure 8a~8fis a process flow chart of the heterojunction battery preparation method in Example 1 of the present invention; Fig. 9 This is a schematic diagram of the structure of a heterojunction battery in Comparative Example 2 of the present invention; Fig.10 for Fig. 9 A local enlarged schematic diagram of the middle A; Fig.11 It is a schematic diagram of the structure of the first transparent conductive layer and the first dielectric layer in Comparative Example 2 of the present invention; Fig.12 Schematic diagram of the structure of the first electrode in Comparative Example 2 of the present invention; Figure 13a~13e It is a process flow chart of the heterojunction battery preparation method in Comparative Example 2 of the present invention; Fig.14 Schematic diagram of the structure of a heterojunction battery in Example 3 of the present invention; Fig.15 for Fig.14 A local enlarged schematic diagram of the N position in the middle; Fig.16 Schematic diagram of the structure of the first transparent conductive layer, the first dielectric layer and the first electrode in Embodiment 4 of the present invention; Fig.17 is a schematic structural diagram of the first transparent conductive layer in Example 4 of the present invention; Fig.18 is a schematic structural diagram of the first dielectric layer and the first mask in Example 5 of the present invention; Fig.19 is a schematic structural diagram of the first transparent conductive layer and the first dielectric layer in Example 5 of the present invention; Fig. 20 is a schematic structural diagram of the first dielectric layer and the first mask in Embodiment 6 of the present invention; Fig.21 Schematic diagram of the structure of the first transparent conductive layer and the first dielectric layer in Example 6 of the present invention; Fig. 22 Schematic diagram of the structure of the first transparent conductive layer, the first dielectric layer and the first electrode in Example 6 of the present invention.

[0051] Comparative Example 1 Description of reference numerals: 10'-silicon wafer, 21'-first intrinsic layer, 22'-second intrinsic layer, 31'-first doped layer, 32'-second doped layer, 41'-first transparent conductive layer, 42'-second transparent conductive layer, 51'-first electrode, 52'-second electrode; Explanation of the reference numerals in Comparative Example 2 and Examples 1 to 6: 10 - silicon wafer, 21 - first intrinsic layer, 22 - second intrinsic layer, 31 - first doped layer, 32 - second doped layer, 41 - first transparent conductive layer, 411 - groove, 42 - second transparent conductive layer, 501 - inner dielectric layer, 502 - outer dielectric layer, 51 - first dielectric layer, 511 - first window, 52 - second dielectric layer, 521 - second window, 601 - seed layer, 602 - first metal layer, 603 - second metal layer, 61 - first electrode, 611 - first electrode portion, 612 - second electrode portion, 62 - second electrode, 71 - first mask, 711 - bottom surface of mask, 712 - top surface of mask, 713 - side surface of mask, 72 - second mask. DETAILED DESCRIPTION

[0052] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0053] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0054] The present invention discloses a method for preparing a solar cell, comprising the following steps: Provide silicon wafers; forming a doping structure on the surface of the silicon wafer; forming a patterned mask over the doped structure; forming a dielectric layer on a surface of the doped structure and a surface of the mask; The mask and the dielectric layer on the surface thereof are removed, and a window penetrating to the doping structure along the thickness direction of the silicon wafer is formed in the dielectric layer; An electrode in contact with the doping structure is prepared at the window of the dielectric layer.

[0055] The present invention also discloses a solar cell, comprising a silicon wafer and a doping structure located on the surface of the silicon wafer. The solar cell also comprises a dielectric layer stacked on the doping structure and an electrode in contact with the doping structure. A window is formed on the dielectric layer and penetrates the doping structure along the thickness direction of the silicon wafer. The width L3 of at least one window top is smaller than the width L4 of the window bottom, and the projection of the window top on the surface of the doping structure is located within the window bottom area.

[0056] The invention also discloses a photovoltaic assembly, comprising the solar cell mentioned above.

[0057] The present invention prepares a patterned mask first, then deposits a dielectric layer and removes the mask to form a window, which can significantly reduce the damage caused by using laser and other processes to open the window on the dielectric layer, ensure the subsequent growth of the electrode, and obtain a metallization structure with excellent electrical performance. The fill factor and open circuit voltage are both improved, thereby improving the battery efficiency and component power. The present invention can achieve a finer grid line design by forming a patterned dielectric layer on the doped structure, thereby further improving the battery efficiency and component power. At the same time, the patterned dielectric layer is used as a mask for preparing electrodes, eliminating the need for expensive photosensitive inks, greatly reducing process costs, and the dielectric layer can protect the transparent conductive layer underneath to prevent corrosion of the transparent conductive layer.

[0058] The present invention is further described below with reference to specific examples.

[0059] Comparative Example 1: The solar cell in this comparative example is described by taking a heterojunction cell as an example. Figure 1 The structure diagram of the heterojunction battery in this comparative example is shown, and the heterojunction battery includes: The silicon wafer 10' comprises a front side (i.e., a light-receiving side) and a back side (i.e., a backlight side) arranged opposite to each other; A first intrinsic layer 21', a first doped layer 31' and a first transparent conductive layer 41' stacked sequentially on the front surface; A second intrinsic layer 22', a second doped layer 32' and a second transparent conductive layer 42' sequentially stacked on the back surface; The first electrode 51' is in contact with the first transparent conductive layer 41'; The second electrode 52 ′ contacts the second transparent conductive layer 42 ′.

[0060] Exemplarily, the silicon wafer 10' is N-type doped; the first intrinsic layer 21' is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, and the first doped layer 31' is an N-type doped amorphous silicon layer or a microcrystalline silicon layer; the second intrinsic layer 22' is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, and the second doped layer 32' is a P-type doped amorphous silicon layer or a microcrystalline silicon layer; the first transparent conductive layer 41' and the second transparent conductive layer 42' can be a combination of one or more transparent conductive layers such as ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO, etc.; the first electrode 51' and the second electrode 52' are both conventional gate line electrodes. Example 1

[0061] The solar cell in this embodiment is described by taking a heterojunction cell as an example. Figure 2 , Figure 3 and Figure 8e , a schematic diagram of the structure of a heterojunction battery in this embodiment, the heterojunction battery comprises: A silicon wafer 10, comprising a front side (i.e., a light-receiving side) and a back side (i.e., a backlight side) arranged opposite to each other, wherein the front side and the back side respectively comprise a metal region and a non-metal region; A first intrinsic layer 21, a first doped layer 31 and a first transparent conductive layer 41 sequentially stacked on the front surface; A second intrinsic layer 22, a second doped layer 32, and a second transparent conductive layer 42 sequentially stacked on the back surface; A first dielectric layer 51 and a first electrode 61. A first window 511 penetrating to the surface of the first transparent conductive layer 41 is provided in the metal region of the first dielectric layer 51. The first electrode 61 penetrates the first window 511 in the first dielectric layer 51 along the thickness direction of the silicon wafer and contacts the first transparent conductive layer 41. The second dielectric layer 52 and the second electrode 62 are provided with a second window 521 penetrating to the surface of the second transparent conductive layer 42 in the metal region of the second dielectric layer 52. The second electrode 62 penetrates the second window 521 in the second dielectric layer 52 along the thickness direction of the silicon wafer and contacts the second transparent conductive layer 42.

[0062] In this embodiment, the silicon wafer 10 is an N-type single crystal silicon wafer, with a resistivity of 0.5Ω·m to 3Ω·m, a thickness of 90μm to 120μm, and a size of 210mm. In other embodiments, double-sided texturing can be performed by an alkali texturing process to form a pyramid texturing light-trapping structure (not shown) on the surface, and the size of the pyramid structure is preferably 0.5μm to 5μm.

[0063] In this embodiment, the first intrinsic layer 21 and the second intrinsic layer 22 are intrinsic amorphous silicon layers or intrinsic microcrystalline silicon layers, the first doped layer 31 is an N-type doped (such as phosphorus-doped) amorphous silicon layer or microcrystalline silicon layer, and the second doped layer 32 is a P-type doped (such as boron-doped) amorphous silicon layer or microcrystalline silicon layer.

[0064] It is understandable that in other embodiments, the silicon wafer 10 may also be a P-type silicon wafer, in which case the first doped layer 31 is a P-type doped (such as boron-doped) amorphous silicon layer or microcrystalline silicon layer, and the second doped layer 32 is an N-type doped (such as phosphorus-doped) amorphous silicon layer or microcrystalline silicon layer.

[0065] In this embodiment, the first transparent conductive layer 41 and the second transparent conductive layer 42 can be a combination of one or more transparent conductive layers such as ITO, VTTO, IWO, HITO, VTZO, AMTO, TTO, etc., preferably an ITO transparent conductive layer; the thickness is 15nm~150nm, preferably 40nm.

[0066] The silicon wafer, intrinsic layer, doped layer and transparent conductive layer in this embodiment are exactly the same as those in comparative example 1 and will not be described again here. The difference from comparative example 1 is that a first dielectric layer 51 and a second dielectric layer 52 are added in this embodiment, and the structures of the first electrode 61 and the second electrode 62 are also different.

[0067] The second dielectric layer 52 and the second electrode 62 are completely the same as the first dielectric layer 51 and the first electrode 61. Figure 2 , Figure 3 Combined with Figures 5 to 7 As shown, the first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer are taken as an example for detailed description.

[0068] In this embodiment, the first dielectric layer 51 includes SiN X 、SiO X 、SiNO X , Al2O3, ZrO2, MgF2, etc., or a multi-layer composite film. The thickness of the first dielectric layer 51 is 30nm-100nm. When the first dielectric layer 51 is a multi-layer composite film structure, it includes an outer dielectric layer and an inner dielectric layer. The refractive index of the inner dielectric layer is greater than or equal to the refractive index of the outer dielectric layer.

[0069] Ginseng Figure 3 , Figure 5 As shown, the first dielectric layer 51 in this embodiment is SiN X layer, refractive index n is 1.95, thickness is 55nm, SiN X The layer can be deposited on the first transparent conductive layer 41 by using a hot wire CVD process.

[0070] Ginseng Figure 5As shown, a first window 511 is formed on the dielectric layer in this embodiment, which penetrates the first transparent conductive layer 41 along the thickness direction of the silicon wafer 10. The depth of the first window 511 is the thickness of the first dielectric layer 51. The width L3 of the top of the first window 511 is less than the width L4 of the bottom of the first window 511, and the projection of the top of the first window 511 on the surface of the first transparent conductive layer 41 is located in the bottom area of ​​the first window 511. Preferably, the width L3 of the top of the first window 511 is 5μm to 25μm, and the width L4 of the bottom of the first window 511 is 8μm to 30μm. Exemplarily, L3 can be 15μm, L4 can be 20μm, and the depth of the first window 511 is 55nm.

[0071] In this embodiment, the first electrode 61 is a gate line electrode. Figure 2 , Figure 3 and Figure 6 As shown, the first electrode 61 includes a first electrode portion 611 extending along the thickness direction of the silicon wafer to the inside of the first dielectric layer 51 and in contact with the first transparent conductive layer 41, and a second electrode portion 612 located above the first electrode portion 611 and extending to the surface of the first dielectric layer 51, and the maximum width of the second electrode portion 612 is greater than the maximum width of the first electrode portion 611. In addition, the surface of the first transparent conductive layer 41 away from the silicon wafer is a plane, and the bottom surface of the first electrode portion 611 is flush with the bottom surface of the first dielectric layer 51.

[0072] It can be understood that, in this embodiment, the first electrode portion 611 is located in the entire first window 511, that is, the first electrode portion 611 completely fills the first window 511, and in other embodiments, the first electrode portion 611 may also be located in part of the first window 511, that is, the first electrode portion 611 does not completely fill the first window 511.

[0073] In addition, the silicon wafer surface in this embodiment is explained by taking the polished surface as an example. In the actual battery structure, the silicon wafer surface is usually prepared with a light-trapping velvet structure, that is, the silicon wafer surface is non-planar. For example, a pyramid velvet light-trapping structure can be formed on the silicon wafer surface through an alkali velveting process. At this time, the surface of the first transparent conductive layer 41 deposited thereon away from the silicon wafer also has a corresponding pyramid structure. At this time, the bottom surface of the first electrode portion 611 corresponds to the velvet light-trapping structure, and the bottom surface of the first electrode portion 611 is flush with the bottom surface of the first dielectric layer 51, that is, the overall structure is roughly the same as a whole velvet light-trapping structure.

[0074] Further, the width W31 of the top surface of the first electrode portion 611 is smaller than the width W32 of the bottom surface of the first electrode portion 611, and the projection of the top surface of the first electrode portion 611 on the plane where the bottom surface of the first electrode portion 611 is located is located in the bottom surface area of ​​the first electrode portion 611, the width W1 of the top surface of the second electrode portion 612 is smaller than the width W2 of the bottom surface of the second electrode portion 612, and the projection of the top surface of the second electrode portion 612 on the plane where the bottom surface of the second electrode portion 612 is located is located in the bottom surface area of ​​the second electrode portion 612, and the side surfaces of the first electrode portion 611 and the second electrode portion 612 are both substantially inclined. At the same time, the maximum width of the second electrode portion 612 (i.e., W2) is greater than the maximum width of the first electrode portion 611 (i.e., W32).

[0075] Preferably, the width W31 of the top surface of the first electrode portion 611 is 5μm ~ 25μm, the width W32 of the bottom surface of the first electrode portion 611 is 8μm ~ 30μm, the width W1 of the top surface of the second electrode portion 612 is 8μm ~ 40μm, the width W2 of the bottom surface of the second electrode portion 612 is 10μm ~ 50μm, the thickness of the first electrode portion 611 is 30nm ~ 100nm, the total thickness of the first electrode portion 611 and the second electrode portion 612 is 5μm ~ 20μm, and the spacing between two adjacent electrodes on the same side of the silicon wafer is 500μm ~ 1000μm.

[0076] In some embodiments, the side surfaces of the first electrode portion 611 and the second electrode portion 612 may be other shapes, and the top surface of the second electrode portion 612 may also be other shapes, such as a regular or irregular curved surface, etc. Any technical solutions that satisfy the conditions that the width W31 of the top surface of the first electrode portion 611 is less than the width W32 of the bottom surface of the first electrode portion 611 and the maximum width of the second electrode portion 612 is greater than the maximum width of the first electrode portion 611 shall fall within the scope of protection of the present invention.

[0077] Specifically, exemplarily, the first electrode portion 611 in this embodiment has the same size as the first window 511, the width W31 of the top surface of the first electrode portion 611 is 15 μm, the width W32 of the bottom surface of the first electrode portion 611 is 20 μm, the width W1 of the top surface of the second electrode portion 612 is 30 μm, the width W2 of the bottom surface of the second electrode portion 612 is 40 μm, and the thickness of the first electrode portion 611 is 55 nm.

[0078] In addition, in this embodiment, the total thickness of the first electrodes is 5 μm to 20 μm, preferably 10 μm, and the distance between two adjacent first electrodes is 500 μm to 1000 μm.

[0079] The first electrode in the present invention is a gate line electrode, which can be a main gate line or a fine gate line. The line width and spacing of the main gate line and the fine gate line are designed according to actual needs and will not be described in detail here.

[0080] Ginseng Figure 7 As shown, the first electrode 61 in this embodiment is prepared by electroplating or chemical plating process, and the first electrode 61 includes a seed layer 601 at least partially located in the first dielectric layer and a first metal layer 602 located outside the seed layer 601, the first metal layer 602 partially covers the top of the seed layer 601, and partially covers the side of the seed layer 601 and contacts with the surface of the first dielectric layer 51 below, and the total thickness of the seed layer 601 and the first metal layer 602 is 1μm ~ 15μm. Further, the first electrode 61 also includes the seed layer 601 coated outside the first window 511 and the second metal layer 603 outside the first metal layer 602, that is, in the overall structure composed of the seed layer 601 and the first metal layer 602, the part located outside the first window 511 is coated by the second metal layer 603, and the two sides of the second metal layer 603 contact with the surface of the first dielectric layer 51 below.

[0081] Specifically, the seed layer 601 and the first metal layer 602 are made of the same material, which can be one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc., and the thickness of the seed layer is 100nm to 500nm; the second metal layer 603 is made of one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc., and the thickness of the second metal layer is 1μm to 5μm. Preferably, the seed layer 601 and the first metal layer 602 are both Cu metal layers, and the total thickness of the seed layer 601 and the first metal layer 602 is 7μm, the second metal layer 603 is a Sn metal layer, and the thickness is 3μm, and the total thickness of the entire first electrode is 10μm.

[0082] In a preferred embodiment, the thickness of the seed layer 601 is greater than the thickness of the first dielectric layer 51 (i.e., the depth of the first window 511), and the seed layer prepared in this way not only fills the inside of the first window 511, but also covers the surface of the first dielectric layer 51 beside the first window 511, so as to facilitate the subsequent preparation of the first metal layer 602 on the seed layer 601. In this case, the first electrode portion 611 is entirely the seed layer, the outer side of the second electrode portion 612 is the second metal layer, and the inner side is the first metal layer and part of the seed layer.

[0083] In other embodiments, the thickness of the seed layer may also be equal to the thickness of the first dielectric layer 51 , or less than the thickness of the first dielectric layer 51 , so that the seed layer is only formed inside the first window 511 .

[0084] The first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer in this embodiment are described in detail above. The second dielectric layer 52 and the second electrode 62 on the back side of the silicon wafer are exactly the same as the first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer, and will not be described again here.

[0085] Furthermore, the first electrode 61 and the second electrode 62 in the present invention can also be prepared by screen printing process, by printing conductive paste at the window of the dielectric layer and forming a metallization structure after curing. The electrode material can be one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, Sn, etc. The screen printing process is a conventional process and will not be described here.

[0086] The preparation method of the heterojunction battery in this embodiment is as follows: 1. Ginseng Figure 8a As shown, a silicon wafer is provided.

[0087] The silicon wafer 10 in this embodiment is an N-type single crystal silicon wafer, with a resistivity of 0.5Ω·m to 3Ω·m, a thickness of 90μm to 120μm, and a size of 210mm.

[0088] Preferably, the silicon wafer 10 is double-sided texturing by an alkali texturing process, specifically: The surface oxide layer is removed by using a 5% diluted HF solution, and a pyramid velvet light-trapping structure (not shown) is formed on the surface by anisotropic etching of single crystal silicon using KOH or NaOH or tetramethylammonium hydroxide (TMAH) plus alcohol. Preferably, the size of the pyramid structure is preferably 0.5μm ~ 5μm.

[0089] 2. Ginseng Figure 8b As shown, a first intrinsic layer 21 , a first doped layer 31 and a first transparent conductive layer 41 are sequentially formed on the front side of the silicon wafer 10 , and a second intrinsic layer 22 , a second doped layer 32 and a second transparent conductive layer 42 are sequentially formed on the back side of the silicon wafer 10 .

[0090] Preferably, in this embodiment, the intrinsic layer and the doping layer are deposited by a plasma chemical vapor deposition (PECVD) process, and the transparent conductive layer is deposited by a reactive plasma deposition (RPD) process or a magnetron sputtering process, as follows: First, SiH4 (silane) gas is introduced into a vacuum chamber, and an intrinsic amorphous silicon layer is formed on the entire front area of ​​the silicon wafer 10 by a PECVD process, and then SiH4 gas, H2 gas and PH3 (phosphine) gas are introduced into the vacuum chamber, and an N-type doped amorphous silicon layer is formed on the intrinsic amorphous silicon layer by a PECVD process; Then, the wafer is turned over, the tray is changed, SiH4 (silane) gas is introduced into the vacuum chamber, and an intrinsic amorphous silicon layer is formed on the entire back side of the silicon wafer 10 by a PECVD process. Then, SiH4 gas, H2 gas and B2H6 (diborane) gas are introduced into the vacuum chamber, and a P-type doped amorphous silicon layer is formed on the intrinsic amorphous silicon layer by a PECVD process. Finally, the N-type doped amorphous silicon layer and the P-type doped amorphous silicon layer are coated by reactive plasma deposition (RPD) or magnetron sputtering. The back side is shielded by the edge of the carrier design (shielded by a mask), and the specific shielding area around is 0.8 mm. The transparent conductive layer is an ITO (99.5:0.5) layer with a thickness of 40 nm.

[0091] In this embodiment, the carrier concentration of the first transparent conductive layer 41 and the second transparent conductive layer 42 is 0.6E20cm -3 ~5E20cm -3 , preferably 3E20cm -3 , the mobility is 30cm 2 / Vs ~ 120cm 2 / Vs, preferably 80cm 2 / Vs, contact resistivity is 0.8mΩ·cm 2 ~ 4mΩ·cm 2 , preferably 2 mΩ·cm 2 , the refractive index is 1.9 ~ 2.1.

[0092] 3. Ginseng Figure 8c As shown, a patterned first mask 71 and a second mask 72 are formed on the metal regions of the first transparent conductive layer 41 and the second transparent conductive layer 42, respectively.

[0093] In this embodiment, the materials of the first mask 71 and the second mask 72 are acid-resistant but not alkali-resistant, and do not react with the transparent conductive layer thereunder. For example, in this embodiment, paraffin mask is used as an example for description.

[0094] Specifically, taking the first mask 71 as an example, the mask is a paraffin mask, which is formed by an inkjet printing process or a screen printing process. During the printing / printing process, the paraffin is in a fluid state and is affected by factors such as the surface tension of the transparent conductive layer. The paraffin mask will form a structure that is narrow at the top and wide at the bottom.

[0095] like Figure 4 As shown, in this embodiment, the width of the first mask gradually decreases from the bottom to the top, and the cross section of the mask is roughly an isosceles trapezoidal structure. Specifically, the first mask includes a mask bottom surface 711 in contact with the surface of the doping structure below, a mask top surface 712 located above the mask structure, and two mask side surfaces 713 connecting the mask bottom surface 711 and the mask top surface 712.

[0096] Exemplarily, the width L1 of the mask top surface 712 is 3 μm to 20 μm, the width L2 of the mask bottom surface 711 is 8 μm to 30 μm, and the height H of the first mask 71 is 1 μm to 5 μm. For example, in this embodiment, L1 is 10 μm, L2 is 20 μm, and H is 2.5 μm. The structure and preparation process of the second mask 72 are exactly the same as those of the first mask 71, and will not be described again here.

[0097] 4. Ginseng Figure 8d As shown, a first dielectric layer 51 is formed on the surface of the first transparent conductive layer 41 and the first mask 71 , and a second dielectric layer 52 is formed on the surface of the second transparent conductive layer 42 and the second mask 72 .

[0098] In the present invention, a low temperature deposition process is used to deposit a first dielectric layer 51 and a second dielectric layer 52 on the front and back sides respectively. The dielectric layer material has the property of being alkali-resistant. The dielectric layer can be SiN X 、SiO X 、SiNO X , Al2O3, ZrO2, MgF2, etc., or it can be a multi-layer composite film.

[0099] Since the melting point of paraffin wax is generally between 40°C and 64°C, in this embodiment, a paraffin wax mask is prepared first, and then the dielectric layer is deposited. During the deposition of the dielectric layer, the paraffin wax mask needs to be kept in a solid state, so the deposition temperature cannot be higher than the melting point of the paraffin wax. Therefore, in this embodiment, a hot wire CVD process is preferably used for deposition, and the deposition temperature is 25°C to 60°C, preferably 25°C to 40°C. For example, when SiN is deposited at 40°C, X layer.

[0100] It is understandable that other commonly used dielectric layer deposition processes in the art that can ensure the paraffin morphology are also applicable and are not limited here.

[0101] In addition, the inventors creatively discovered that when the thickness of the paraffin mask is higher than the thickness of the dielectric layer, even after the paraffin mask is formed and the dielectric layer is deposited, the dielectric layer will not form a dense coverage on the surface of the paraffin mask, that is, part of the surface of the paraffin will be exposed. Therefore, the paraffin mask can be easily removed in subsequent steps without affecting the surface morphology of the dielectric layer at other locations.

[0102] Therefore, preferably, the deposition thickness of the dielectric layer is less than the height of the paraffin mask. In this case, it is easier to form a window penetrating to the transparent conductive layer in the subsequent process. For example, the deposition thickness of the dielectric layer in this embodiment is 55 nm.

[0103] 5. Ginseng Figure 8eAs shown, the mask and the dielectric layer on its surface are removed, and a window is formed in the dielectric layer that penetrates through the transparent conductive layer along the thickness direction of the silicon wafer.

[0104] Taking the first mask 71 and the first dielectric layer 51 as an example, since the first mask 71 is acid-resistant but not alkali-resistant, and the first dielectric layer 51 is alkali-resistant, an alkali solution is used in the present invention to perform alkali washing to remove the first mask 71. When the first mask 71 is removed by alkali washing, the first dielectric layer 51 above it is also removed synchronously, and finally only the first dielectric layer 51 beside the first mask 71 is retained.

[0105] Specifically, the alkaline solution may be a NaOH or KOH solution with a mass fraction of 30% to 50%, the alkaline washing temperature is 60° C. to 80° C., and the alkaline washing time is 50s to 200s. For example, a NaOH solution with a mass fraction of 40% may be selected for alkaline washing at 70° C. for 100s. It is understood that the alkaline solution may also be other alkaline solutions similar to NaOH and KOH solutions that can dissolve the first mask 71 and do not damage the first dielectric layer 51, and no specific limitation is made here.

[0106] Combination Figure 5 As shown, after the first mask 71 and the first dielectric layer 51 thereon are removed, a first window 511 which is narrow at the top and wide at the bottom is formed on the first dielectric layer 51. Considering that the dielectric layer is relatively thin, the upper surface of the first dielectric layer 51 can be approximately a plane. In a specific process, the top surface of the first dielectric layer 51 is not necessarily a plane near the first window 511, but this does not affect the formation of the first window 511 and will not be described in detail here.

[0107] In addition, when a velvet light-trapping structure is formed on the surface of the silicon wafer, the velvet light-trapping structure will affect the formed first window 511, resulting in the first window 511 being irregular in shape. Not all first windows are narrow at the top and wide at the bottom.

[0108] In this embodiment, the depth of the first window 511 is the thickness of the first dielectric layer 51, the width L3 of the top of the first window 511 is less than the width L4 of the bottom of the first window 511, and the projection of the top of the first window 511 on the surface of the first transparent conductive layer 41 is located in the bottom area of ​​the first window 511. Preferably, the width of the first window 511 gradually decreases from the bottom of the window to the top of the window, the width L3 of the top of the first window 511 is 5μm to 25μm, and the width L4 of the bottom of the first window 511 is 8μm to 30μm. Exemplarily, L3 in this embodiment is 15μm, L4 is 20μm, and the depth of the first window 511 is 55nm.

[0109] The structure and preparation process of the second window 521 are identical to those of the first window 511, and will not be described again. Preferably, in this embodiment, the first mask and the second mask are removed simultaneously in a one-step process using an alkaline solution to form the first window 511 and the second window 521 simultaneously.

[0110] Furthermore, in this embodiment, the silicon wafer after the mask is removed by alkali washing is annealed in an annealing furnace, the annealing temperature is 180° C. to 220° C., and the annealing time is 10 min to 30 min. A densified film layer can be formed through the annealing process.

[0111] 6. Ginseng Figure 8f Combined with Figure 6 , Figure 7 As shown, a first electrode 61 in contact with the first transparent conductive layer 41 is prepared at the first window 511 of the first dielectric layer 51, and a second electrode 62 in contact with the second transparent conductive layer 42 is prepared at the second window 521 of the second dielectric layer 52. Taking the preparation of the first electrode 61 as an example, it specifically includes: First, a seed layer 601 is prepared at the first window 511 of the first dielectric layer 51 by using an electroplating or chemical plating process; Then, a first metal layer 602 is formed on the outer side of the seed layer 601 by electroplating or chemical plating; Finally, the second metal layer 603 is formed on the outer sides of the seed layer 601 and the first metal layer 602 by electroplating or chemical plating.

[0112] The seed layer 601 is described by taking copper as an example, and the thickness of the copper seed layer is 100nm to 500nm; The first metal layer 602 is electroplated copper as an example. The electroplating copper solution includes copper sulfate, sulfuric acid, copper balls, and additives that can optimize the crystal structure of the copper layer. 2+ The concentration of is 50g / L, the concentration of sulfuric acid is 40g / L, the thickness is 7μm, and the width is 15μm; The second metal layer 603 is electroplated with tin as an example. The electroplating tin solution includes tin methanesulfonate and a tin plating additive. 2+ The concentration of is 30 g / L, the concentration of methanesulfonic acid is 200 g / L, and the thickness is 3 μm.

[0113] Finally, the heterojunction battery was alkaline washed, and the prepared battery cell was subjected to light injection treatment. The temperature of the light injection treatment was 210° C., and the time of the light injection treatment was 90 s.

[0114] The electrode in this embodiment is illustrated by taking a seed layer and two metal layers as an example. In other embodiments, the electrode may also include only a seed layer and a first metal layer, or other metal layers may be further prepared outside the second metal layer, which will not be described in detail here.

[0115] It can be understood that the heterojunction battery in this embodiment is not limited to being manufactured using the preparation method in this embodiment.

[0116] Comparative Example 2: The solar cell in this comparative example is described by taking a heterojunction cell as an example. Fig. 9 , Fig.10 The structure diagram of the heterojunction battery in this comparative example is shown, and the heterojunction battery includes: A silicon wafer 10, comprising a front side (i.e., a light-receiving side) and a back side (i.e., a backlight side) arranged opposite to each other, wherein the front side and the back side respectively comprise a metal region and a non-metal region; A first intrinsic layer 21, a first doped layer 31 and a first transparent conductive layer 41 sequentially stacked on the front surface; A second intrinsic layer 22, a second doped layer 32, and a second transparent conductive layer 42 sequentially stacked on the back surface; A first dielectric layer 51 and a first electrode 61. The first dielectric layer 51 is provided with a first window in the metal region penetrating to the surface of the first transparent conductive layer 41. The first electrode 61 penetrates the first window in the first dielectric layer 51 along the thickness direction of the silicon wafer and contacts the first transparent conductive layer 41. The second dielectric layer 52 and the second electrode 62 , the second dielectric layer 52 is provided with a second window in the metal region penetrating to the surface of the second transparent conductive layer 42 , the second electrode 62 penetrates the second window in the second dielectric layer 52 along the thickness direction of the silicon wafer and contacts the second transparent conductive layer 42 .

[0117] The silicon wafer, intrinsic layer, doped layer and transparent conductive layer in this comparative example are exactly the same as those in comparative example 1 and will not be described again here. The difference from comparative example 1 is that a first dielectric layer 51 and a second dielectric layer 52 are added in this comparative example, and the structures of the first electrode 61 and the second electrode 62 are also different.

[0118] The second dielectric layer 52 and the second electrode 62 are completely the same as the first dielectric layer 51 and the first electrode 61. Fig. 9 Combined with Figures 10 to 12 As shown, the first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer are taken as an example for detailed description.

[0119] The first dielectric layer 51 in this comparative example includes SiN X 、SiO X 、SiNO X, Al2O3, ZrO2, MgF2, etc., or a multi-layer composite film. The thickness of the first dielectric layer 51 is 30nm~100nm. When the first dielectric layer 51 is a multi-layer composite film structure, it includes an outer dielectric layer and an inner dielectric layer. The thickness of the inner dielectric layer is less than that of the outer dielectric layer, and the refractive index of the inner dielectric layer is greater than or equal to the refractive index of the outer dielectric layer.

[0120] Ginseng Fig.10 As shown, the first dielectric layer 51 in this comparative example is SiN X layer, refractive index n is 1.95, thickness is 55nm, SiN X The layer can be deposited on the first transparent conductive layer 41 by using a PECVD process.

[0121] Ginseng Fig.11 As shown, the first dielectric layer 51 is patterned by laser processing, and the first dielectric layer 51 in the metal area is completely removed to expose the first transparent conductive layer 41 below, thereby forming a plurality of first windows 511 penetrating the first transparent conductive layer 41. Preferably, in this comparative example, a green laser is used to remove the first dielectric layer 51 on the metal area, with a pulse width of 300ps to 700ps and an energy density of 0.3J / cm 2 ~ 5J / cm 2 .

[0122] Specifically, by controlling the laser parameters in the laser process, only the first dielectric layer on the first transparent conductive layer can be removed, the depth of the first window 511 is the thickness of the first dielectric layer 51, and the width of the first window is 1 μm to 25 μm. For example, the width of the first window is 15 μm and the depth is 55 nm.

[0123] In other comparative examples, the first window 511 may also be formed by other processes, such as wet etching, but not limited to the aforementioned laser process. In some comparative examples, the first window may not be prepared separately, but may be formed by simultaneous sintering during the electrode preparation process, which will not be described in detail here.

[0124] The first electrode 61 in this comparative example is a gate line electrode. Figure 1 , Fig.10 and Fig.12As shown, the first electrode 61 includes a first electrode portion 611 extending along the thickness direction of the silicon wafer to the inside of the first dielectric layer 51 and in contact with the first transparent conductive layer 41, and a second electrode portion 612 located above the first electrode portion 611 and extending to the surface of the first dielectric layer 51, and the maximum width of the second electrode portion 612 is greater than the maximum width of the first electrode portion 611. In addition, the surface of the first transparent conductive layer 41 away from the silicon wafer is a plane, the bottom surface of the first electrode portion 611 is flush with the bottom surface of the first dielectric layer 51, that is, the bottom surface of the first electrode portion 611 is flush with the bottom of the first window 511, and the top surface of the first electrode portion 611 is flush with the top surface of the first dielectric layer 51, that is, the top surface of the first electrode portion 611 is flush with the top of the first window 511.

[0125] Furthermore, the width W1 of the top surface of the second electrode portion 612 is smaller than the width W2 of the bottom surface of the second electrode portion 612, and the side surface of the second electrode portion 612 is arranged in an inclined surface. At the same time, the width W2 of the bottom surface of the second electrode portion 612 is greater than the width of the first electrode portion (that is, the width of the first window 511). In this comparative example, the width of the first electrode portion 611 is a certain value W3 along the thickness direction of the silicon wafer. With this arrangement, the maximum width of the first electrode portion 611 is W3, and the maximum width of the second electrode portion 612 is W2.

[0126] In some comparative examples, the side surface of the second electrode portion 612 may be other shapes, such as a regular or irregular curved surface, etc., as long as the width W1 of the top surface of the second electrode portion 612 is smaller than the width W2 of the bottom surface of the second electrode portion 612 .

[0127] Specifically, the thickness of the first electrode portion 611 (i.e., the thickness of the first dielectric layer) is 30nm~100nm, preferably 55nm, and the maximum width W3 of the first electrode portion (i.e., the width of the first window 511) is 1μm~25μm; the maximum width W2 of the bottom surface of the second electrode portion 612 is 10μm~50μm, and the width W1 of the top surface of the second electrode portion 612 is preferably between W3 and W2.

[0128] In addition, in this comparative example, the total thickness of the first electrode is 5 μm to 20 μm, preferably 10 μm, and the distance between two adjacent first electrodes on the same side of the silicon wafer is 500 μm to 1000 μm.

[0129] The first electrode in this comparative example is a gate line electrode, which can be a main gate line or a fine gate line. The line width and spacing of the main gate line and the fine gate line are designed according to actual needs, which will not be further described here.

[0130] Similar to Example 2, the first electrode 61 in this comparative example is prepared by electroplating or chemical plating, and the first electrode 61 includes a seed layer 601 that is entirely or partially located in the first dielectric layer and a first metal layer 602 that is located on the seed layer 601, and the total thickness of the seed layer 601 and the first metal layer 602 is 1 μm to 15 μm. Furthermore, it also includes the seed layer 601 that is coated outside the first window 511 and the second metal layer 603 outside the first metal layer 602, that is, in the overall structure composed of the seed layer 601 and the first metal layer 602, the portion located outside the first window 511 is coated by the second metal layer 603.

[0131] The first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer in this comparative example are described in detail above. The second dielectric layer 52 and the second electrode 62 on the back side of the silicon wafer are exactly the same as the first dielectric layer 51 and the first electrode 61 on the front side of the silicon wafer, and will not be described again here.

[0132] The preparation method of the heterojunction battery in this comparative example is as follows: 1. Ginseng Fig.13a As shown, a silicon wafer is provided.

[0133] The silicon wafer 10 in this comparative example is an N-type single crystal silicon wafer, with a resistivity of 0.5Ω·m to 3Ω·m, a thickness of 90μm to 120μm, and a size of 210mm.

[0134] Preferably, the silicon wafer 10 is double-sided texturing by an alkali texturing process, specifically: The surface oxide layer is removed by using a 5% diluted HF solution, and a pyramid velvet light-trapping structure (not shown) is formed on the surface by anisotropic etching of single crystal silicon using KOH or NaOH or tetramethylammonium hydroxide (TMAH) plus alcohol. Preferably, the size of the pyramid structure is preferably 0.5μm ~ 5μm.

[0135] 2. Ginseng Fig.13b As shown, a first intrinsic layer 21 , a first doped layer 31 and a first transparent conductive layer 41 are sequentially formed on the front side of the silicon wafer 10 , and a second intrinsic layer 22 , a second doped layer 32 and a second transparent conductive layer 42 are sequentially formed on the back side of the silicon wafer 10 .

[0136] Preferably, in this comparative example, the intrinsic layer and the doped layer are deposited by a plasma chemical vapor deposition (PECVD) process, and the transparent conductive layer is deposited by a reactive plasma deposition (RPD) process or a magnetron sputtering process, as follows: First, SiH4 (silane) gas is introduced into a vacuum chamber, and an intrinsic amorphous silicon layer is formed on the entire front area of ​​the silicon wafer 10 by a PECVD process, and then SiH4 gas, H2 gas and PH3 (phosphine) gas are introduced into the vacuum chamber, and an N-type doped amorphous silicon layer is formed on the intrinsic amorphous silicon layer by a PECVD process; Then, the wafer is turned over, the tray is changed, SiH4 (silane) gas is introduced into the vacuum chamber, and an intrinsic amorphous silicon layer is formed on the entire back side of the silicon wafer 10 by a PECVD process. Then, SiH4 gas, H2 gas and B2H6 (diborane) gas are introduced into the vacuum chamber, and a P-type doped amorphous silicon layer is formed on the intrinsic amorphous silicon layer by a PECVD process. Finally, the N-type doped amorphous silicon layer and the P-type doped amorphous silicon layer are coated by reactive plasma deposition (RPD) or magnetron sputtering. The back side is shielded by the edge of the carrier design (shielded by a mask), and the specific shielding area around is 0.8 mm. The transparent conductive layer is an ITO (99.5:0.5) layer with a thickness of 40 nm.

[0137] In this comparative example, the carrier concentration of the first transparent conductive layer and the second transparent conductive layer is 0.6E20cm -3 ~5E20cm -3 , preferably 3E20cm -3 , the mobility is 30cm 2 / Vs ~ 120cm 2 / Vs, preferably 80cm 2 / Vs, contact resistivity is 0.8mΩ·cm 2 ~ 4mΩ·cm 2 , preferably 2 mΩ·cm 2 , the refractive index is 1.9 ~ 2.1.

[0138] 3. Ginseng Fig.13c As shown, a first dielectric layer 51 and a second dielectric layer 52 are formed on the first transparent conductive layer 41 and the second transparent conductive layer 42 respectively.

[0139] A low-temperature PECVD process is used with a deposition temperature of 100°C to 160°C. A first dielectric layer 51 and a second dielectric layer 52 are deposited on the first transparent conductive layer 41 and the second transparent conductive layer 42, respectively. The dielectric layer material may be SiN X 、SiO X 、SiNO X , Al2O3, ZrO2, MgF2, etc., or it can be a multi-layer composite film.

[0140] For example, SiN is selected in this comparative example. X layer as dielectric layer, SiNO XThe refractive index n of the layer is 1.95 and the thickness is 55 nm.

[0141] 4. Ginseng Fig.13d As shown, the first dielectric layer 51 and the second dielectric layer 52 are patterned and opened to form a first window 511 penetrating the surface of the first transparent conductive layer 41 and a second window 521 penetrating the surface of the second transparent conductive layer 42 .

[0142] Preferably, in this comparative example, a green laser is used to remove the dielectric layer on the front and back metal areas, with a pulse width of 300ps to 700ps and an energy density of 0.3J / cm 2 ~ 5J / cm 2 The width of the film opening (i.e., the window width) is 1μm ~ 25μm, and the depth of laser processing is equal to the thickness of the dielectric layer, so that the surface of the transparent conductive layer away from the silicon wafer is a plane.

[0143] Furthermore, in this comparative example, the modified silicon wafer is annealed in an annealing furnace at a temperature of 180° C. to 220° C. for a time of 10 min to 30 min. A densified film layer can be formed through the annealing process.

[0144] 5. Ginseng Fig.13e As shown, a first electrode 61 in contact with the first transparent conductive layer 41 is prepared at the first window 511 of the first dielectric layer 51 , and a second electrode 62 in contact with the second transparent conductive layer 42 is prepared at the second window 521 of the second dielectric layer 52 .

[0145] First, a seed layer is prepared at the window of the dielectric layer by using an electroplating or chemical plating process; Then, a first metal layer is prepared on the outer side of the seed layer by using an electroplating or chemical plating process; Finally, a second metal layer is prepared on the outer sides of the seed layer and the first metal layer by using an electroplating or chemical plating process.

[0146] The seed layer is described by taking copper as an example, and the thickness of the copper seed layer is 100nm to 500nm; The first metal layer takes electroplating copper as an example. The electroplating copper solution includes copper sulfate, sulfuric acid, copper balls and additives that can optimize the crystal structure of the copper layer. 2+ The concentration of is 50g / L, the concentration of sulfuric acid is 40g / L, the thickness is 7μm, and the width is 15μm; The second metal layer is tin electroplated as an example. The tin electroplating solution includes tin methanesulfonate and tin plating additives. 2+ The concentration of is 30 g / L, the concentration of methanesulfonic acid is 200 g / L, and the thickness is 3 μm.

[0147] Finally, the heterojunction battery was alkaline washed, and the prepared battery cell was subjected to light injection treatment. The temperature of the light injection treatment was 210° C., and the time of the light injection treatment was 90 s.

[0148] The gate line electrodes in Comparative Examples 1, 2 and Example 1 are all described by taking fine gate lines as examples, wherein when the structure in Comparative Example 1 is prepared by screen printing, the gate line electrode line width is 25 μm and the number of roots is 60, and when it is prepared by ink copper interconnection process, the gate line electrode line width is 20 μm and the number of roots is 100; while the gate lines prepared by the structures in Comparative Example 2 and Example 1 are finer and denser, and the gate line electrode line width is 15 μm and the number of roots is 140. It can be seen that by introducing an insulating dielectric layer on the surface of the transparent conductive layer, the dielectric layer can play the role of an insulating mask for electroplating, thereby realizing copper electrode electroplating on a heterojunction battery, and a metallized structure with fine gate lines (the gate line width is preferably 5 μm to 15 μm) can be obtained.

[0149] In addition, the dielectric layer can reduce reflection to maximize optical utilization through optimal design of the refractive index, make up for the shortcoming of low short-circuit current Isc of heterojunction batteries, and obtain a metallized structure with excellent electrical properties (high conductivity, low contact resistivity).

[0150] Patterning the dielectric layer on the transparent conductive layer can replace the expensive ink printing, exposure and development steps. It is easier to obtain a fine grid structure than the conventional method, and the process cost is lower. At the same time, it eliminates the traditional ink etching and seed layer back etching process, reduces the process cost, and reduces the risk of negative impact of chemical liquid on battery performance in the wet process. Compared with the traditional ink copper electroplating process, the cost can be reduced from 0.20 yuan / W to 0.17 yuan / W.

[0151] However, in Comparative Example 2, since a laser process is used to open windows on the dielectric layer, the input of additional energy will inevitably cause damage to the battery, such as damage to the surface of the doped structure and damage to the side wall surface of the dielectric layer. The damage to the interface will directly affect the subsequent electrode growth, resulting in excessive contact resistance and significantly reducing the battery's fill factor FF. Excessive energy will reduce the passivation performance of the doped structure and significantly reduce the battery's pseudo fill factor pFF and open circuit voltage Voc.

[0152] Based on this, the inventor creatively discovered that when the preparation process of Example 1 of the present application is adopted, although the paraffin mask is formed first and the dielectric layer is deposited later, near the horizontal junction of the paraffin and the dielectric layer, that is, Figure 5Near the side of the first window shown, the provision of paraffin does not have too much impact on the deposition interface of the dielectric layer, so as to affect the subsequent electrode growth; on the contrary, by first forming a patterned mask on the doping structure in Example 1, then depositing the dielectric layer on the doping structure and the mask, and finally removing the mask and the dielectric layer on its surface, thereby forming a window in the dielectric layer, the damage caused by using laser to open the window in the dielectric layer can be significantly reduced.

[0153] IV performance tests were conducted on different heterojunction batteries, and the test data are shown in the following table:

[0154] It can be seen that in Example 1, the paraffin mask is used to open windows in the dielectric layer, which avoids the passivation loss in the laser window opening process, improves the fill factor and open circuit voltage, and improves the battery efficiency by 0.22%. Example 2

[0155] The solar cell structure and preparation method in this embodiment are basically the same as those in Example 1. The difference is that in this embodiment, by modifying the transparent conductive layer, the transparent conductive layer can obtain a higher carrier concentration, a higher mobility and a lower contact resistivity, so that the electrode and the transparent conductive layer form a good contact, thereby improving the battery efficiency and component power.

[0156] Specifically, after forming the window in the dielectric layer in step 5, the first transparent conductive layer 41 in the first window 511 and the second transparent conductive layer 42 in the second window 521 are modified.

[0157] The exposed transparent conductive layer in the window is modified by laser technology, so that the transparent conductive layer obtains higher carrier concentration, higher mobility and lower contact resistivity. For example, in this embodiment, an infrared laser is used for modification, with a pulse width of 100ns to 800ns and an energy density of 0.54J / cm 2 ~ 6J / cm 2 .

[0158] The carrier concentration of the transparent conductive layer in the window after modification is 2.5E20cm -3 ~ 6.5E20cm -3 , preferably 4.5E20cm -3 , the mobility is 40cm 2 / Vs ~ 150cm 2 / Vs, preferably 88cm 2 / Vs, contact resistivity is 0.4mΩ·cm 2 ~ 3mΩ·cm 2 , preferably 1.5 mΩ·cm2 .

[0159] It can be seen that after laser modification, the carrier concentration can be increased by 1.5E20cm -3 , the mobility can be increased by 8cm 2 / Vs, the contact resistivity can be reduced by 0.5mΩ·cm 2 . Example 3

[0160] The solar cell in this embodiment is described by taking a heterojunction cell as an example. Fig.14 , Fig.15 As shown, the structure of the heterojunction battery in this embodiment is basically the same as that in Embodiment 1, except that the dielectric layer in Embodiment 1 is a single-layer film structure, while the dielectric layer in this embodiment is a two-layer composite film.

[0161] Specifically, in this embodiment, SiNO is used on the front side of the battery. X Layer and SiN X The layers are respectively used as the outer dielectric layer 502 and the inner dielectric layer 501, SiNO X The refractive index n of the layer is 1.8, the thickness is 15nm, and the SiN X The refractive index n of the layer is 1.95, the thickness is 35 nm, and the thickness of the entire first dielectric layer 51 is 50 nm. X Layer and SiN X The layers can be deposited sequentially on the first transparent conductive layer 41 by using a hot wire CVD process. The second dielectric layer on the back of the battery has the same structure as the first dielectric layer, and will not be described in detail here. Example 4

[0162] Ginseng Fig.16 , Fig.17 As shown, the structure and preparation method of the heterojunction battery in this embodiment are basically the same as the structure and preparation method of the heterojunction battery in Example 1, except that a groove 411 is formed on the surface of the first transparent conductive layer 41 away from the silicon wafer in this embodiment, and the bottom surface of the first electrode portion in the first electrode 61 is lower than the bottom surface of the first dielectric layer 51 and contacts with the bottom surface of the groove 411.

[0163] The grooves 411 on the surface of the first transparent conductive layer 41 may be formed by laser processing or other processes, which will not be described in detail herein.

[0164] Likewise, the structures of the second transparent conductive layer 42 , the second dielectric layer 52 and the second electrode 62 are completely the same as those of the first transparent conductive layer 41 , the first dielectric layer 51 and the first electrode 61 , and are not described in detail herein. Example 5

[0165] Ginseng Fig.18 , Fig.19 As shown, the structure and preparation method of the heterojunction battery in this embodiment are basically the same as the structure and preparation method of the heterojunction battery in Example 1. The difference is that during different printing / printing processes, the paraffin is affected by factors such as the surface tension of the transparent conductive layer, and the top surface of the paraffin mask is a curved surface that is bent away from the doping structure.

[0166] Taking the first mask 71 as an example, in this embodiment, the bottom surface 711 and the side surface 713 of the mask are planes, and the top surface of the mask is a curved surface bent behind the first transparent conductive layer 41, that is, it is convex in the middle.

[0167] Furthermore, in this embodiment, the mask top surface 712 can be a surface formed in other preparation processes. Since the thickness of the dielectric layer is less than the height of the mask, the shape of the first window 511 is mainly affected by the mask side surface 713, and the shape of the mask top surface 712 will not affect the window shape. Example 6

[0168] Ginseng Figure 20 to Figure 22 As shown, the structure and preparation method of the heterojunction battery in this embodiment are basically the same as the structure and preparation method of the heterojunction battery in Example 1. The difference is that during different printing / printing processes, the paraffin is affected by factors such as the surface tension of the transparent conductive layer, and the top and side surfaces of the paraffin mask are curved surfaces.

[0169] Taking the first mask 71 as an example, in this embodiment, the bottom surface 711 of the mask is a plane, and the rest of the surface is a smooth curved surface, and the width of the first mask 71 gradually decreases from the surface of the first transparent conductive layer 41 to the outside along the thickness direction of the silicon wafer. Different from Embodiment 1 and Embodiment 6, the first mask in this embodiment does not clearly distinguish between the side surface of the mask and the top surface of the mask.

[0170] Different from the first embodiment, since the outer side surface of the first mask in this embodiment is a smooth curved surface, the side wall of the first window 511 is also correspondingly curved, and the shape of the first electrode 61 in the first window 511 is consistent with the shape of the first window 511 .

[0171] It should be understood that the solar cells in the above embodiments are described using heterojunction cells (HJT cells) as an example. In heterojunction cells, the doping structure includes an intrinsic layer, a doping layer and a transparent conductive layer located on the surface of the silicon wafer. The present invention is also applicable to other types of solar cells, such as PERC cells, TOPCon cells, IBC cells, etc.

[0172] For example, in TOPCon cells, the dielectric layer window and electrode structure are applicable to the front and back sides of the cell. The front doping structure includes a boron diffusion layer, and the back doping structure includes a tunneling layer and a phosphorus diffusion layer. The electrodes penetrate the dielectric layer and contact the boron diffusion layer and the phosphorus diffusion layer respectively. In IBC cells, the doping structure includes a P-type doping region and an N-type doping region, both of which are located on the back side of the cell. Therefore, only the dielectric layer needs to be prepared on the back side of the cell, and the two electrodes penetrate the dielectric layer and contact the P-type doping region and the N-type doping region respectively. In PERC cells, the dielectric layer window and electrode structure are applicable to the front and back sides of the cell. The dielectric layer is located on the phosphorus emitter on the front side and the aluminum back field on the back side, and the electrodes penetrate the dielectric layer and contact the phosphorus emitter and the aluminum back field respectively.

[0173] It can be seen from the above technical solutions that the present invention has the following technical effects: The present invention forms a patterned dielectric layer on the transparent conductive layer, which can realize a finer grid line design, thereby improving the battery efficiency and component power; at the same time, the patterned dielectric layer is used as a mask for preparing electrodes, and there is no need to use expensive photosensitive ink, which greatly reduces the process cost, and the dielectric layer can protect the transparent conductive layer below to avoid corrosion of the transparent conductive layer; In the present invention, a patterned mask is used to open a window in the dielectric layer, thereby avoiding the passivation loss in the laser window opening process, improving the fill factor and the open circuit voltage, and further improving the battery efficiency. In addition, by modifying the transparent conductive layer, the transparent conductive layer can obtain a higher carrier concentration, a higher mobility and a lower contact resistivity, so that the electrode and the transparent conductive layer form a good contact, thereby improving the battery efficiency and component power.

[0174] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0175] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for preparing a solar cell, characterized in that: The preparation method comprises the following steps: Provide silicon wafers; forming a doping structure on the surface of the silicon wafer; forming a patterned mask on the doped structure; forming a dielectric layer on the surface of the doping structure and the surface of the mask; Removing the mask and the dielectric layer on the surface of the mask, and forming a window in the dielectric layer that penetrates the doping structure along the thickness direction of the silicon wafer; An electrode in contact with the doping structure is prepared at the window of the dielectric layer.

2. The preparation method according to claim 1, characterized in that: The width of the mask gradually decreases from the surface of the doping structure outwards along the thickness direction of the silicon wafer.

3. The preparation method according to claim 1, characterized in that: The mask includes a mask bottom surface in contact with the surface of the doping structure, a mask top surface located above the mask, and two mask side surfaces connecting the mask top surface and the mask bottom surface. The width L1 of the mask top surface is smaller than the width L2 of the mask bottom surface, and the projection of the mask top surface on the plane where the mask bottom surface is located is located in the mask bottom surface area.

4. The preparation method according to claim 3, characterized in that: The top surface of the mask is a plane; or, the top surface of the mask is a curved surface that is bent away from the doping structure.

5. The preparation method according to claim 3, characterized in that: The side surface of the mask is a plane; or, the side surface of the mask is a curved surface.

6. The preparation method according to claim 1, characterized in that: The mask is a paraffin mask.

7. The preparation method according to claim 6, characterized in that: The paraffin mask is formed by inkjet printing or screen printing; and, The paraffin mask is removed by alkaline washing with an alkaline solution, and the alkaline washing temperature is 60° C. to 80° C.

8. The preparation method according to claim 1, characterized in that: The width of the window gradually decreases from the bottom of the window to the top of the window.

9. The preparation method according to claim 1, characterized in that: The width L3 of the window top is smaller than the width L4 of the window bottom, and the projection of the window top on the surface of the doping structure is located within the window bottom region.

10. The preparation method according to claim 1, characterized in that: The mask includes a mask bottom surface in contact with the surface of the doping structure, a mask top surface located above the mask, and two mask side surfaces connecting the mask top surface and the mask bottom surface, the width L1 of the mask top surface is 3μm to 20μm, and the width L2 of the mask bottom surface is 8μm to 30μm; and / or, The height of the mask is 1 μm to 5 μm; and / or, The width L3 of the top of the window is 5 μm to 25 μm, and the width L4 of the bottom of the window is 8 μm to 30 μm; and / or, The depth of the window is 30nm~100nm.

11. The preparation method according to claim 1, characterized in that: The dielectric layer is deposited by hot wire CVD process at a deposition temperature of 25° C. to 60° C.; and / or, The deposition thickness of the dielectric layer is smaller than the height of the mask.

12. The preparation method according to claim 1, characterized in that: The dielectric layer includes SiN X 、SiO X 、SiNO X , Al2O3, ZrO2, MgF2, and the thickness of the dielectric layer is 30nm~100nm.

13. The preparation method according to claim 12, characterized in that: The dielectric layer comprises an outer dielectric layer and an inner dielectric layer, and the refractive index of the inner dielectric layer is greater than or equal to the refractive index of the outer dielectric layer.

14. The preparation method according to claim 1, characterized in that: The preparation method further comprises: The silicon wafer after removing the mask is annealed at a temperature of 180° C. to 220° C. for a time of 10 min to 30 min.

15. The preparation method according to claim 1, characterized in that: The electrode is partially located in the window, and partially located outside the window and extending to the surface of the dielectric layer.

16. The preparation method according to claim 1, characterized in that: The solar cell is any one of a HJT cell, a PERC cell, a TOPCon cell, and an IBC cell.

17. The preparation method according to claim 1, characterized in that: The doping structure includes an intrinsic layer, a doping layer and a transparent conductive layer stacked in sequence on the surface of the silicon wafer, the window penetrates the transparent conductive layer along the thickness direction of the silicon wafer, and the electrode contacts the transparent conductive layer.

18. The preparation method according to claim 17, characterized in that: The thickness of the transparent conductive layer is 15nm to 150nm; and / or, The transparent conductive layer is a combination of one or more of ITO, VTTO, IWO, HITO, VTZO, AMTO, and TTO.

19. The preparation method according to claim 1, characterized in that: The preparation of the electrode comprises: A seed layer is prepared at the window of the dielectric layer by using an electroplating or chemical plating process; The first metal layer is prepared on the outer side of the seed layer by electroplating or chemical plating.

20. The preparation method according to claim 19, characterized in that: The preparation of the electrode also includes: The second metal layer is prepared on the outer sides of the seed layer and the first metal layer by using an electroplating or chemical plating process.

21. The preparation method according to claim 19, characterized in that: The material of the seed layer and the first metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, and Sn; and / or, The total thickness of the seed layer and the first metal layer is 1 μm to 15 μm; and / or, The thickness of the seed layer is 100nm to 500nm; and / or, The thickness of the seed layer is greater than or equal to the thickness of the dielectric layer.

22. The preparation method according to claim 20, characterized in that: The material of the second metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, and Sn; and / or, The thickness of the second metal layer is 1 μm to 5 μm.

23. A solar cell, characterized in that: The solar cell includes a silicon wafer and a doping structure located on the surface of the silicon wafer, and the solar cell also includes a dielectric layer stacked on the doping structure and an electrode in contact with the doping structure. A window is formed on the dielectric layer and penetrates the doping structure along the thickness direction of the silicon wafer. The width L3 of at least one of the tops of the windows is smaller than the width L4 of the bottom of the window, and the projection of the top of the window on the surface of the doping structure is located in the bottom area of ​​the window.

24. The solar cell according to claim 23, characterized in that The width of at least one of the windows gradually decreases from the bottom of the window to the top of the window.

25. The solar cell according to claim 23, characterized in that The electrode includes a first electrode portion located in the window and in contact with the doping structure, wherein a top surface of the first electrode portion is flush with a top of the window, and a bottom surface of the first electrode portion is flush with a bottom of the window.

26. The solar cell according to claim 25, characterized in that The width of the top surface of the first electrode portion is smaller than the width of the bottom surface of the first electrode portion, and the projection of the top surface of the first electrode portion on the plane where the bottom surface of the first electrode portion is located is located within the bottom surface area of ​​the first electrode portion.

27. The solar cell according to claim 25, characterized in that The first electrode portion is located in all of the windows.

28. The solar cell according to claim 25, characterized in that The electrode further includes a second electrode portion located above the first electrode portion and extending to the surface of the dielectric layer, and a maximum width of the second electrode portion is greater than a maximum width of the first electrode portion.

29. The solar cell according to claim 28, characterized in that The width of the top surface of the second electrode portion is smaller than the width of the bottom surface of the second electrode portion, and the projection of the top surface of the second electrode portion on the plane where the bottom surface of the second electrode portion is located is located within the bottom surface area of ​​the second electrode portion.

30. The solar cell according to claim 23, characterized in that The side wall of the window is a plane; or, the side wall of the window is a curved surface.

31. The solar cell according to claim 25, characterized in that The bottom surface of the first electrode portion is flush with the surface of the doping structure; or, A groove is formed on the surface of the doping structure away from the silicon wafer, and the bottom surface of the first electrode portion is lower than the bottom surface of the dielectric layer and contacts with the bottom surface of the groove.

32. The solar cell according to claim 23, characterized in that The width L3 of the top of the window is 5 μm to 25 μm, and the width L4 of the bottom of the window is 8 μm to 30 μm; and / or, The depth of the window is 30nm ~ 100nm.

33. The solar cell according to claim 23, characterized in that The dielectric layer includes SiN X 、SiO X 、SiNO X , Al2O3, ZrO2, MgF2, and the thickness of the dielectric layer is 30nm ~ 100nm.

34. The solar cell according to claim 23, characterized in that The dielectric layer comprises an outer dielectric layer and an inner dielectric layer, and the refractive index of the inner dielectric layer is greater than or equal to the refractive index of the outer dielectric layer.

35. The solar cell according to claim 23, characterized in that The spacing between two adjacent electrodes on the same side of the silicon wafer is 500 μm to 1000 μm; and / or, The total thickness of the electrode is 5 μm to 20 μm.

36. The solar cell according to claim 23, characterized in that The electrode includes a seed layer at least partially located in the dielectric layer and a first metal layer located outside the seed layer. The total thickness of the seed layer and the first metal layer is 1 μm to 15 μm.

37. The solar cell according to claim 36, characterized in that The thickness of the seed layer is 100nm to 500nm; and / or, The thickness of the seed layer is greater than or equal to the thickness of the dielectric layer; and / or, The material of the seed layer and the first metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, and Sn.

38. The solar cell according to claim 36, characterized in that The electrode also includes a seed layer coated on the outside of the window and a second metal layer outside the first metal layer. The material of the second metal layer is one or more of Ag, Al, Cu, Mg, Mo, W, Cr, Ni, and Sn, and the thickness of the second metal layer is 1μm to 5μm.

39. The solar cell according to claim 23, characterized in that The solar cell is any one of a HJT cell, a PERC cell, a TOPCon cell, and an IBC cell.

40. The solar cell according to claim 23, characterized in that The doping structure includes an intrinsic layer, a doping layer and a transparent conductive layer stacked in sequence on the surface of the silicon wafer, the window penetrates the transparent conductive layer along the thickness direction of the silicon wafer, and the electrode contacts the transparent conductive layer.

41. The solar cell according to claim 40, characterized in that The thickness of the transparent conductive layer is 15nm to 150nm; and / or, The transparent conductive layer is a combination of one or more of ITO, VTTO, IWO, HITO, VTZO, AMTO, and TTO.

42. A photovoltaic module, characterized in that: The photovoltaic module includes a solar cell prepared by the preparation method described in any one of claims 1 to 22 or includes a solar cell described in any one of claims 23 to 41.

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