Three-dimensional memory device utilizing dummy memory blocks to mitigate defects

Abstract

A structure of a three-dimensional (3D) memory device and a structure of a system including the three-dimensional (3D) memory device are disclosed. In one example, the 3D memory device includes a storage plane, where the storage plane includes a first edge and an array of blocks. The block array includes: a plurality of memory blocks configured to store data, where the plurality of memory blocks are separated by a continuous slot structure; and a first dummy region between the first edge and the plurality of memory blocks. The first dummy region includes alternating first and second slot structures, where the first and second slot structures are discontinuous slot structures.

Description

Technical Field

[0001] The present specification relates to the field of semiconductor technology, and more particularly, to a three-dimensional (3D) memory device (eg, a 3D NAND memory device) that utilizes one or more dummy memory blocks to mitigate defects. Background Art

[0002] As memory devices continue to shrink to reduce manufacturing costs and increase storage density, the scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations of planar memory cells.

[0003] Planar memory cells have been miniaturized to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and manufacturing techniques become challenging and costly. Therefore, the memory density of planar memory cells approaches the upper limit. 3D memory architectures can solve the density limitations in planar memory cells by vertically stacking memory cells in memory blocks. 3D architectures generally include multiple memory block arrays and peripheral devices (e.g., memory controllers) for controlling data requests to and from memory blocks in these arrays.

[0004] However, 3D memory architectures are rapidly approaching an upper limit on the height of functional memory blocks due to structural instabilities. As the height increases, instabilities in the 3D architecture (e.g., due to various stresses) can cause many memory blocks to fail, thereby reducing the storage capacity of the 3D architecture and potentially rendering the 3D architecture inoperable. The gains achieved by the 3D architecture over planar memory cells can be significantly reduced by the failure of one or more memory blocks, thereby requiring a trade-off between memory density and the number of memory blocks in the array. Summary of the invention

[0005] The present specification describes a three-dimensional (3D) memory device (eg, a 3D NAND memory device) that utilizes one or more dummy memory blocks to mitigate defects and improve structural stability. A system including the 3D memory device is also described.

[0006] In one aspect, a 3D memory device includes a storage plane, wherein the storage plane includes a first edge and a block array. The block array includes: a plurality of storage blocks configured to store data, wherein the plurality of storage blocks are separated by continuous gap structures; and a first dummy region located between the first edge and the plurality of storage blocks. The first dummy region includes alternating first gap structures and second gap structures, wherein the first gap structures and the second gap structures are discontinuous gap structures.

[0007] In another aspect, a system includes a 3D memory device and a memory controller electrically connected to the 3D memory device, wherein the memory controller is configured to manage data to and from the 3D memory device. The 3D memory device includes a storage plane, wherein the storage plane includes a first edge and a block array. The block array includes: a plurality of storage blocks configured to store data, wherein the plurality of storage blocks are separated by a continuous gap structure; and a first dummy region located between the first edge and the plurality of storage blocks. The first dummy region includes alternating first and second gap structures, wherein the first and second gap structures are discontinuous gap structures.

[0008] In yet another aspect, a 3D memory device includes a storage plane, wherein the storage plane includes a first edge and a block array. The block array includes: a plurality of storage blocks configured to store data, wherein the plurality of storage blocks are separated by a continuous gap structure; and one or more dummy blocks located between the first edge and the plurality of storage blocks. Each dummy block includes a first gap structure separating adjacent blocks and one or more second gap structures dividing the dummy block into a plurality of fingers, wherein the first gap structure and the one or more second gap structures are discontinuous gap structures.

[0009] One or more of the following advantages may be realized by implementing particular embodiments of the subject matter described in this specification.

[0010] The present disclosure introduces a 3D memory architecture that achieves improved structural stability and defect mitigation without sacrificing a significant number of memory blocks. Specifically, the 3D architecture utilizes one or more dummy memory blocks made at the edge of the array to stabilize the functional memory blocks in the array. By intentionally using appropriately made dummy blocks, the functional memory blocks can exhibit reduced stress and are less prone to defects. The number of functional memory blocks in the array can be increased, thereby increasing storage density and total data storage capacity. In addition, due to the stabilizing effect of the dummy blocks, the height of the memory blocks can also be increased to provide further benefits in terms of storage capacity. The devices and techniques for stabilizing the 3D memory architecture provided in the present disclosure increase memory capacity, reduce device defects and increase the manufacturing yield of such devices.

[0011] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is an isometric view showing an example of a three-dimensional (3D) memory block.

[0013] Figure 2A is a top view illustrating an example of a 3D memory structure.

[0014] Figure 2B-2D It shows Figure 2A Cross-sectional view of a 3D memory structure.

[0015] Figure 3A and Figure 3B is a top view showing an example of two 3D memory structures forming a 3D memory block.

[0016] Figure 4 is a top view illustrating an example of a semiconductor die providing multiple 3D memory devices.

[0017] Figure 5 is a top view illustrating an example of a 3D memory device providing multiple memory planes.

[0018] Fig. 6A is a top view showing an example of a defective memory plane including a memory block array.

[0019] Figure 6B It shows Fig. 6A A top view of an example of a defective memory block contained in a defective memory plane.

[0020] Figure 6C It shows Figure 6B A top view of an example of a defective seam structure (SS) in a defective memory block.

[0021] Fig. 7A is a top view showing an example of a memory plane including a memory block array and a dummy area.

[0022] Figure 7B It shows Fig. 7A A top view of an example of a memory block contained in a memory plane.

[0023] Figure 7C It shows Figure 7B A top view of an example of a memory block in a SS.

[0024] Figures 8A-8C is a top view illustrating an example of a dummy region including one or more dummy memory blocks.

[0025] Fig. 9A and Fig. 9B is a top view showing an example of a memory block and a dummy area having a core array area located between two stepped structure areas.

[0026] Fig.10is a schematic diagram illustrating an exemplary system including one or more 3D memory devices and a memory controller.

[0027] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0028] In order to understand and implement the present disclosure and achieve technical effects, reference will now be made in detail to the exemplary embodiments shown in the accompanying drawings. It should be understood that the following description is made by way of example only and is not intended to limit the present disclosure. The various embodiments of the present disclosure and the various features in the embodiments can be combined and rearranged in various ways as long as they are not contradictory. Without departing from the essence and scope of the present disclosure, modifications, equivalent transformations or improvements to the present disclosure are understandable to those skilled in the art, and are intended to be included in the scope of the present disclosure.

[0029] It should be noted that the references to "one embodiment", "an embodiment", "an exemplary embodiment", "some embodiments", etc. in the specification indicate that the embodiments described may include specific features, structures or characteristics, but not every embodiment may include the specific features, structures or characteristics. In addition, such phrases do not necessarily refer to the same embodiment.

[0030] In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments whether explicitly or not explicitly described.

[0031] In general, terms should be understood, at least in part, by the context in which they are used. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may also be understood to express singular or plural usage, depending, at least in part, on the context.

[0032] It should be easily understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, so that “on” not only means being directly on something, but also includes the meaning of being on something with intervening features or layers therebetween, and “on” or “over” not only means being on or over something, but also includes the meaning of being on or over something with no intervening features or layers therebetween (i.e., directly on something).

[0033] In addition, spatially relative terms, such as "below," "under," "down," "above," "upper," etc., may be used herein for ease of description to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation other than the orientation shown in the drawings. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly in the same manner. The term "vertical" refers to a direction perpendicular to a surface of a semiconductor substrate, and the term "horizontal" refers to any direction parallel to the surface of the semiconductor substrate.

[0034] As used herein, the term "substrate" generally refers to a material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned, or can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, oxide, or sapphire wafers.

[0035] As used herein, the term "layer" generally refers to a material portion including an area with a certain thickness. A layer may extend within the range of the entire lower structure or upper structure, or may have a range smaller than the range of the lower structure or upper structure. In addition, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any paired horizontal planes between the top surface and the bottom surface of the continuous structure, or at the top surface and the bottom surface. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, may contain one or more layers therein, and / or may have one or more layers located thereon, above and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (in which interconnect lines and / or vertical contacts are formed) and one or more dielectric layers.

[0036] As used herein, the term "3D memory device" generally refers to a semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "memory string", e.g., a NAND string) disposed on a laterally oriented substrate such that the memory string extends in a vertical direction relative to the substrate. As used herein, the term "vertical" or "vertically" generally refers to a direction perpendicular to a lateral surface of a substrate.

[0037] As used herein, the term "level" generally refers to elements having substantially the same height in the vertical direction. For example, a word line (e.g., a control gate electrode) and the underlying gate dielectric layer may be collectively referred to as a level. A sacrificial layer and an underlying insulating layer may be collectively referred to as a level. A conductive layer and an underlying insulating layer may be collectively referred to as a level. Word lines having substantially the same height may be referred to as word line levels, and similar situations may be referred to by analogy.

[0038] As used herein, the term "slit structure" generally refers to a feature that runs through the stacked layers of a 3D memory device in the vertical direction and is substantially straight in the horizontal direction. An exemplary metaphor is a cut through a layered cake. The slit structure may or may not run through the lower substrate of the 3D memory device. In some embodiments, the slit structure may be referred to as a "gate line slit" or a "gate line slit structure". For example, the slit structure may separate and electrically isolate different gate electrodes (or word lines) of the same level located on both sides of the slit structure. The slit structure may be continuous ("continuous slit structure"), so that the slit structure is not interrupted along its length in the horizontal direction (e.g., similar to a solid line from a top-down perspective). The slit structure may also be discontinuous ("discontinuous slit structure"), so that the slit structure is interrupted along its length in the horizontal direction (e.g., similar to a dotted line from a top-down perspective).

[0039] Some 3D memory devices (e.g., 3D NAND memory devices) include multiple storage planes, each of which provides a specific data storage capacity. The storage plane generally includes a series of 3D storage blocks for storing data arranged in a linear array. The 3D storage block stacks the storage cells vertically (in the form of a storage string), thereby increasing the storage density and reducing the cost per gigabyte. The storage cell is typically embedded in a word line (e.g., control gate electrode) stack and a semiconductor channel formed vertically through the stack. That is, the intersection of the word line and the semiconductor channel forms a storage cell transistor. Multiple intersections of the stacked word line and the semiconductor channel form a storage string. The 3D storage block typically includes a stepped structure formed on one or more sides or at the center of the stacked data storage structure, so as to achieve the following purposes: for example, using metal contact vias landing on different levels (or steps) of the stepped structure for word line pick-up and fan-out.

[0040] Continuous seam structures (SS) are often formed between adjacent memory blocks, thereby separating and electrically isolating the memory blocks in the array. Discontinuous SS can also be formed within the memory block itself, thereby dividing the memory block into multiple fingers. Each finger can be associated with a subset of the memory strings of the memory block to provide improved data communication with the individual memory cells in these strings. Discontinuous SS between fingers can allow some parts of adjacent fingers to be electrically isolated from each other, while other parts are still electrically connected. This feature can reduce the number of metal contact vias involved in word line pickup and reduce the possibility of connection failures.

[0041] However, as the staircase structure grows due to increasing layers of stacked memory cells, instabilities in the memory blocks (e.g., due to stress at the edges of the memory plane) may cause distortions and / or changes in the SS (both continuous SS and discontinuous SS). These distortions may render multiple memory blocks in the memory plane inoperable, thereby reducing data storage capacity. The number of defective and inoperable memory blocks may be unpredictable and may be large enough to cause the entire 3D memory device to be discarded, which reduces manufacturing yield.

[0042] In order to solve one or more of the aforementioned problems, the present disclosure introduces a solution that will achieve structural stability in a 3D memory architecture without sacrificing a significant number of memory blocks. Specifically, the present disclosure utilizes one or more dummy memory blocks made at the edge of the storage surface to stabilize the functional memory blocks. By intentionally using dummy blocks made with appropriate SS, the functional memory blocks can exhibit reduced stress and are less prone to defects. The number of functional memory blocks in the array and the height of the memory blocks can be increased, thereby improving storage density and total data storage capacity.

[0043] Figure 1 An example of a three-dimensional (3D) storage block 100 configured to store data is shown. Specifically, the storage block 100 employs an array of storage strings 114, each of which is composed of a stack of storage cells. The storage cells store data bits in the form of captured charges. The storage block can store data and communicate with various peripheral devices (e.g., a memory controller) to perform read and / or write requests to individual storage cells. As will be described below, multiple storage blocks can be integrated into a single storage plane, for example, a linear array, to provide an expected data storage capacity. The storage plane can also include one or more appropriately made dummy blocks to stabilize the array and reduce the prevalence of defects in the storage block. Figure 1The memory block 100 is an example of a NAND flash memory block. However, the 3D memory architecture discussed herein is not limited thereto, and the 3D memory architecture discussed herein may include various types of 3D memory blocks, for example, a 3D NOR flash memory block, a 3D RRAM memory block, and the like.

[0044] The 3D memory block 100 includes a substrate 101 supporting several stacked layers of components. The substrate 101 also includes a doped source line region 120, which forms a well structure for the memory block 100. The substrate 101 is covered by an insulating layer 103, thereby electrically isolating the substrate 101 from other layers. Multiple levels of gate electrodes 104, 107, and 109 are stacked in the vertical (z) direction on top of the insulating layer 103 and extend in the horizontal (x) direction. Although Figure 1 100. Although not shown in the figure, each level of gate electrodes generally includes an insulating layer (and / or a gate dielectric layer) to electrically isolate gate electrodes of different levels. In this exemplary embodiment, the gate electrodes of these levels form two stair structures located on opposite sides of the memory block 100. These stair structures correspond to levels (or steps) rising from opposite sides of the memory block 100 toward its center. The bit line 111 is arranged orthogonally (in the y direction) to the gate electrode on the topmost level of the memory block 100.

[0045] A level of lower selection gate electrodes 104 exists on top of the insulating layer 103. The lower selection gate electrodes 104 function as source selection gates of the memory block 100. A source line region 120 is located between adjacent lower selection gate electrodes 104 in the substrate 101. A plurality of levels of control gate electrodes 107-1, 107-2, and 107-3 are stacked in sequence above the lower selection gate electrodes 104, and function as word lines of the memory block 100. A level of upper selection gate electrodes 109 exists on top of the control gate electrodes 107. The upper selection gate electrodes 109 function as drain selection gates of the memory block 100. The gate electrodes of each level are electrically connected to a metal interconnect 119 through a metal contact via 117 landing on each level for word line pick-up, for example, to communicate with a peripheral device.

[0046] Adjacent gate electrodes 104, 107, and 109 in each level are separated by parallel slit structures (SS) 108-1 and 108-2. SS 108 vertically penetrates the stack of gate electrodes, thereby separating adjacent gate electrodes into different conductive paths. Figure 1104. Although not shown in the drawings, SS 108 is generally lined and / or filled with one or more materials to electrically isolate gate electrodes at the same level. In some embodiments, SS 108 also interacts with source line 120. For example, SS 108 may be lined with an insulating material to electrically insulate adjacent gate electrodes from each other. SS 108 with a liner may be filled with a conductive material (e.g., a metal or semiconductor) to form a metal-insulator-semiconductor (MIS) capacitor interface between the conductive material, insulating layer 103, and doped source line region 120. MIS capacitors may be biased with a voltage to change the conductive properties in substrate 101, for example, to generate a depletion layer and / or an inversion layer in source line region 120 between lower gate electrodes 104.

[0047] A plurality of semiconductor channels 114 vertically penetrate the gate electrodes 104, 107, and 109 of each stacked level at the center of the memory block 100. The semiconductor channels 114 are electrically connected to the bit lines 111 present on the topmost level. The intersection of the semiconductor channels 114 and the control gate electrode (word line) 107 corresponds to an individual memory cell transistor, for example, a field effect transistor. Thus, each semiconductor channel 114 acts as a memory string. The collection of semiconductor channels 114 constitutes a stacked data storage structure of the memory block 100.

[0048] The memory cell can receive a read and / or write request through the bit line 111 and the control gate electrode 107. Specifically, the memory cell row in the y direction can be accessed by the bit line 111, and the memory cell row in the x direction can be accessed by the control gate electrode 107. The control gate electrodes 107-1, 107-2 and 107-3 of different levels can access different memory cells in the z direction. The lower gate electrode 104 and the upper gate electrode 109 can facilitate the readout of the memory cell. Accordingly, any individual memory cell can be read and / or programmed by appropriately adjusted bit lines 111 and gate electrodes 104, 107 and 109. For example, when a specified voltage is placed on the bit line 111 and / or the control gate electrode 107, the presence or absence of the stored charge corresponding to the data bit in the memory cell will result in a change in the electrical impedance through the corresponding semiconductor channel 114. This impedance change will either allow current to flow through the semiconductor channel 114 or will inhibit current from flowing through the semiconductor channel 114, which can be sensed by the source select gate 104 and the drain select gate 107 to determine the programming state of the memory cell.

[0049] The semiconductor channel 114 is lined with a storage layer 113 to store charge (e.g., data bits), and the semiconductor channel 114 may be partially or completely filled with a dielectric filler (e.g., silicon dioxide). The semiconductor channel 114 may also support various other layers. For example, a semiconductor layer (e.g., a channel layer) may be located between the storage layer 113 and the dielectric filler 115 to facilitate the flow of current within the semiconductor channel 114. In some embodiments, the storage layer 113 is a composite layer composed of multiple layers (e.g., a tunneling layer, a storage layer (e.g., a "charge trapping layer"), and a blocking layer), which can improve the performance of the memory block 100. For example, the tunneling layer can allow controlled charge transfer between the semiconductor layer and the storage layer 113 (e.g., due to Fowler-Nordheim tunneling), the storage layer can store trapped charges associated with the data bits, and the blocking layer can inhibit the charge of the semiconductor channel 114 from leaking outward.

[0050] The present disclosure describes a memory block in which multiple word lines of the same level are conductively connected together. Specifically, a memory block (e.g., Figure 1 The exemplary memory block 100 of FIG. 1 is divided into a plurality of fingers with interconnected word lines. As described below, the discontinuous SS can also improve the structural stability of the 3D memory architecture and alleviate the defects of the 3D memory architecture when implemented in one or more dummy memory blocks. In addition, although Figure 1 The exemplary 3D memory block 100 of the embodiment adopts two stair structures, but in some embodiments, the 3D memory block may not include a stair structure, may include one stair structure, or may include more than two stair structures. For example, in the case of no stair structure, the 3D memory block may use a through-chip via that runs through the stack of material layers for word line pickup and fan-out. The 3D memory structure (e.g., the example described below) can be implemented as a 3D memory block with a single stair structure. As another example, the 3D memory block can also use multiple alternating stair structures (e.g., 3, 4, 5, 6 or more stair structures) and semiconductor channels to provide multiple stacked data storage structures. All such 3D memory blocks can use the techniques described herein (e.g., SS and dummy blocks) to achieve structural stability and defect mitigation.

[0051] Figures 2A-2D Various views of an exemplary 3D memory structure 50 configured to store data are shown. Figure 2A 5 shows a top view of an exemplary 3D memory structure 50. The memory structure 50 may be used as an individual memory block, however the memory structure 50 representatively represents half of a memory block (eg, Figure 1100). Figure 3A and Figure 3B , for example, an exemplary memory block formed by two memory structures. For clarity, Figures 2A-2D Various elements such as bit lines, metal contact vias, and semiconductor channel layers are omitted in order to outline other structural components of memory structure 50.

[0052] The memory structure 50 includes a plurality of memory strings (in the form of semiconductor channels 114) that provide a stacked data storage structure. The memory structure 50 is divided into a plurality of fingers 110 by parallel slit structures (SS) 108 (more specifically, discontinuous SS). The discontinuous SS 108-1 and 108-2 extend the length of the memory structure 50 horizontally in the x-direction. In this way, the semiconductor channels 114 are shared between the fingers 110 and can be accessed through the word lines of each finger 110. Each finger 110-1, 110-2, and 110-3 corresponds to a stack of word lines (in the form of conductive layers 211) that intersect the semiconductor channels 114, thereby forming a memory cell transistor. Note that in Figure 2A Three fingers 110 are shown in FIG. 5 for illustration, but memory structure 50 may include varying numbers of fingers separated by discontinuous SSs, for example, 2, 3, 4, 5, 6, or more fingers.

[0053] In this context, a discontinuous SS 108 refers to a SS having alternating discrete portions (or gaps) 208 and spaces 209. From a top view, a discontinuous SS is similar to a dashed line segment. In contrast, a continuous SS has a single uninterrupted portion and is similar to a solid line segment from a top-down perspective. The discrete portions 208 of the discontinuous SS 108 electrically isolate the word lines of adjacent fingers 110, while the spaces 209 (i.e., areas without gaps) facilitate electrical connections between the word lines of adjacent fingers 110. As mentioned above, connected word lines of the same level can share metal contact vias, thereby reducing the number of metal contact vias and corresponding metal interconnects. Increasing the number of connections in each word line level can also reduce the probability of connection failures.

[0054] Different portions 208 and different intervals 209 of a particular discontinuous SS 108 may have desired different lengths. In some embodiments, portion 208 may have a length of about 1 micrometer (μm) to 10 μm. The width of portion 208 may be about 0.5 μm to 2 μm in some cases. Intervals 209 between portions 208 may also be about 1 μm to 10 μm in some cases. Although discontinuous SS 108-1 and 108-2 are shown as alternating portions 208 and intervals 209 of the same pattern, different discontinuous SSs may even have different patterns within the same memory structure 50. For example, different patterns of discontinuous SSs may facilitate different electrical connections between adjacent fingers, which may be advantageous in situations involving many fingers (e.g., 4, 5, 6, or more fingers). As described below, different patterns of discontinuous SSs may also provide improved structural stability, similar to different bricklaying patterns used in brickwork.

[0055] Figure 2B A cross-sectional view along the BB' direction of an exemplary memory structure 50 is shown. In this embodiment, the memory structure 50 uses a staircase structure for word line pick-up and fan-out. However, as mentioned above, the techniques for defect mitigation described herein can be used for memory structures that do not use a staircase structure and 3D memory architectures. The cross-section BB' is a cross-section that runs through the length of the memory structure 50 and intersects the two semiconductor channels 114. As shown in FIG. Figure 2BAs can be seen in FIG. 1 , the memory structure 50 includes a substrate 101 supporting a plurality of ascending levels 210 of layers. Semiconductor channels 114 vertically penetrate through each level 210 to reach the substrate 101. Each level 210 forms a stepped structure that can be used for word line pick-up and fan-out, for example, by landing metal contact vias on each level 210. Each level 210-1, 210-2, 210-3, and 210-4 includes a corresponding conductive layer 211 present on top of a corresponding insulating layer 212. The conductive layers 211-1, 211-2, 211-3, and 211-4 constitute the word line of each finger 110. The insulating layers 212-1, 212-2, 212-3, and 212-4 electrically isolate the word lines of different levels. Discontinuous SS 108 allows electrical connections to be formed between adjacent word lines in the same level. For illustrative purposes, four levels 210 of alternating conductive layers 211 and insulating layers 212 are shown, but the memory structure 50 may include significantly more levels, for example, 25 levels or more, 50 levels or more, 100 levels or more, 125 levels or more, 150 levels or more, etc. In addition, each level 210 may include more than two layers, depending on the implementation. For example, each level 210 may include a gate dielectric layer sandwiched between a conductive layer 211 and an insulating layer 212. The gate dielectric layer may include a high dielectric constant (high-k) material, such as aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, or a combination thereof.

[0056] Depending on the implementation, the substrate 101 may include any suitable semiconductor material and / or insulating material, for example, silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), silicon on insulator (SOI), germanium (Ge), germanium on insulator (GOI), gallium nitride (GaN), gallium arsenide (GaAs), glass, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y ), ceramics, suitable III-V compounds, carbon or a combination thereof. For example, if the substrate 101 carries a doped source line region, the substrate 101 may include a semiconductor material forming a well structure. The conductive layer 211 may include any suitable conductive material, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polysilicon, doped silicon, silicide or a combination thereof. The insulating layer 212 may include any suitable insulating material, for example, silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiO x N y) or a combination thereof. Depending on the implementation, conductive layer 211 and insulating layer 212 may have the same thickness or different thicknesses. In some cases, there is no bottommost insulating layer (e.g., insulating layer 212-4) in the stack, so that substrate 101 acts as the bottommost insulating layer.

[0057] Figure 2C A cross-sectional view along the CC' direction of the memory structure 50 is shown. The cross-section CC' is a cross-section of the space 209 of the discontinuous SS 108. Here, the space 209 can be characterized as having no gaps, so that the conductive layer 211 of the memory structure 50 is not interrupted, thereby providing electrical connection between adjacent word lines in the same level 210. Figure 2C It is also shown how various stresses can create instabilities and / or defects in the 3D memory structure 50. For example, due to the organization of the conductive layer 211 and the insulating layer 212, the stacked level 210 generally has stability against compressive stresses in the vertical (z) direction. However, stresses in the horizontal (x and y) directions can act as shear stresses, which can cause the conductive layer 211 and the insulating layer 212 to separate from each other along their bonding surfaces. In some embodiments, the portion 208 can act as a stabilizer against these shear stresses similar to the steel bars in concrete.

[0058] Figure 2D A cross-sectional view along the D-D' direction of the memory structure 50 is shown. The cross-section D-D' is a cross-section of a portion 208 of the discontinuous SS 108, which shows the vertical gap structure of the SS. The portion 208 corresponds to a gap in the memory structure 50 that runs through the stack, so that the conductive layer 211 is interrupted, thereby isolating the electrical paths on both sides of the portion 208. The portion 208 is lined with an insulating material 213, and the portion 208 is filled with a filling material 214. In some embodiments, the portion 208 of the SS is partially filled with the insulating material 213 or completely filled with the insulating material 213. The insulating material 213 can include any of the materials described above for the insulating layer 212. The filling material 214 can include an insulating material or a conductive material. For example, in some embodiments, the filling material 214 can be a conductive material (e.g., any of the materials described above for the conductive layer 211) to interact with the source line in the substrate 101.

[0059] A set of SSs (including continuous SSs and / or discontinuous SSs) can be formed by various methods. An exemplary process of forming SSs in a memory structure, a memory block, and / or a memory block array will be described to achieve the technical effect of SSs. The exemplary process is as follows.

[0060] 1. Providing an alternating stack of insulating layers 212 and sacrificial layers. For example, insulating layers 212 and sacrificial layers may be deposited in an alternating manner on substrate 101. In some embodiments, the sacrificial layers are composed of silicon nitride (Si3N4).

[0061] 2. Etch grooves (corresponding to portions of SSs) through the stack. For example, if one or more of the SSs are discontinuous SSs, a series of grooves for each discontinuous SS can be etched. If one or more of the SSs are continuous SSs, a continuous groove for each continuous SS can be etched.

[0062] 3. Removing the sacrificial layer and depositing the conductive layer 211 in the cavity formed by removing the sacrificial layer, thereby generating an alternating stack of conductive layers 211 and insulating layers 212 .

[0063] 4. Recess the conductive layer 211 to remove any excess conductive material in the etched trenches.

[0064] 5. Fill the trenches in the stack with insulating material 213.

[0065] 6. Optionally, etching the insulating material 213 to form trenches in the insulating material 213 , and filling the trenches in the insulating material 213 with a filling material 214 .

[0066] 7. As an alternative to steps 5 and 6, the trenches in the stack are lined with an insulating material 213 and the lined trenches are filled with a filling material 214.

[0067] When performing the aforementioned process, the insulating layer 212, the sacrificial layer, the conductive layer 211, the insulating material 213 and the filling material 214 may be deposited by any suitable deposition method, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), metal organic CVD (MOCVD), sputtering, atomic layer deposition (ALD) or a combination thereof. Various other components (for example, the semiconductor channel 114 and the bit line) may be formed before, after or between (at least some of) the steps of the aforementioned process.

[0068] Figure 3A and Figure 3B is shown as two memory structures 50-1 and 50-2 (e.g., Figures 2A-2D1 and 100B are formed by two of the memory structures 50 shown in FIG. 1 . In general, the memory blocks 100A and 100B include one or more core array regions 51 and one or more staircase structure regions 52. The core array region 51 includes semiconductor channels 114 (e.g., memory strings) that constitute a stacked data storage structure. The staircase structure region 52 includes a staircase structure in which, for example, metal contact vias can land on different levels for word line pick-up and fan-out. The memory blocks 100A and 100B are divided into a plurality of fingers 110-1, 110-2, and 110-3 by discontinuous SS 108-1 and 108-2 that provide electrical connections between word lines at the same level.

[0069] refer to Figure 3A , the memory block 100A includes two core array regions 51-1 and 51-2 and a step structure region 52 located between the two. In this case, the level of the step structure 52 rises from the center of the memory block 100A toward the core array regions 51-1 and 51-2 located on opposite sides thereof. Figure 3B The memory block 100B includes two stepped structure regions 52-1 and 52-2 and a core array region 51 located between the two. The memory block 100B has Figure 1 The memory block 100 is similarly configured as shown. In this case, the levels of the stepped structures 52-1 and 52-2 rise from opposite sides of the memory block 100B toward the core array region 51 located at the center thereof.

[0070] The memory blocks 100A and 100B are exemplary configurations of 3D memory blocks that may be implemented in a 3D memory device to provide a desired data storage capacity. However, the 3D memory device described herein is not limited thereto. The 3D memory block may have a configuration greater than that in the above Figure 3A and Figure 3B . For example, a memory block may have a plurality of alternating core array regions 51 and staircase regions 52 formed by a plurality of memory structures 50 (e.g., 3, 4, 5, 6 or more memory structures). In some cases, a 3D memory block may not have any staircase regions and use different structures for word line pickup and fan-out, such as word line pickup structures and / or through-chip vias that penetrate the material layer stack. The method described below for stabilizing a 3D memory architecture may be implemented for all such memory blocks.

[0071] Figure 41 is a top view of an example of a semiconductor die 30 on which a plurality of 3D memory devices 10-1, ..., 10-15 are fabricated. These 3D memory devices 10 may be separated and may be used in integrated circuits and / or electronic devices for data storage and retrieval, for example, these 3D memory devices 10 may be combined with a memory controller. The specific number of 3D memory devices 10 fabricated on the die 30 may vary and depend on the specific manufacturing process implemented. Large-scale manufacturing techniques may produce a large number of 3D memory devices 10 simultaneously. However, horizontal edge stresses 31 between adjacent 3D memory devices 10 may be significant and may increase the prevalence of defects in the 3D memory devices 10 during fabrication. For example, the edge stresses 31 may induce shear stresses in the 3D memory devices 10 to which 3D memory architectures are generally susceptible.

[0072] Figure 5 2 is a top view showing an example of a 3D memory device 10 including a plurality of memory planes 20-1, ..., 20-9. The memory planes 20 generally provide a specific data storage capacity, for example, by organizing a plurality of memory blocks in a linear array. Figure 5 , nine storage planes 20 of equal size are shown, but the 3D memory device 10 may include any number of storage planes, for example, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 or more storage planes. Each storage plane 20 may have different sizes, but it is generally desirable to have consistent sizes from the standpoint of manufacturing and application. As mentioned above, similar to the edge stress 31 between adjacent 3D memory devices 10, the edge stress 21 between adjacent storage planes 20 may increase the prevalence of defects in the storage planes 20-1, ..., 20-9. The edge stresses 21 and 31 may originate from various defects, such as imperfect deposition of material layers, imperfect etching of layers and semiconductor channels, etc. The edge stresses 21 and 31 generally increase with the increase in the number of layers of the 3D architecture and / or the increase in the height of the 3D architecture. For example, due to increased loads, an increased number of bonding surfaces and / or imperfect layer deposition, the 3D architecture may tend to deform, which will induce significant stresses near the edges of the storage plane 20 .

[0073] Fig. 6Ais a top view showing an example of a defective storage plane 20* produced by edge stress 21 and / or 31. The defective storage plane 20* includes a linear array of storage blocks, wherein the storage blocks are divided into individual units by continuous gate line gaps (SS) 308. The continuous SS 308 can also electrically isolate adjacent storage blocks in the array, for example, by providing a liner for the SS 308 or filling the SS 308 with an insulating material. The storage blocks can share a common substrate, so that the storage blocks on the storage plane 20* are simultaneously made using a stack of material layers deposited on the substrate. For example, the stack of material layers can be etched, and various other materials can be deposited to form storage blocks and different components of storage blocks, such as SS, semiconductor channels, bit lines, word lines, metal contact vias, step structures, etc. The storage blocks can also share some components (e.g., bit lines) with each other to achieve some purposes, such as storage cell row selection.

[0074] The linear array includes a plurality of defective memory blocks 100*-1, ..., 100*-3 and a plurality of functional memory blocks 100-1, ..., 100-4 near the edge 25 of the memory surface 20*. Generally speaking, the edge stresses 21 and 31 cause most defects in the memory blocks 100* near the edge 25 of the memory surface 20*. Defective memory blocks 100* with significant defects and / or dimensional changes are usually sacrificed and cannot be used for data storage. This limits the total storage capacity of the memory surface 20*. Therefore, it is desirable to minimize the number of defective memory blocks 100* in the memory surface.

[0075] Figure 6B 1 is a top view showing an example of a defective memory block 100* having two fingers 110-1 and 110-2 separated by a discontinuous SS 108. For the sake of clarity, components such as semiconductor channels, bit lines, metal contact vias, etc. are omitted. In this case, the defective memory block 100* has a configuration similar to the memory block 100A, which has a stepped structure area 52 located between two core array areas 51-1 and 51-2. The edge stresses 21 and 31 may cause significant defects and / or changes in one or more portions 208* of the discontinuous SS 108, and cause other defects. Since electronic devices may be sensitive to feature size and consistency, the defects and / or changes may cause unpredictable and / or degraded performance of the memory block 100*. For example, the defective portion 208* may change the conductive characteristics between adjacent fingers 110, which may increase the probability of word line connection failure. The connection failure may increase data programming errors (e.g., incorrect programming of one or more memory cells) and / or make the memory block 100* inoperable.

[0076] Figure 6Cis a top view showing an example of a defective portion 208* caused by edge stress 21 and / or 31 of a discontinuous SS. Defective portion 208*-1 has a tapered profile such that the width of portion 208*-1 varies throughout its length. Defective portion 208*-2 has a curved profile such that the length of portion 208*-2 has a shape similar to an "S". Defective portion 208* may vary in many other ways, all of which may be detrimental to the performance of the memory block, for example, by causing word line connection failures.

[0077] Fig. 7A 4 is a top view showing an example of a storage plane 20 including a dummy region 40. The dummy region 40 is adjacent to the edge 25 of the storage plane 20 and absorbs most of the edge stress 21. The storage plane 20 includes a linear array of storage blocks 100-1, ..., 100-5, which are separated from each other and electrically isolated by continuous SS 308. The dummy region 40 is located between the edge 25 and the storage blocks 100-1, ..., 100-5, so as to stabilize the storage plane 20 and alleviate defects in the storage blocks 100-1, ..., 100-5. In general, the dummy region 40 includes one or more dummy storage blocks, that is, storage blocks that are intentionally sacrificed to maintain and increase the number of functional storage blocks 100-1, ..., 100-5 in the storage plane 20. For example, as a demonstration, the storage plane 20 includes five functional storage blocks compared to the four functional storage blocks in the defective storage plane 20*. Accordingly, the storage plane 20 provides an increased data storage capacity. A properly optimized dummy region 40 can gain benefits in both the number and height of functional memory blocks 100, thereby increasing both storage density and total capacity. As described below, the dummy blocks in the dummy region 40 are made using discontinuous SS of different patterns, which provide improved structural stability and reduced defect accumulation in the memory block 100.

[0078] like Fig. 7A As shown in , the storage surface 20 includes a single dummy area 40 adjacent to the top edge 25. However, the dummy area 40 can be located in any area of ​​the storage surface 20. Alternatively or additionally, multiple dummy areas can be implemented into the storage surface 20. For example, the dummy area can be adjacent to the top edge 25, the bottom edge or both. The dummy area can also be located between different storage blocks 100 in the storage surface 20. In some cases, the dummy area located in the storage surface 20 can alleviate the deformation caused by internal stress. In general, the storage surface 20 can include one or more dummy areas, each of which includes one or more dummy blocks, and the dummy blocks are located at any position in the array to improve structural stability.

[0079] Figure 7B It shows Fig. 7A 2. A top view of an example of a (defect-free) memory block 100 included in the memory plane 20 of FIG. 1. The memory block 100 includes a stepped structure region 52 located between two core array regions 51-1 and 51-2, and a discontinuous SS 108 that divides the memory block 100 into two fingers 110-1 and 110-2. Due to the stability derived from the dummy region 40, the memory block 100 includes only a few defects or no defects. Figure 7C 2 is a top view showing an example of a portion 208 of a discontinuous SS 108. Figure 7C As can be seen in FIG. 2 , portion 208 is free of defects and / or variations and thus has a uniform width along its length. As mentioned above, this uniformity can allow for consistent operation of memory block 100, for example, by ensuring that electrical connections between adjacent word lines are less susceptible to failures.

[0080] Figures 8A-8C is a top view showing an example of a dummy region 40A-40C that can be implemented in a memory plane for achieving stability. In this case, the dummy region 40A-40C has a stepped structure region 52 located between two core array regions 51-1 and 51-2, but other configurations are possible, for example, as in Fig. 9B As observed in , the core array region is located between the two stepped structure regions, as well as the other configurations mentioned above.

[0081] refer to Fig. 8A , the dummy area 40A includes two dummy storage blocks 400-1 and 400-2 corresponding to two intentionally sacrificed storage blocks. The dummy blocks 400-1 and 400-2 are separated by the second type of discontinuous SS 309, and are divided into a plurality of fingers by the first type of discontinuous SS 108. In this case, the dummy block 400 in the dummy area 40A can be made by interrupting the continuous SS between adjacent storage blocks. That is, in the dummy area 40A, the second type of discontinuous SS 309 can be made to replace the continuous SS. The alternating pattern of discontinuous SS 108 and 309 provides an improved structural stability to the storage surface, otherwise its structural stability will be limited by the presence of continuous SS in the dummy area 40A. In addition, the discontinuous SS 108 and 309 can be made to support different areas of the storage surface. For example, the second type of discontinuous SS 309 includes a long portion 311 located at its center, which substantially extends the length 52a of the step structure area 52. In some embodiments, the long portion 311 has a length that is longer than the length 52a of the stepped structure region 52. Since the ascending levels of a stepped structure may tend to be unstable, the long portion 311 can provide better support than a series of short portions.

[0082] Figure 8B Another example of a dummy region 40B including two dummy blocks 400-1 and 400-2 is shown. Dummy block 400 is divided by alternating discontinuous SSs 108 of the first type and discontinuous SSs 309 of the second type, but has a different pattern than dummy region 40A. In general, since the dummy region is not used for data storage, any pattern of one or more discontinuous SSs may be implemented. Depending on the relative structure of the memory blocks in the memory plane, some patterns may be preferred over other patterns. For example, Figure 8B The alternating discontinuous SS 108 and 309 shown in FIG. 1 is similar to a running bond brick laying pattern that is sometimes used for its strength and stability.

[0083] Figure 8C Shown as Fig. 8A Another example of a dummy area 40C that is a variation of the dummy area 40A in FIG. Here, the dummy area 40C includes a semi-dummy block, for example, a dummy block 400 and a finger 110. Similarly, since the dummy area is not used for data storage, any number of dummy blocks may be used, or even portions of dummy blocks may be used.

[0084] Fig. 9A and Fig. 9B is shown with Figure 3B A top view of an example of a memory block 100 and a dummy region 40 having a configuration similar to that of a memory block 100B, wherein the memory block 100 and the dummy region 40 have a core array region 51 located between two stepped structure regions 52-1 and 52-2. One or more of the memory block 100 and the dummy region 40 may be implemented into a memory surface for data storage and structural stability. Fig. 9A and Fig. 9B As can be seen, discontinuous SS of different patterns can be used for different 3D architectures, for example, 3D architectures with core array regions and step structure regions arranged differently. In this embodiment, the first type of discontinuous SS 108 divides the memory block 100 and the dummy region into a plurality of fingers. The second type of discontinuous SS 309 separates the dummy blocks 400-1 and 400-2 from each other and can be made to replace the continuous SS in the dummy region 40A. The second type of discontinuous SS 309 also includes two long portions 311-1 and 311-2 located at the ends thereof, which substantially extend the lengths 52-1a and 52-2a of the step structure regions 52-1 and 52-2. In some embodiments, the two long portions 311-1 and 311-2 have a length greater than the lengths 52-1a and 52-2a of the step structure regions 52-1 and 52-2.

[0085] Fig.10 A schematic diagram of an exemplary system 1400 including one or more 3D memory devices is shown. System 1400 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other electronic device having a storage component located therein. Fig.10 As shown in , system 1400 may include a host 1408 and a memory system 1402, the memory system 1402 having one or more 3D memory devices 1404 and a memory controller 1406. The host 1408 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system on chip (SoC), such as an application processor (AP). The host 1408 may be configured to send data to the 3D memory device 1404 or receive data from the 3D memory device 1404.

[0086] The 3D memory device 1404 may be any combination of the 3D memory devices disclosed herein, such as NAND flash memory devices, NOR flash memory devices, phase change memory (PCM) devices, resistive memory devices, RAM memory devices, DRAM memory devices, RRAM memory devices, magnetic memory devices, spin transfer torque (STT) memory devices, and other memory devices. By using the disclosed methods (e.g., appropriately patterned SS and one or more dummy memory blocks), all such memory devices are made to have excellent stability and / or reduced defects. In some embodiments, each 3D memory device 1404 includes a NAND flash memory. The memory controller 1406 (also known as a controller circuit) is coupled to the 3D memory device 1404 and the host 1408, and is configured to control the 3D memory device 1404. For example, the controller circuit can be configured to operate the memory cells of the 3D memory device 1404 via word lines and / or bit lines. The memory controller 1406 can manage the data stored in the 3D memory device 1404 and communicate with the host 1408.

[0087] According to one aspect of the present disclosure, a three-dimensional (3D) memory device includes a storage surface, wherein the storage surface includes a first edge and a block array. The block array includes: a plurality of storage blocks configured to store data, wherein the plurality of storage blocks are separated by a continuous gap structure; and a first dummy region located between the first edge and the plurality of storage blocks. The first dummy region includes alternating first and second gap structures, wherein the first and second gap structures are discontinuous gap structures.

[0088] In some implementations, the first dummy area includes 1 to 4 dummy blocks.

[0089] In some embodiments, each dummy block includes two first gap structures among the first gap structures, and one or more second gap structures among the second gap structures are located between the two first gap structures.

[0090] In some embodiments, the storage surface includes: a second edge opposite to the first edge; and a second dummy region located between the second edge and the plurality of storage blocks, the second dummy region including alternating first gap structures and second gap structures.

[0091] In some embodiments, each memory block is divided into a plurality of fingers by a discontinuous gap structure.

[0092] In some embodiments, the block array includes a stepped structure region between two core array regions.

[0093] In some embodiments, each first slit structure includes a slit extending along the step structure region, and the slit has a length at least greater than a length of the step structure region.

[0094] In some embodiments, the block array includes a core array region located between two stepped structure regions.

[0095] In some embodiments, each block includes alternating oxide layers and tungsten layers, and for each discontinuous seam structure including alternating seams and spaces, each space includes alternating oxide layers and tungsten layers.

[0096] In some embodiments, each slot structure includes an insulating material.

[0097] In some embodiments, the insulating material is used as a liner for each slot structure.

[0098] In some embodiments, the insulating material includes at least one of oxide, carbon, or polysilicon.

[0099] In some embodiments, each gap structure is filled with a filling material.

[0100] In some embodiments, the filler material includes a conductive material.

[0101] In some embodiments, each slit of each discontinuous slit structure has a length in a range of 1 micron to 10 microns.

[0102] In some embodiments, the gaps of each discontinuous gap structure are spaced apart from each other by 1 micrometer to 10 micrometers.

[0103] In some embodiments, the continuous gap structure electrically isolates the plurality of memory blocks.

[0104] According to another aspect of the present disclosure, a system includes a three-dimensional (3D) memory device and a memory controller electrically connected to the 3D memory device, wherein the memory controller is configured to manage data to and from the 3D memory device. The 3D memory device includes a storage plane, wherein the storage plane includes a first edge and a block array. The block array includes: a plurality of storage blocks configured to store data, wherein the plurality of storage blocks are separated by a continuous gap structure; and a first dummy region located between the first edge and the plurality of storage blocks. The first dummy region includes alternating first and second gap structures, wherein the first and second gap structures are discontinuous gap structures.

[0105] According to another aspect of the present disclosure, a three-dimensional (3D) memory device includes a storage plane, wherein the storage plane includes a first edge and a block array. The block array includes: a plurality of storage blocks configured to store data, wherein the plurality of storage blocks are separated by a continuous gap structure; and one or more dummy blocks located between the first edge and the plurality of storage blocks. Each dummy block includes a first gap structure separating adjacent blocks, and one or more second gap structures dividing the dummy block into a plurality of fingers, wherein the first gap structure and the one or more second gap structures are discontinuous gap structures.

[0106] In some implementations, the block array includes 1 to 4 dummy blocks.

[0107] The above description of the specific embodiments can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance provided herein, it is intended that such adjustments and modifications fall within the meaning and scope of equivalent changes of the disclosed embodiments.

[0108] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. Accordingly, other embodiments are within the scope of the claims.

Claims

1. A three-dimensional (3D) memory device, the three-dimensional (3D) memory device comprising a storage surface, wherein: The storage surface comprises: first edge; and Block array, including: a plurality of memory blocks configured to store data, wherein the plurality of memory blocks are separated by a continuous gap structure; and A first dummy region is located between the first edge and the plurality of storage blocks, wherein the first dummy region includes alternating first gap structures and second gap structures, wherein the first gap structures and the second gap structures are discontinuous gap structures.

2. The 3D memory device according to claim 1, wherein: The first dummy area includes 1 to 4 dummy blocks.

3. The 3D memory device according to claim 2, wherein: Each dummy block includes two of the first slot structures, and wherein one or more of the second slot structures are located between the two first slot structures.

4. A 3D memory device according to any preceding claim, wherein The storage surface comprises: a second edge opposite to the first edge; and A second dummy region is located between the second edge and the plurality of memory blocks, wherein the second dummy region includes alternating first gap structures and second gap structures.

5. A 3D memory device according to any preceding claim, wherein Each memory block is divided into multiple fingers by one or more discontinuous gap structures.

6. A 3D memory device according to any preceding claim, wherein The block array includes a stepped structure region between two core array regions.

7. The 3D memory device according to claim 6, wherein: Each first slit structure includes a slit extending along the step structure region, and wherein the slit has a length at least greater than a length of the step structure region.

8. The 3D memory device according to any one of claims 1 to 5, wherein: The block array includes a core array region located between two stepped structure regions.

9. A 3D memory device according to any preceding claim, wherein Each block includes alternating oxide layers and tungsten layers, and wherein, for each discontinuous gate slot structure including alternating slots and spaces, each space includes alternating the oxide layers and the tungsten layers.

10. A 3D memory device according to any preceding claim, wherein Each slot structure includes an insulating material.

11. The 3D memory device according to claim 10, wherein: The insulating material acts as a liner for each slot structure.

12. The 3D memory device according to any one of claims 10 to 11, wherein: The insulating material includes at least one of oxide, carbon or polysilicon.

13. The 3D memory device according to any one of claims 11 to 12, wherein: Each gap structure is filled with a filling material.

14. The 3D memory device according to claim 13, wherein: The filling material includes a conductive material.

15. A 3D memory device according to any preceding claim, wherein Each slit of each discontinuous slit structure has a length in the range of 1 micrometer to 10 micrometers.

16. A 3D memory device according to any preceding claim, wherein The gaps of each discontinuous gap structure are spaced apart from each other by 1 micron to 10 microns.

17. A 3D memory device according to any preceding claim, wherein The continuous gap structure electrically isolates the plurality of memory blocks.

18. A system comprising: A three-dimensional (3D) memory device, the three-dimensional (3D) memory device comprising a memory plane, wherein the memory plane comprises: first edge; and Block array, including: a plurality of memory blocks configured to store data, wherein the plurality of memory blocks are separated by a continuous gap structure; and a first dummy region located between the first edge and the plurality of memory blocks, the first dummy region comprising alternating first slit structures and second slit structures, wherein the first slit structures and the second slit structures are discontinuous slit structures; and A memory controller is electrically connected to the 3D memory device, wherein the memory controller is configured to manage data to and from the 3D memory device.

19. A three-dimensional (3D) memory device, the three-dimensional (3D) memory device comprising a storage surface, wherein: The storage surface comprises: first edge; and Block array, including: a plurality of memory blocks configured to store data, wherein the memory blocks are separated by a continuous gap structure; and One or more dummy blocks are located between the first edge and the multiple storage blocks, each dummy block includes a first gap structure separating adjacent blocks, and one or more second gap structures dividing the dummy block into multiple fingers, wherein the first gap structure and the one or more second gap structures are discontinuous gap structures.

20. The 3D memory device of claim 19, wherein: The block array includes 1 to 4 dummy blocks.

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