Cache consistency maintenance method and device and multi-core system

Abstract

The invention provides a cache consistency maintenance method and device and a multi-core system.The method comprises the steps that a write-in pointer and an eviction pointer of a directory are obtained, and the directory comprises cache line sharing information; configuring an emergency threshold and a conventional threshold, wherein the emergency threshold is smaller than the conventional threshold; if the sum of the write-in pointer and the emergency threshold value is greater than the eviction pointer, setting a high priority, and preferentially performing directory eviction; if the sum of the write-in pointer and the emergency threshold value is less than or equal to the eviction pointer and the sum of the write-in pointer and the conventional threshold value is greater than the eviction pointer, setting a low priority, and evicting the directory; wherein the directory comprises the shared information of the cache lines, and the directory eviction means that the shared information of the cache lines which are not used for the longest time in the directory is evicted; and repeating the steps until the sum of the write-in pointer and the conventional threshold value is smaller than the eviction pointer. According to the method, available space in the catalog is guaranteed to the maximum extent to store new data, the method is suitable for a small system, catalog coverage can be guaranteed, query efficiency is improved, and query power consumption is reduced.

Description

Technical Field

[0001] The present application belongs to the field of information technology, and in particular relates to a cache consistency maintenance method, device and multi-core system. Background Art

[0002] In a computer system, cache is a high-speed memory that stores copies of recently accessed data. The role of cache is to reduce the number of times the processor accesses the (slower) memory, thereby increasing the operating speed of the system. However, when multiple processor cores (CPU cores) or multiple processor clusters (a group of cores) share the same data, ensuring that the data seen by each core or cluster is consistent is the problem that cache consistency needs to solve.

[0003] In order to maintain cache consistency, the system usually adopts a snooping consistency protocol, which ensures that the same memory data in different caches is consistent through a snooping mechanism. However, as the number of processor cores increases, snooping requests will occupy a large amount of system bus bandwidth, resulting in reduced efficiency. In order to solve the inefficiency of the snooping mechanism, a consistency maintenance device is designed, which records which processor cores share which data. This eliminates the need to frequently snoop the bus, but directly queries the consistency maintenance device. However, if the shared information is recorded in the secondary cache, it will take up a lot of space, and this space is idle when not shared. Therefore, a consistency maintenance device is used to manage the shared information. However, for small systems, hardware resources are limited, and the design of the consistency maintenance device needs to find a balance between hardware overhead and query efficiency.

[0004] Therefore, cache consistency management faces the problem of a balance between hardware overhead and query efficiency. Summary of the invention

[0005] The present application discloses a cache consistency maintenance method, device and multi-core system, which performs dynamic directory eviction by setting dynamic thresholds and priorities, maximizes the available space in the directory, is suitable for small systems, achieves the same query accuracy with smaller hardware overhead, improves query efficiency and reduces query power consumption.

[0006] Other purposes and advantages of the present application can be further understood from the technical features disclosed in the present application.

[0007] To achieve one or part or all of the above purposes or other purposes, in a first aspect, the present application provides a cache consistency maintenance method, the method comprising: obtaining a write pointer and an evict pointer of a directory, wherein the write pointer indicates a directory address currently written by the directory, the evict pointer indicates a directory address currently evicted by the directory, and the directory includes cache line sharing information; Configure emergency threshold and regular threshold, and the emergency threshold is smaller than the regular threshold; If the sum of the write pointer and the emergency threshold is greater than the eviction pointer, it is set to high priority and directory eviction is performed first; if the sum of the write pointer and the emergency threshold is less than or equal to the eviction pointer, and the sum of the write pointer and the regular threshold is greater than the eviction pointer, it is set to low priority and directory eviction is performed; where directory eviction means evicting the cache line shared information that has not been used for the longest time in the directory; Repeat the above steps until the sum of the write pointer and the normal threshold is less than the eviction pointer.

[0008] In one implementation, the method further includes: determining a maximum value of a directory address according to a space size of the directory, and restarting counting from 0 after the write pointer and the eject pointer reach the maximum value; when the eject pointer catches up with the write pointer, it indicates that the directory has been completely ejected; when the write pointer catches up with the eject pointer, it indicates that the directory is completely occupied.

[0009] In one implementation, determining the cache line in the directory that has not been used for the longest time includes: defining that the recorded cache line is located before the write pointer and after the evict pointer; When the processor accesses a cache line, if the cache line used this time has been recorded in the directory, the cache line sharing information is extracted and placed at the latest write pointer position, and the position of the remaining cache line sharing information is moved forward; if the cache line used this time has not been recorded in the directory, the cache line sharing information is placed at the latest write pointer position, and the position of the remaining cache line sharing information remains unchanged; The location after the eviction pointer is determined to be the cache line that has not been used for the longest time and shares information.

[0010] In one implementation, the method is used to maintain the consistency of data sharing between multi-core processors. When a processor accesses a cache line, a directory query first matches based on an index value, and then performs a tag value match after a successful match to confirm the cache line sharing information of the cache line in the directory; wherein the cache line sharing information includes a cache line address, the lower n bits of the cache line address are expanded as an index value, and the remaining high bits of the cache line address are used as a tag value.

[0011] In one implementation, each index value carries flag information, and the flag information includes a valid bit, a host indication bit, and a dirty data bit; When writing cache line sharing information, the valid bit and the corresponding host indication bit are pulled high, and the processor number is written into the dirty data bit, indicating that the current processor has a copy of the cache line and is in a modified state; When receiving a read transaction, the dirty data bit is set to instruct the processor to read the latest data; When an invalid transaction is received, the Go To Host indication bit instructs the processor to perform an invalid operation.

[0012] In one implementation, when the sum of the write pointer and the emergency threshold is greater than the eviction pointer, the arbitration clear bit and the priority bit are pulled high to give priority to eviction; When the sum of the write pointer and the emergency threshold is less than or equal to the eviction pointer, and the sum of the write pointer and the normal threshold is greater than the eviction pointer, eviction is performed by pulling the arbitration clear bit high and the priority bit low.

[0013] In one implementation, when the directory is evicted, the cache line continues to be written and continuously evicted at a preset eviction speed until the sum of the write pointer and the regular threshold is smaller than the eviction pointer.

[0014] In a second aspect, the present application provides a cache consistency maintenance device, which maintains the consistency of shared data between multi-core processors through the cache consistency maintenance method described in any one of the first aspects above.

[0015] In a third aspect, the present application provides a multi-core system, the system comprising a cache consistency maintenance device as described in the second aspect and multiple processor cores, the system maintaining the consistency of shared data between multi-core processors through the cache consistency maintenance method described in any one of the first aspects above; The system also includes a second-level cache shared between different processor cores in the same processor cluster and a third-level cache shared between multiple processor clusters; the consistency maintenance device includes an inter-core consistency maintenance device and an inter-cluster consistency maintenance device, the inter-core consistency maintenance device is used to maintain the second-level cache between multiple processor cores to achieve data consistency when sharing between cores, and the inter-cluster consistency maintenance device is used to maintain the third-level cache between multiple processor clusters to achieve data consistency when sharing between clusters.

[0016] In a fourth aspect, the present application provides an electronic device, comprising one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute a cache consistency maintenance method as described in any one of the first aspects.

[0017] The above-mentioned cache consistency maintenance method, device, multi-core system and electronic device can set dynamic thresholds and priorities for dynamic eviction, and can maximize the guarantee that there is available space in the directory to store new data when reading and modifying data, so that the stored directory can be monitored according to the directory record, thereby improving query efficiency and reducing query power consumption; compared with the previous large directory design at the expense of large area, the present application can be applied to small systems, and can also ensure directory coverage, that is, to achieve the same query accuracy with smaller hardware overhead, improve query efficiency and reduce query power consumption.

[0018] In order to make the above and other purposes, features and advantages of the present application more obvious and understandable, preferred embodiments are specifically listed below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 This is a flowchart of the cache consistency maintenance method of this application.

[0021] Figure 2 This is a structural block diagram of the multi-core system of this application.

[0022] Figure 3 This is a structural block diagram of the cache consistency maintenance device of this application.

[0023] Figure 4 This is a schematic diagram of the judgment process of the cache consistency maintenance method of this application. DETAILED DESCRIPTION

[0024] The aforementioned and other technical contents, features and effects of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances. This is just a way of distinguishing objects with the same attributes when describing the embodiments of the present application.

[0025] In the related art, the consistency maintenance device marks the data when the processor core reads the data in a shared manner, and clears the mark synchronously when the processor core evicts the data. The query method of the consistency maintenance device mainly includes hierarchical query and group query. Among them, the hierarchical query matches the index value, then searches for the tag value in the matching index row for matching, and when storing, it is preferred to fill the free space in the index row, and then integrate the information of the same tag value. This method needs to store a large number of indexes and tag values, and the hardware overhead is large. When the directory is full and there is no identical data, it faces the problem of reduced efficiency, and it is easy to have multiple hits. The group query divides the query address information into multiple blocks of index values. Only when the multiple blocks of index values ​​are matched can it represent a hit. The hit information of the multiple blocks of index values ​​is integrated as the final query information, which can represent more cache address information with a smaller hardware overhead, but due to the reduced correlation between the complete address information, invalid access caused by false hits follows. It can be seen that this method introduces a large number of index values ​​at a low hardware overhead cost, improves the query efficiency, but correspondingly loses the query accuracy.

[0026] In order to find a balance between hardware overhead and query efficiency, an embodiment of the present application provides a cache consistency maintenance method, which uses a directory consistency protocol and hierarchical query, dynamically manages the directory by setting thresholds and priorities, and prioritizes the elimination of locations that have not been used for the longest time or that most need reserved space. It is suitable for a variety of scenarios, and can both ensure query efficiency and take into account hardware overhead.

[0027] The present application is described in detail below in conjunction with the accompanying drawings.

[0028] refer to Figure 1 , an embodiment of the present application provides a cache consistency maintenance method, the method comprising: Step 1: Get the write pointer and evict pointer of the directory, where the write pointer indicates the directory address currently written to the directory, and the evict pointer indicates the directory address currently evicted from the directory. The directory address is the position in the directory. The directory includes cache line sharing information to indicate the sharing status and position of the cache line. The cache line sharing information specifically includes the cache line address, information of the processor host participating in the sharing, etc.

[0029] Among them, the pointer count value is not infinite, but a cycle. In this embodiment, the maximum value of the directory address is determined according to the space size in the directory, and after the write pointer and the eject pointer reach the maximum value, the count starts again from 0. With use, when the eject pointer catches up with the write pointer, the directory is considered empty, indicating that the directory has been completely ejected; when the write pointer catches up with the eject pointer, the directory is considered full, indicating that the directory is fully occupied, so that the determined write pointer and eject pointer are more accurate.

[0030] Step 2: configure an emergency threshold and a regular threshold, and the emergency threshold is smaller than the regular threshold, wherein the emergency threshold and the regular threshold are collectively referred to as the eviction threshold in this document.

[0031] Step 3: If the sum of the write pointer and the emergency threshold is greater than the eviction pointer, set it to high priority and perform directory eviction first; if the sum of the write pointer and the emergency threshold is less than or equal to the eviction pointer, and the sum of the write pointer and the regular threshold is greater than the eviction pointer, set it to low priority and perform directory eviction; wherein, the directory includes the shared information of the cache line, and the directory eviction means to evict the shared information of the cache line that has not been used for the longest time in the directory, that is, to remove the shared information of the cache line from the directory.

[0032] Step 4: Repeat the above steps until the sum of the write pointer and the regular threshold is smaller than the eviction pointer.

[0033] Specifically, when the processor needs to read data, it will first query whether the data is in the cache. If the data is in the cache, the data will be read from the corresponding cache line and returned to the processor. When the processor needs to write data, it also needs to query whether the data is in the cache. If the data is in the cache, the data will be written to the cache line. When reading or writing data, it is necessary to consider the shared consistency of the data. If multiple processors write the same data at the same time, it is necessary to ensure the consistency of the data in multiple processors. The directory is used to maintain the consistency state of each cache line, track which caches own this cache line and the state of this cache line. This method obtains the write pointer and eviction pointer of the directory, configures the dynamic eviction threshold, and judges the relationship between the write pointer, eviction threshold, and eviction pointer in real time, and prioritizes the eviction of the cache line shared information that has not been used for the longest time in the directory, so as to improve the performance of the cache and maximize the available space in the directory.

[0034] According to the above description, the cache consistency maintenance method of the embodiment of the present application makes the directory eviction method more flexible by setting dynamic thresholds and priorities. When reading and modifying data, it can maximize the guarantee that there is available space in the directory to store new data. The directory can be monitored according to the directory record, thereby improving query efficiency and reducing query power consumption. Compared with the previous large directory design at the cost of large area, the present application can be applied to small systems and can also ensure directory coverage, that is, to achieve the same query accuracy with less hardware overhead, improve query efficiency and reduce query power consumption. At the same time, the present application can optimize the dynamic management of cache space, ensure efficient use of cache, and avoid cache overflow or data loss.

[0035] The present application is described in detail below in conjunction with the cache consistency maintenance device and multi-core system provided by the present application.

[0036] refer to Figure 2, is a structural block diagram of a multi-core system applied by the cache consistency maintenance device of the embodiment of the present application. The multi-core system includes multiple processor clusters, each processor cluster includes multiple processor cores, and the multi-core system adopts a multi-level cache architecture: each processor core uses a first-level cache to achieve independent cache, the same processor cluster uses a second-level cache to achieve inter-core sharing, and multiple processor clusters use a third-level cache to achieve inter-cluster sharing. In the figure, AXI, ACE and CHI are extension interfaces for interconnection protocols in multi-core systems.

[0037] The cache consistency maintenance device of the embodiment of the present application includes an inter-core consistency maintenance device and an inter-cluster consistency maintenance device. The inter-core consistency maintenance device is used to ensure data consistency when the secondary cache is shared between multiple processor cores, and the inter-cluster consistency maintenance device is used to ensure data consistency when the third-level cache is shared between multiple processor clusters. It should be noted that for the convenience of description, the detailed description of the inter-core consistency maintenance device and the inter-cluster consistency maintenance device below, if not specifically distinguished, are uniformly referred to as consistency maintenance devices, and will not be repeated below.

[0038] The consistency maintenance device of this embodiment is a device based on hierarchical query and directory consistency, and adopts an eviction mechanism to manage the space of the consistency maintenance device. The consistency maintenance device of this application balances the hardware overhead and dynamically evicts the locations that have not been used for a long time or the locations that currently need to reserve space the most, so as to achieve efficient maintenance of the consistency maintenance device.

[0039] Specifically, during the search process, the consistency maintenance device first matches the index value, and after success, searches for the tag value in the index row for a match. If the match is successful, it is considered a hit, indicating that the current data has been shared and an operation needs to be performed on the specified processor core; if the match fails, it is considered a miss, indicating that the current data has not been shared. If the data exists in the L2 / L3 cache, it can be returned directly. After the data response is returned, the consistency maintenance device updates the information about the shared processor core in the row. At the same time, the consistency maintenance device of this embodiment allows the user to configure the eviction threshold and eviction priority. When the space margin is less than the set threshold, it will spontaneously evict or prioritize eviction to adapt to different application scenarios and improve operating efficiency.

[0040] More specifically, see Figure 1 When processor core 0 in processor cluster 0 needs to read and modify data, it first queries its own first-level cache. If it misses, it queries the second-level cache and the consistency maintenance device within the cluster to check whether it is shared in processor cores 1 to n-1.

[0041] If only the L2 cache hits, it means that the current data is not shared by the processor cores, and the data will be returned from the L2 cache to the processor core 0 and the exclusive core will be recorded by the intra-cluster consistency maintenance device.

[0042] If all misses, query the third-level cache and the inter-cluster consistency maintenance device to check whether it is shared in processor cluster 1 to processor cluster n-1.

[0043] If only the L3 cache hits, it means that the current data is not shared by the processor cluster, and the data will be returned from the L3 cache to processor cluster 0 and the inter-cluster consistency maintenance device will record the exclusive cluster.

[0044] If both the L3 cache and the inter-cluster consistency maintenance device indicate a hit, it means that other clusters are sharing, and the processor cluster (such as processor cluster n-1) needs to be invalidated first and the cache line in the modified state (Modified state in the MESI protocol) needs to be written back to the main memory. Send the invalidation request to processor cluster n-1 as instructed. After receiving the request, query the L2 cache and the intra-cluster consistency maintenance device, invalidate the data in the L2 / L1 cache as instructed, and write the modified state data back to the main memory to complete the request.

[0045] refer to Figure 3, is a structural block diagram of the consistency maintenance device provided in this embodiment, and the consistency maintenance device includes an index value, a valid bit, a tag value, and an indication. The consistency maintenance device of this embodiment queries the directory hierarchically, and then matches the tag value after the index value matches successfully, so as to confirm the cache line sharing information of the cache line in the directory. In addition to carrying address information, the cache line sharing information carries three flag information (valid bit, host indication bit, and dirty data bit). Among them, the index is used to locate the cache line address, and each cache line has an index for locating the line in the consistency maintenance device. The figure shows multiple index values ​​(index 0 to index n-1), and each index value corresponds to a cache line. The valid bit is used to indicate whether it is a hit. If there is a shared information record in the current address line, it remains high, prompting the consistency maintenance device to hit, that is, the valid bit can indicate whether the cache line is valid. Each cache line has a valid bit to indicate whether the line stores valid data. For example, if the valid bit is 1, it means that the line is valid; if it is 0, it means that the line is invalid. The tag value is used to indicate the main memory block corresponding to the cache line. When the processor accesses the cache line data, it uses the tag part of the cache line address to match the tag value in the consistency maintenance device to determine whether the data is in the cache. The indication is used to indicate the shared state and modified state of the data. The indication includes a host indication bit and a dirty data bit. The host indication bit is used to indicate which processor cores / clusters the hit address exists in, that is, which processor cores or clusters have a copy of the cache line. The dirty data bit is used to indicate which processor core / cluster the hit address modification state copy exists in, that is, whether the data in the cache line has been modified (that is, dirty data). For example, if the dirty data bit is 1, it means that the row of data has been modified and the data in the main memory needs to be updated when it is written back to the main memory. When facing a dirty data write-back transaction, the request only needs to be forwarded to the location of the modification state copy, without having to be forwarded to all shared processor cores.

[0046] Exemplarily, when a processor accesses data, an index value is used to match a tag value in a consistency maintenance device. If a matching tag value is found and the valid bit is 1, it means that the data is in the cache and the data can be read directly from the cache. Through the host indicator bit and the dirty data bit, the consistency maintenance device can track the sharing status and modification status of the data. When a processor modifies the data in the cache line, the dirty data bit is set to 1, and the host indicator bit is updated to reflect the sharing status of the data. When the cache line needs to be replaced, if the dirty data bit is 1, the modified data needs to be written back to the main memory. The consistency maintenance device will instruct to write the data back to the correct location in the main memory. Through the host indicator bit, the consistency maintenance device can track which processor cores or clusters have a copy of the cache line. When a processor accesses data, if the host indicator bit shows that other processor cores or clusters also have a copy of the cache line, a consistency protocol needs to be executed to ensure that the data seen by all processor cores or clusters is consistent.

[0047] In some embodiments, the consistency maintenance device includes m paths, that is, each index value can store up to m different tag values. The system writes the consistency maintenance device information, expands the lower n bits of the cache line address as the index value, and writes the remaining high bits into the line as the tag value according to the index value, pulls up the valid bit and the corresponding host indication bit, and writes the processor core number into the dirty data bit, indicating that the current processor core / cluster has a copy and is in a modified state. When a read transaction is received, it will go to the dirty data bit to instruct the processor core to read the latest data; when an invalid transaction is received, it will go to the host indication bit to instruct the processor core to perform an invalid operation.

[0048] As addresses are continuously written, the consistency maintenance device will eventually become full. Figure 4 , which is a judgment flow chart of the consistency maintenance device executing the maintenance method. The consistency maintenance device confirms the write position through the write pointer and confirms the evict position through the evict pointer. The evict object is the cache line shared information that has not been used for the longest time.

[0049] In this embodiment, the cache line sharing information used each time is placed at the latest write pointer position, and the remaining cache line sharing information is moved before the latest write pointer position, and the front cache line sharing information is determined as the longest unused, so as to more quickly and accurately determine the eviction object for eviction operation. Specifically, the sharing information of the cache line where the data exists is located before the write pointer and after the eviction pointer, and the before and after here represent the front and back of the pointer movement direction. Therefore, it is defined that the recorded cache line sharing information is located before the write pointer and after the eviction pointer; if the cache line sharing information used this time has been recorded in the directory, the cache line sharing information is extracted and placed at the latest write pointer position, and the position of the remaining cache line sharing information is moved forward; if the cache line sharing information used this time has not been recorded in the directory, the cache line sharing information is placed at the latest write pointer position, and the position of the remaining cache line sharing information remains unchanged; the position after the eviction pointer is determined to be the cache line sharing information that has not been used for the longest time, and the position before the write pointer is determined to be the latest used cache line sharing information. For example, assume that there are 10 cache lines sharing information space in the directory: 1-10. If the current write pointer position is 2 and the eviction pointer position is 5, the data exists at 5, 6, 7, 8, 9, 10, and 1. The next data will be stored at position 2, and the next data will be evicted at position 5.

[0050] At the beginning of use, two thresholds are set through parameters, namely the regular threshold and the emergency threshold. When the processor core accesses a cache line, it is determined whether the sum of the write pointer and the emergency threshold exceeds the eviction pointer. If it exceeds, it means that the risk of data in this index line being full is high, and it is necessary to raise the arbitration clear bit and the priority bit, and eviction is prioritized. The number of evictions is 1. The eviction process does not affect the writing of new data, so the actual number of evictions may be greater than 1, that is, it is always evicted until the sum of the write pointer and the emergency threshold is less than the eviction pointer. If it does not exceed, it is determined whether the sum of the write pointer and the regular threshold exceeds the eviction pointer. If it exceeds, it means that the current margin (margin) is less than the regular threshold, and it is necessary to raise the arbitration clear bit, invalidate the data copy and write the modified status data therein back to the main memory. At this time, the eviction does not set the priority, and the number of evictions may also be greater than 1, and it is always evicted until the sum of the write pointer and the regular threshold is less than the eviction pointer.

[0051] Due to the real-time maintenance function, the consistency maintenance device can ensure the same query accuracy with relatively small hardware overhead. At the same time, the read operation only goes to the modified state processor core for monitoring, which further reduces the number of accesses. The setting of dynamic thresholds makes the eviction method of the consistency maintenance device more flexible. Therefore, while maintaining less hardware overhead, the advantage of maintaining the consistency of the second / third level cache is faster query speed and lower query power consumption.

[0052] In summary, the consistency maintenance device and multi-core system of the present application can record cache line sharing information, maintain cache consistency, and reduce query power consumption; compared with the traditional hierarchical query consistency maintenance device, it retains the advantages of query accuracy while taking into account low hardware overhead, and allows adjustment of eviction thresholds and eviction priorities; compared with the grouped query consistency maintenance device, it has the advantage of no false hits, clearer instructions for read operations, and reduces the number of unnecessary accesses.

[0053] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0054] Based on the same inventive concept, the embodiment of the present application also provides a cache consistency maintenance device, which maintains the consistency of shared data between multi-core processors through the cache consistency maintenance method of any of the above embodiments. The implementation scheme of the cache consistency maintenance device to solve the problem is similar to the implementation scheme recorded in the above method, so the specific limitations in the cache consistency maintenance device embodiment provided below can refer to the limitations of a cache consistency maintenance method above, and will not be repeated here.

[0055] In one embodiment, the present application also provides a multi-core system, which includes a cache consistency maintenance device and multiple processor cores as in the above embodiment, and the system maintains the consistency of shared data between multi-core processors through the cache consistency maintenance method of any of the above embodiments. The system also includes a secondary cache for sharing between different processor cores in the same processor cluster, and a third-level cache for sharing between multiple processor clusters; the consistency maintenance device includes an inter-core consistency maintenance device and an inter-cluster consistency maintenance device, the inter-core consistency maintenance device is used to maintain the data consistency of the secondary cache between multiple processor cores when sharing between cores, and the inter-cluster consistency maintenance device is used to maintain the data consistency of the third-level cache between multiple processor clusters when sharing between clusters.

[0056] In one embodiment, the present application also provides an electronic device, which includes one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute a cache consistency maintenance method such as any of the above embodiments.

[0057] It should be noted that, for those of ordinary skill in the art, several improvements and modifications may be made to the present application without departing from the principles of the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application. It should be understood that certain features of the present disclosure described in the context of a separate embodiment for the sake of clarity may also be provided in a single embodiment by combination. Conversely, various features of the present disclosure described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present disclosure.

Claims

1. A cache consistency maintenance method, characterized in that: The method comprises: Acquire a write pointer and an evict pointer of a directory, wherein the write pointer indicates a directory address currently written by the directory, and the evict pointer indicates a directory address currently evicted by the directory, and the directory includes cache line sharing information; An emergency threshold and a regular threshold are configured, and the emergency threshold is smaller than the regular threshold; If the sum of the write pointer and the emergency threshold is greater than the eviction pointer, it is set to a high priority and directory eviction is performed first; if the sum of the write pointer and the emergency threshold is less than or equal to the eviction pointer, and the sum of the write pointer and the regular threshold is greater than the eviction pointer, it is set to a low priority and directory eviction is performed; wherein the directory eviction means evicting the cache line shared information that has not been used for the longest time in the directory; The above steps are repeated until the sum of the write pointer and the regular threshold is smaller than the eviction pointer.

2. A cache consistency maintenance method according to claim 1, characterized in that: The method further includes: determining a maximum value of a directory address according to the space size of the directory, and restarting counting from 0 after the write pointer and the eject pointer reach the maximum value; when the eject pointer catches up with the write pointer, it indicates that the directory has been completely ejected; when the write pointer catches up with the eject pointer, it indicates that the directory is completely occupied.

3. A cache consistency maintenance method according to claim 1, characterized in that: Determining the cache line in the directory that has not been used for the longest time includes: defining that the recorded cache line is located before the write pointer and after the evict pointer; When the processor accesses a cache line, if the cache line used this time has been recorded in the directory, the cache line sharing information is extracted and placed at the latest write pointer position, and the position of the remaining cache line sharing information is moved forward; if the cache line used this time has not been recorded in the directory, the cache line sharing information is placed at the latest write pointer position, and the position of the remaining cache line sharing information remains unchanged; The position after the eviction pointer is determined as the cache line sharing information that has not been used for the longest time.

4. A cache consistency maintenance method according to claim 1, characterized in that: The method is used to maintain the consistency of data sharing between multi-core processors. When a processor accesses a cache line, a directory query first matches based on an index value, and then performs a tag value match after a successful match, so as to confirm the cache line sharing information of the cache line in the directory; wherein the cache line sharing information includes a cache line address, the lower n bits of the cache line address are expanded as an index value, and the remaining high bits of the cache line address are used as a tag value.

5. A cache consistency maintenance method according to claim 4, characterized in that: Each index value carries flag information, and the flag information includes a valid bit, a host indication bit, and a dirty data bit; When writing cache line sharing information, the valid bit and the corresponding host indication bit are pulled high, and the processor number is written into the dirty data bit, indicating that the current processor has a copy of the cache line and is in a modified state; When receiving a read transaction, the dirty data bit is set to instruct the processor to read the latest data; When an invalid transaction is received, the Go To Host indication bit instructs the processor to perform an invalid operation.

6. A cache consistency maintenance method according to claim 1, characterized in that: In the case where the sum of the write pointer and the emergency threshold is greater than the ejection pointer, the ejection is performed with priority by pulling up the arbitration clear bit and the priority bit; When the sum of the write pointer and the emergency threshold is less than or equal to the eviction pointer, and the sum of the write pointer and the normal threshold is greater than the eviction pointer, eviction is performed by pulling the arbitration clear bit high and pulling the priority bit low.

7. A cache consistency maintenance method according to claim 6, characterized in that: During directory eviction, cache lines continue to be written and continuously evicted at a preset eviction speed until the sum of the write pointer and the regular threshold is less than the eviction pointer.

8. A cache consistency maintenance device, characterized in that: The device maintains the consistency of shared data between multi-core processors through the cache consistency maintenance method described in any one of claims 1 to 7.

9. A multi-core system, characterized in that: The system comprises a cache consistency maintenance device as described in claim 8 and a plurality of processor cores, and the system maintains the consistency of shared data between multi-core processors through the cache consistency maintenance method as described in any one of claims 1 to 7 above; The system also includes a second-level cache shared between different processor cores in the same processor cluster and a third-level cache shared between multiple processor clusters; the consistency maintenance device includes an inter-core consistency maintenance device and an inter-cluster consistency maintenance device, the inter-core consistency maintenance device is used to maintain the second-level cache between multiple processor cores to achieve data consistency when sharing between cores, and the inter-cluster consistency maintenance device is used to maintain the third-level cache between multiple processor clusters to achieve data consistency when sharing between clusters.

10. An electronic device, characterized in that: The electronic device includes one or more processors; a memory; and one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, and the one or more applications are configured to execute a cache consistency maintenance method as described in any one of claims 1-7.

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