Chip calibration method and device, storage medium and electronic equipment

Abstract

The embodiment of the invention discloses a chip calibration method and device, a storage medium and electronic equipment, relates to the technical field of communication, and aims to solve the problem of performance reduction caused by time interleaving errors of a chip of a time interleaving architecture in the prior art. According to the method, firstly, the error calculation of the whole link is carried out by directly collecting the digital result output by the ADC, then optimization iteration is carried out in the simulation domain according to the calculated time interleaving error, the numerical value of the corresponding sub-ADC channel register is adjusted, the register is updated in a register control code mode, and the time interleaving error of the whole link is calculated. The offset error, the gain error and the clock offset between the sub-ADC channels are corrected, and finally the chip is calibrated, so that the performance of the chip is improved.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a chip calibration method, device, storage medium and electronic device. Background Art

[0002] With the rapid development of technologies in the fields of radar, electronic countermeasures, navigation, and communications, and the updating and iteration of related devices and equipment, high-speed broadband electronic measuring instruments represented by oscilloscopes will become important equipment for testing the electromagnetic performance of complete equipment and the electronic performance of various information payload systems it carries. The key to the successful development of related high-end instruments lies in the design and manufacture of core chips such as high-speed and large-bandwidth analog-to-digital converters (ADCs). Ultra-high-speed, medium- and low-precision high-performance ADC circuits are key circuit modules in mixed signal processing systems, and their performance directly affects the performance of the entire circuit system. However, in ADCs that use a time-interleaved architecture, the time-interleaving error between different sub-ADC channels will lead to a loss in signal-to-noise ratio, thereby reducing the effective number of bits of the ADC chip. Summary of the invention

[0003] The main purpose of the present application is to provide a chip calibration method, device, storage medium and electronic device, aiming to solve the problem of performance degradation caused by time interleaving errors in chips with time interleaving architecture in the prior art.

[0004] To achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0005] In a first aspect, an embodiment of the present application provides a chip calibration method, comprising the following steps:

[0006] Initialize register configuration;

[0007] Perform data acquisition based on the calibration instruction to obtain the ADC digital output result;

[0008] Calculate the time interleaving error according to the ADC digital output result; wherein the time interleaving error includes the offset error, gain error or sampling clock offset between the sub-ADC channels;

[0009] According to the time interleaving error, the register value of the sub-ADC channel is adjusted and the register control code is obtained;

[0010] Update the register according to the register control code, and return to the step of collecting data based on the calibration instruction to obtain the ADC digital output result until the iteration termination condition is met and the register target value is obtained;

[0011] According to the register target value, the target register is obtained to realize chip calibration.

[0012] In a possible implementation manner of the first aspect, adjusting a register value of a sub-ADC channel and obtaining a register control code according to a time interleaving error includes:

[0013] According to the size of the time interleaving error, the direction, iteration direction and iteration step size are changed;

[0014] According to the iteration direction and the iteration step, the register value of the sub-ADC channel is adjusted and the register control code is obtained.

[0015] In a possible implementation manner of the first aspect, before adjusting the register value of the sub-ADC channel and obtaining the register control code according to the time interleaving error, the method further includes:

[0016] According to the adjustable range of the register, determine the register adjustment reference value;

[0017] According to the time interleaving error, the register value of the sub-ADC channel is adjusted and the register control code is obtained, including:

[0018] According to the time interleaving error and the register adjustment reference value, the register value of the sub-ADC channel is adjusted and the register control code is obtained.

[0019] In a possible implementation manner of the first aspect, initializing the configuration of the register includes:

[0020] According to the adjustable range of the register, the register is adjusted to an intermediate value state of the adjustable range of the register to achieve initialization configuration.

[0021] In a possible implementation manner of the first aspect, before calculating the time interleaving error according to the ADC digital output result, the method further includes:

[0022] Split the ADC digital output results into equal intervals to obtain multi-channel ADC data;

[0023] Based on the sub-ADC data, calculate the time interleaving error, including:

[0024] Calculate the time interleaving error based on the digital output results of multiple ADCs.

[0025] In a possible implementation manner of the first aspect, calculating the time interleaving error according to the ADC digital output result includes:

[0026] According to the ADC digital output result, the time interleaving error is calculated by using the estimation method based on digital domain Fourier transform.

[0027] In a possible implementation manner of the first aspect, the iteration termination condition includes: a change in adjustment variance between two adjacent iterations is less than a preset threshold value.

[0028] In a second aspect, an embodiment of the present application provides a chip calibration device, comprising:

[0029] Initialization module, the initialization module is used to initialize the configuration of registers;

[0030] The acquisition module is used to collect data based on the calibration instructions to obtain the ADC digital output results;

[0031] A calculation module, the calculation module is used to calculate a time interleaving error according to an ADC digital output result; wherein the time interleaving error includes an offset error, a gain error or a sampling clock offset between sub-ADC channels;

[0032] An adjustment module, the adjustment module is used to adjust the register value of the sub-ADC channel and obtain a register control code according to the time interleaving error;

[0033] Iteration module, which is used to update the register according to the register control code, and return to collect data based on the calibration instruction to obtain the ADC digital output result until the iteration termination condition is met to obtain the register target value;

[0034] The calibration module is used to obtain the target register according to the register target value to realize chip calibration.

[0035] In a third aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program. When the computer program is loaded and executed by a processor, the chip calibration method provided in any one of the first aspects above is implemented.

[0036] In a fourth aspect, an embodiment of the present application provides an electronic device, including a processor and a memory, wherein:

[0037] The memory is used to store computer programs;

[0038] The processor is used to load and execute a computer program so that the electronic device executes the chip calibration method provided in any one of the first aspects above.

[0039] Compared with the prior art, the beneficial effects of this application are:

[0040] The chip calibration method, device, storage medium and electronic device proposed in the embodiment of the present application include: initializing the configuration of the register; collecting data based on the calibration instruction to obtain the ADC digital output result; calculating the time interleaving error according to the ADC digital output result; wherein the time interleaving error includes the offset error, gain error or sampling clock offset between the sub-ADC channels; adjusting the register value of the sub-ADC channel and obtaining the register control code according to the time interleaving error; updating the register according to the register control code, and returning to the step of collecting data based on the calibration instruction to obtain the ADC digital output result until the iteration termination condition is met to obtain the register target value; according to the register target value, obtaining the target register to realize chip calibration. The present application first calculates the error of the entire link by directly collecting the digital result of the ADC output, and then optimizes and iterates in the analog domain according to the calculated time interleaving error, and adjusts the corresponding sub-ADC channel register value, and updates the register in the form of the register control code, so as to correct the offset error, gain error and clock offset between the sub-ADC channels, and finally realizes the calibration of the chip, so that the chip performance is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A schematic diagram of the structure of an electronic device of a hardware operating environment involved in an embodiment of the present application;

[0042] Figure 2 A schematic diagram of a chip calibration method according to an embodiment of the present application;

[0043] Figure 3 A core block diagram of an ADC chip in a chip calibration method provided in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of a flow chart of a chip calibration method provided in an embodiment of the present application in one implementation manner;

[0045] Figure 5 A schematic diagram of the variation of the bias error during the calibration process of the chip calibration method provided in an embodiment of the present application;

[0046] Figure 6 A schematic diagram of gain error variation during the calibration process of the chip calibration method provided in an embodiment of the present application;

[0047] Figure 7 A schematic diagram of phase error variation during the calibration process of the chip calibration method provided in an embodiment of the present application;

[0048] Figure 8 A schematic diagram of the change of the differential nonlinearity (DNL) static index of the ADC chip before and after the calibration process of the chip calibration method provided in an embodiment of the present application;

[0049] Fig. 9 A schematic diagram of the change of the static index of the integral nonlinearity (INL) of the ADC chip before and after the calibration process of the chip calibration method provided in an embodiment of the present application;

[0050] Fig.10 A schematic diagram of signal waveforms before and after calibration of the chip calibration method provided in an embodiment of the present application;

[0051] Fig.11 A schematic diagram of a module of a chip calibration device provided in an embodiment of the present application;

[0052] Markings in the figure: 101 - processor, 102 - communication bus, 103 - network interface, 104 - user interface, 105 - memory. DETAILED DESCRIPTION

[0053] It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0054] See attached Figure 1 , attached Figure 1 This is a schematic diagram of the structure of an electronic device of the hardware operating environment involved in the embodiment of the present application. The electronic device may include: a processor 101, such as a central processing unit (CPU), a communication bus 102, a user interface 104, a network interface 103, and a memory 105. Among them, the communication bus 102 is used to realize the connection and communication between these components. The user interface 104 may include a display screen (Display), an input unit such as a keyboard (Keyboard), and the user interface 104 may also include a standard wired interface and a wireless interface. The network interface 103 may optionally include a standard wired interface and a wireless interface (such as a wireless fidelity (WIreless-FIdelity, WI-FI) interface). The memory 105 may optionally be a storage device independent of the aforementioned processor 101. The memory 105 may be a high-speed random access memory (RAM) memory, or it may be a stable non-volatile memory (NVM), such as at least one disk storage; the processor 101 may be a general-purpose processor, including a central processing unit, a network processor, etc., or it may be a digital signal processor, an application-specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component.

[0055] Those skilled in the art will appreciate that Figure 1The structure shown in the figure does not constitute a limitation on the electronic device, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0056] As attached Figure 1 As shown, the memory 105 as a storage medium may include an operating system, a network communication module, a user interface module and a chip calibration device.

[0057] In the attached Figure 1 In the electronic device shown, the network interface 103 is mainly used for data communication with a network server; the user interface 104 is mainly used for data interaction with a user; the processor 101 and the memory 105 in the present application can be set in the electronic device, and the electronic device calls the chip calibration device stored in the memory 105 through the processor 101, and executes the chip calibration method provided in the embodiment of the present application.

[0058] With the rapid development of technologies in the fields of radar, electronic countermeasures, navigation, and communications, and the updating and iteration of related devices and equipment, high-speed broadband electronic measuring instruments represented by oscilloscopes will become important equipment for testing the electromagnetic performance of complete equipment and the electronic performance of various information payload systems it carries. The key to the successful development of related high-end instruments lies in the design and manufacture of core chips such as high-speed and large-bandwidth analog-to-digital converters (ADCs). Existing technologies have made breakthroughs in achieving high-precision, high-speed, and high-reliability signal acquisition and conversion technologies, and currently have the ability to design and manufacture chips for related industries. However, due to limited market demand, chip iterations are relatively slow.

[0059] Ultra-high-speed, medium-low precision, high-performance ADC circuits are key circuit modules in mixed signal processing systems, and their performance directly affects the performance of the entire circuit system. Ultra-high-speed ADCs can achieve very high conversion rates based on compound semiconductor processes such as SiGe, GaAs or InP, but according to the latest research, compared with other process designs, ADC chips designed based on advanced CMOS processes are still the mainstream trend in related chip design because of their advantages such as low power consumption, low cost, and high circuit integration. In advanced CMOS processes, ultra-high-speed, medium-low resolution ADCs, such as those greater than 10GSa / s and less than or equal to 8-bit, mostly use time-interleaved architectures, that is, multiple low-sampling rate sub-ADCs are time-interleaved and spliced. One of the related core technologies is the estimation and correction of offset errors, gain errors, and clock offsets between interleaved channels of sub-ADCs. Offset, gain, and timing mismatches between different sub-ADC channels will lead to a loss in SNR signal-to-noise ratio, thereby reducing the effective number of bits of the ADC chip.

[0060] Therefore, refer to the attached Figure 2Based on the hardware device of the above embodiment, the embodiment of the present application provides a chip calibration method to solve the above problem, as shown in the attached Figure 3 The figure shows the core block diagram of the direct sampling ADC chip with a sampling rate of 80GSa / s and a bandwidth of 18GHz. The chip consists of an 8-bit 80GSa / s ADC core, a high-speed serial port, a PLL and other devices. The 0GHz-18GHz analog signal is distributed to each SubADC through the ADC Input Net (which includes T-coil input matching, various levels of Driver, transmission line matching, etc.). After analog-to-digital conversion, each Sub ADC generates 32 8-bit 2.5GSa / s digital signals, which are sent to Serdes after serial-to-parallel conversion, and the 32 Serdes output 640Gbps sampled data. In order to achieve clock synchronization of multiple parallel Sub ADCs, the system design uses a differential input 20GHz clock, generates 32 2.5GHz interleaved clocks through Clock Gen and sends them to each Sub ADC, and ensures synchronization through the clock generated by the PLL and SYNC modules. Among them, ADC Input Net is the ADC input network, Sub ADC is the sub-ADC, Serdes is the parallel-to-serial converter, PLL&SYNC is the clock phase-locked loop and synchronization, Analog Input is the sampling signal input, ADC Clock Net is the ADC clock signal, Clock Gen is the clock signal generation, Clock and SYNC are the external clock and synchronization signals, BGR&LDO is the ADC power supply port, and TX0 / TX1 to TX31 are the ADC output ports. At the same time, in order to reduce the requirements for the drive circuit, the system adopts a design scheme combining multi-level drive and multi-level acquisition. Among them, the first-level drive circuit is connected to 8 groups of second-level drives through 8 parallel switches, and each group of second-level drives contains 4 drive circuits to directly drive a single-channel sub-ADC. The 8 switches in the first-level drive are turned on in turn at a sampling rate of 10GHz. When one of the switches is turned on, the operating frequency of the 4 switches in the corresponding second-level drive is 1 / 32 of the sampling rate, that is, 2.5GSa / s.

[0061] The chip calibration method includes the following steps:

[0062] S10: Initialize register configuration.

[0063] In the specific implementation process, the initialization configuration can switch the control signal source to the calibration signal frequency, and then initialize the register. The initialization of the register configuration is to adjust its state, which can be performed according to the adjustable range of the register, and adjust each sub-ADC channel register to the middle value state of the adjustable range. That is, the configuration of the initialization register includes:

[0064] According to the adjustable range of the register, the register is adjusted to an intermediate value state of the adjustable range of the register to achieve initialization configuration.

[0065] The adjustable range of the register can be obtained according to the sent value, that is, by sending different bias, gain, and clock offset register values, the adjustable range of the register can be obtained.

[0066] S20: Perform data acquisition based on the calibration instruction to obtain an ADC digital output result.

[0067] In the specific implementation process, data collection is started by issuing and responding to the calibration instruction, and the ADC digital output results are directly collected for subsequent error estimation of the entire link. Further, the collected data can be split at equal intervals to obtain multi-channel ADC data, such as dividing the collected data into 32 channels of ADC data at equal intervals, which are used to time-interleave and splice the multi-channel ADC, that is, according to the ADC digital output results, before calculating the time interleaving error, the method also includes:

[0068] Split the ADC digital output results into equal intervals to obtain multi-channel ADC data;

[0069] Based on the sub-ADC data, calculate the time interleaving error, including:

[0070] Calculate the time interleaving error based on the digital output results of multiple ADCs.

[0071] S30: Calculate a time interleaving error according to the ADC digital output result; wherein the time interleaving error includes an offset error, a gain error or a sampling clock offset between sub-ADC channels.

[0072] In the specific implementation process, the performance requirement after time interleaving and splicing is to keep the time interleaving error small and the waveform smooth in order to achieve chip calibration. The performance loss factors caused by splicing include the offset error, gain error, and sampling clock offset between sub-ADC channels. This is why chip calibration can be achieved by correcting these errors. The calculation of time interleaving error can use an estimation method based on the digital domain Fourier transform (FFT). FFT is an efficient discrete Fourier transform (DFT) algorithm. Its principle is based on discrete Fourier transform (DFT). It improves computing efficiency by reducing the amount of calculation. DFT decomposes a discrete time signal into a linear combination of sine waves and cosine waves of different frequencies. FFT optimizes the calculation process, reducing the computational complexity from O(n^2) to O(n log n), greatly improving the calculation speed.

[0073] S40: According to the time interleaving error, adjust the register value of the sub-ADC channel and obtain the register control code.

[0074] In the specific implementation process, the rapid correction of the relative errors between the sub-ADC channels lies in determining the register adjustment reference, register initialization settings, register control code adjustment steps, and register adjustment loop iteration methods. The register control code adjustment is obtained according to the adjustment of the register value, and the adjustment direction of the offset, gain, and clock offset register values ​​is consistent with the change direction of the time interleaving error. Therefore, the iteration direction of the register value can be determined according to the error, and the iteration step can be gradually reduced. That is: according to the time interleaving error, the register value of the sub-ADC channel is adjusted and the register control code is obtained, including:

[0075] According to the size of the time interleaving error, the direction, iteration direction and iteration step size are changed;

[0076] According to the iteration direction and the iteration step, the register value of the sub-ADC channel is adjusted and the register control code is obtained.

[0077] In one embodiment, before adjusting the register value of the sub-ADC channel and obtaining the register control code according to the time interleaving error, the method further includes:

[0078] According to the adjustable range of the register, determine the register adjustment reference value;

[0079] According to the time interleaving error, the register value of the sub-ADC channel is adjusted and the register control code is obtained, including:

[0080] According to the time interleaving error and the register adjustment reference value, the register value of the sub-ADC channel is adjusted and the register control code is obtained.

[0081] In the specific implementation process, in order to reduce the interleaving error of time interleaving, a reference is set as the basis for adjustment, that is, the register adjustment reference benchmark is set. The benchmark needs to be within the adjustable range of each channel register, and the middle value of the adjustable range of each sub-ADC channel can be selected as the adjustment reference value.

[0082] S50: updating the register according to the register control code, and returning to the step of collecting data based on the calibration instruction to obtain the ADC digital output result, until the iteration termination condition is met and the register target value is obtained.

[0083] S60: According to the register target value, a target register is obtained to implement chip calibration.

[0084] In the specific implementation process, the ADC register control code is continuously updated iteratively, and the updated real-time data is continuously collected in a loop to converge in the desired direction. Finally, after the iteration termination condition is met, the register target value, that is, the optimal solution of the register value, is obtained, and the chip calibration is completed. The iteration termination condition can be that the set number of iterations is reached, the change in the adjustment variance between two adjacent iterations is less than the preset threshold value, etc.

[0085] In this embodiment, the error calculation of the entire link is first performed by directly collecting the digital results of the ADC output, and then optimization iterations are performed in the analog domain according to the calculated time interleaving error, and the corresponding sub-ADC channel register values ​​are adjusted. The registers are updated in the form of register control codes to correct the offset error, gain error, and clock offset between the sub-ADC channels, and finally the chip is calibrated to improve the chip performance.

[0086] See attached Figure 4 , as attached Figure 4 The present application is further described below with reference to the embodiments shown:

[0087] First, initialize the configuration, then issue the SCPI calibration command for data collection. After calculating the time interleaving error, determine whether the iteration termination condition is met. If not, update the ADC register configuration and return to the step of issuing the command to collect the updated real-time data until the judgment result is yes, ending the task of complete calibration.

[0088] Through the real-time feedback link, the ADC collects data in real time and analyzes and calculates the time interleaving error. According to the error, the relevant registers inside the ADC are adjusted to achieve iterative optimization. This can overcome the problem of non-universal analog calibration parameters caused by differences in the process of different ADC chips, and can also be more directly calibrated for ADC performance. Taking 32 sub-channels as an example, the method of the embodiment of the present application interleaves and splices the 32 sub-ADC channels in time, estimates the offset, gain, and clock mismatch errors of each sub-channel in the digital domain, and feeds back the control code to the input drive circuit, the reference voltage generation circuit, and the clock delay adjustment circuit for error correction. The calibration methods for the offset error, gain error, and clock offset are described respectively:

[0089] Regarding the correction of offset error, the offset error between channels comes from the driver offset difference, which can be corrected by determining the reference benchmark and optimizing the iterative register control. Specifically:

[0090] First, obtain the adjustable bias range under no-sampling; in the absence of signal input, the ADC continuously samples the system noise floor, and obtains the adjustable bias range of each sub-ADC by adjusting the bias register configuration of the 32-channel ADC. If the register value related to the offset adjustment of the m-channel ADC has N bits, it can be said that the adjustable range of the register value during the offset adjustment process is [0,2 N -1]. It should be noted that this register adjustment value affects the offset of the m-th ADC and is monotonic, that is, the larger the value, the higher the offset value of the m-th ADC. Due to its monotonicity, first set this parameter to 0 and map it to the corresponding register value, which is sent to the ADC chip through the SCPI instruction. Then collect the original data and split it to get the m-th ADC data. Calculate the average value of the collected data to get the minimum offset value D of the m-th ADC in this mode. min (m). Similarly, set the offset register value to 2 N -1, repeat the above process to get the maximum offset value D of the mth ADC max (m).

[0091] Secondly, the bias register is used to adjust the reference base calculation; the 8-bit ADC quantization range is 0 to 255. Ideally, the reference bias of each channel ADC is 128 when the sampling is empty. However, due to differences in ADC processes, if the adjustable bias range of a certain channel sub-ADC does not include the middle value 128, in order to reduce the interleaving error of time interleaving, a reference value should be selected. This value can be within the adjustable range of each channel. Therefore, the middle value of the adjustable range boundary of each channel ADC can be taken as the reference base. Therefore, the 32-channel ADC bias register is used to adjust the reference base D std Calculate as follows:

[0092]

[0093] Wherein, 1≤m≤32, max[·] represents the maximum value, and min[·] represents the minimum value. The above formula indicates that if the adjustable range of each sub-ADC includes the quantized middle value of the ADC, the quantized middle value of the ADC is used as the reference benchmark, otherwise the middle value of the boundary of the ADC adjustable range is selected as the reference benchmark.

[0094] Then, the registers are initialized and set; the bias circuit registers of each ADC are adjusted to the intermediate value state, and the state at that time is x dc (m)=2 N-1 ,m=1,2,...,32. Collect data and calculate the average bias of each ADC

[0095] Finally, perform binary iterative optimization; assume that the adjustable bits of the ADC bias circuit are N = 6 bits, with a value range of 0 to 63, and set the adjustment step to step = [32, 16, 8, 4, 2, 1] for a total of 5 steps. At the i-th step, update the ADC bias register value x of each channel dc (m), if Then x dc (m) = x dc (m)+step(i), otherwise x dc (m) = x dc (m)-step(i), update the calculated bias mean Repeat this step for iteration 2 i times, and the variance is calculated at each iteration, namely:

[0096]

[0097] Iterate from large to small step size until the end, and select the x corresponding to the result with the smallest variance dc (m) is the optimal solution for the mth sub-ADC channel.

[0098] For gain error correction, the inter-channel gain error comes from the sub-driver gain error and the reference voltage error caused by the wiring voltage drop. This gain error correction is similar to the correction of offset error. Specifically:

[0099] First, obtain the adjustable gain range of the low-frequency signal; input a low-frequency, such as a 100MHz single-tone signal, adjust the gain registers of the 32-channel ADC, and the ADC samples and calculates the adjustable gain range of each sub-ADC. If the register value related to the gain adjustment of the m-th channel ADC has N bits, it can be said that the adjustable range of the register value during the gain adjustment process is [0,2 N -1]. It should be noted that this value affects the sampling gain of the m-th ADC and is monotonic, that is, the larger the value, the higher the sampling gain of the m-th ADC. First, set it to 0 and map it to the corresponding register configuration value, and send it to the ADC through the SCPI instruction. Then, according to the register configuration at this time, collect the original data and split it to get the m-th ADC data, calculate its absolute gain value to get the minimum gain value G of the m-th ADC in this mode. min (m). Similarly, set the gain circuit register to 2 N -1, repeat the above process to get the maximum gain value G of the mth ADC max (m).

[0100] Secondly, the gain standard value is calculated; in the traditional method, the gain error in time interleaving is obtained by selecting a reference channel and comparing the gains of the remaining channels with the reference channel gain. However, since the gain adjustable ranges of the sub-ADCs inside the chip are inconsistent, there may even be a situation where the gain adjustable range of a channel has no intersection with that of another channel. Therefore, the embodiment of the present application defines a gain standard value and uses it to iterate the gains of the 32-channel sub-ADCs. Here, the gain standard value D std Calculated by the following formula:

[0101] G std =(max[G min (m)]+min[G max (m)]) / 2

[0102] Where 1≤m≤32, max[·] represents the maximum value, min[·] represents the minimum value, G min (m) and G max (m) are the maximum and minimum adjustable gain values ​​of each sub-ADC channel.

[0103] Then, the register is initialized and set; the gain circuit register of each ADC is adjusted to the intermediate value state, and the state at that time is x g (m)=2 N-1 ,m=1,2,...,32. Collect data and calculate the mean gain

[0104] Finally, the binary iterative optimization is performed; similar to the bias binary iterative optimization, if the ADC gain circuit can be adjusted from 0 to 63, the adjustment step is set to step = [32, 16, 8, 4, 2, 1] for a total of 5 steps. At the i-th step, update the ADC gain register value x of each channel g (m), if Then x g (m) = x g (m)+step(i), otherwise x g (m) = x g (m)-step(i), update the calculated bias mean Repeat this step for iteration 2 i times, calculating the variance at each iteration:

[0105]

[0106] The step size is iterated from large to small until the end, and each iteration updates the x corresponding to the result with the smallest variance. g (m) is taken as the optimal solution.

[0107] For clock offset correction, the clock offset between channels is mainly caused by the processing errors of each buffer in the clock tree and the routing errors. Unlike offset and gain error correction, changes in the control code of a single-channel clock phase adjustment register will have a certain non-random interference on the clock phases of other channels. To this end, clock offset correction needs to optimize the register configuration through a loop iteration method so that the register values ​​of each channel converge to an acceptable range during the loop. In addition, in order to reduce the difficulty of clock offset adjustment and avoid the influence of ambient temperature on the drift caused by the simultaneous adjustment of the phases of 32 ADC channels, based on the multi-stage drive architecture of this ADC chip, this application will only control and adjust the timing registers of the 8 parallel switches that pass through the first-stage drive. The phase control of the 4 drive switches under a single group of second-stage drives has been automatically configured when the system is powered on. Specifically:

[0108] First, select the clock offset reference channel; adjust the timing register values ​​of the 8 groups of parallel switches to the intermediate value state. Assume that the timing register for adjusting a parallel switch has a total of N bits, and the adjustable range of each group of clock offset registers is [0,2 N -1], then the register values ​​of all 8 groups are set to 2 N-1 . Set the signal source to input a high-frequency signal to the ADC, such as an 18GHz single-tone signal. After the ADC collects data, it is split into 32 sub-ADC data. Taking a certain sub-ADC as the standard, use the FFT-based estimation method to calculate the relative phase error P(m) of the 32 sub-ADCs, where m=1,2,…32. If P(m)<0, it means that the sampling time of the chip ADC lags behind the reference sub-ADC. On the contrary, if P(m)>0, it means that the sampling time of the chip ADC is ahead of the reference sub-ADC. Since there are 8 adjustable timing registers, each group of 4 sub-ADCs is used to obtain the average relative phase error of each group of channels. Next, calculate the variance between the 4 sub-ADCs in each channel:

[0109]

[0110] choose The smallest channel is used as the reference channel. Since changes in the reference ADC will affect the calculation of parameters such as phase error, after determining the reference channel, the phase error needs to be updated, that is, the first sub-ADC in the reference channel is used as the standard to recalculate the ADC's relative phase error P(m) and the average relative phase error of each channel.

[0111] Secondly, the register configuration value of the reference channel is calculated; unlike the offset and gain error calibration, which use the absolute value of the relevant parameters as the reference. In the first step of phase calibration, the reference channel for calculating the phase error is selected, and the timing register value of this channel is not determined. It should be noted that the timing register value of the reference channel affects the phase error of the remaining channels. For example, the register value of the non-reference channel remains at the intermediate value of 2 N-1 The reference channel timing register value is set to 0. At this time, the phase error of the non-reference channel is calculated. Then set the timing register value of the reference channel to 2 N -1, the phase error of the non-reference channel is calculated at this time Due to monotonicity, there must be The purpose of phase calibration is to make the phase error of all channels as close to 0 as possible. Therefore, for the mth channel, if and It means that the mth channel may get an ideal phase calibration effect. Therefore, the present application provides a method to calculate the register configuration value of the reference channel. The method gradually increases the register value of the reference channel. At this time, the register of the non-reference channel is set to its maximum and minimum boundary values. In this case, the relative phase error calculated by sampling is its adjustable range. If there is a zero value in this range, it means that the channel can get an ideal phase calibration effect. It ends when a value that satisfies all non-reference channels to achieve ideal calibration is found.

[0112] Specifically, first set the clock register of the reference channel to 0, in steps of 20, until 2 N -1, repeat the following steps:

[0113] 1. The clock register values ​​of the other non-reference channels are set to 0, the ADC samples data, and the relative phase error of each sub-ADC is calculated using the FFT-based estimation method. This phase error is also the low value of the adjustable range. It represents the lower limit of the adjustable range of the phase error of the mth channel. Due to its monotonicity, if This means that no matter how the clock offset register of channel m is adjusted, it is impossible to find a situation where its relative phase error is 0.

[0114] 2. Then set the clock register value of the remaining non-reference channels to 2 N -1, ADC sampling, using FFT-based estimation method to calculate the relative phase error of each sub-ADC, this phase error is also the high value of the adjustable range It represents the clock adjustment high boundary value of the mth channel. This means that no matter how the clock offset register of channel m is adjusted, it is impossible to find a situation where its relative phase error is 0.

[0115] 3. In the process of gradually increasing the reference register value, if and In theory, all non-reference channels can find an optimal value to satisfy the minimum phase error close to 0. At this time, the current value of the clock register of the reference channel is selected as the standard value x pstd Otherwise, the sum w of the number of channels that do not meet the conditions is counted.

[0116] 4. If all situations have been traversed and the register value of the reference channel that meets the conditions is still not found, the clock register value of the reference channel when the w value is the smallest is selected as the standard value x pstd .

[0117] Then, the registers are initialized and set; based on the reference channel obtained in the first step and the reference channel standard register value x obtained in the second step pstd , adjust the clock register of the sub-ADC of the non-reference channel to the intermediate value state, such as 2 N-1 , the clock register of the reference channel is set to the standard value x pstd If the first group is used as the reference channel, the status at that time is:

[0118]

[0119] Collect data and calculate the relative phase error:

[0120] P(m), m=1,2,…,32

[0121] And the average relative phase error of each group of channels:

[0122]

[0123] And the reference error:

[0124]

[0125] Finally, binary iterative optimization is performed; assume that the adjustable bit of the clock register circuit of each channel ADC is N = 9, the corresponding value range is 0 to 511, and the adjustment step is set to step = [128, 64, 32, 16, 8, 4, 2, 1] for a total of 8 steps. At the i-th step, update the ADC phase register value x of the non-reference channel p (n), if Then x p (n) = x p (n)+step(i), otherwise x p (n) = xp (n)-step(i), sent to ADC and then collected and updated P(m), m = 1,.2,…,32 and Repeat this step for iteration 2 i times, calculating the variance at each iteration:

[0126]

[0127] The step length is iterated from large to small until the end. Since the error calculation in the iterative process is obtained by real-time sampling of the ADC, it will be affected by noise, and the entire process assumes that the timing register adjusts the adjacent channels without mutual influence. However, in actual applications, due to reasons such as the internal circuit of the chip, adjacent channels will have a certain influence when adjusting, so multiple cycles of iteration are required to obtain a relatively stable optimal solution, that is, repeat the above iterative steps many times until the variance change of two adjacent step adjustments is less than the preset threshold value. At this time, the x corresponding to the result p (n) as the optimal solution.

[0128] As a test to verify the method of this application, the experimental equipment is a dual-channel broadband high-speed digital storage oscilloscope built on a time-interleaved sampling architecture, a sampling rate of 80GSa / s, and an ADC direct sampling chip with a bandwidth of 18GHz, and a signal generator that can generate a single-tone sine signal with a frequency range of 20GHz. Figure 5 Schematic diagram of the change of bias error during calibration. Figure 6 The gain error change diagram during the calibration process is shown in Figure 2. Figure 7 This is a schematic diagram of the phase error change during the calibration process. Due to factors such as ADC design, it can be seen that the offset and gain adjustable ranges of different ADC channels are inconsistent, and in the case of the initial intermediate value, the time interleaving error values ​​between each ADC are large. After binary iterative optimization, the time interleaving error of each channel ADC is significantly reduced.

[0129] After the calibration is completed, the signal source output is randomly set to a frequency point, such as a 73MHz single-tone sine signal, and the amplitude is as large as possible to meet the full scale of the ADC. Figure 8 The following is a schematic diagram showing the change of the static index of differential nonlinearity (DNL) of the ADC chip before and after the calibration process. Fig. 9 The figure shows the change of the static indicator of the integral nonlinearity (INL) of the ADC chip before and after the calibration process. Fig.10 The signal waveforms before and after simulation calibration are given when the signal source output is set to a single-tone sine signal of 2 GHz. It can be seen that the bias mean of the calibrated signal is generally in the middle of the sampling range, and the overall waveform is smoother.

[0130] See attached Fig.11 Based on the same inventive concept as in the above-mentioned embodiment, the embodiment of the present application further provides a chip calibration device, comprising:

[0131] Initialization module, the initialization module is used to initialize the configuration of registers;

[0132] The acquisition module is used to collect data based on the calibration instructions to obtain the ADC digital output results;

[0133] A calculation module, the calculation module is used to calculate a time interleaving error according to an ADC digital output result; wherein the time interleaving error includes an offset error, a gain error or a sampling clock offset between sub-ADC channels;

[0134] An adjustment module, the adjustment module is used to adjust the register value of the sub-ADC channel and obtain a register control code according to the time interleaving error;

[0135] Iteration module, which is used to update the register according to the register control code, and return to collect data based on the calibration instruction to obtain the ADC digital output result until the iteration termination condition is met to obtain the register target value;

[0136] The calibration module is used to obtain the target register according to the register target value to realize chip calibration.

[0137] Those skilled in the art should understand that the division of the various modules in the embodiment is only a division of logical functions, and can be fully or partially integrated into one or more actual carriers in actual application, and these modules can be implemented entirely in the form of software called by a processing unit, or entirely in the form of hardware, or in the form of a combination of software and hardware. It should be noted that each module in the chip calibration device in this embodiment corresponds one-to-one to each step in the chip calibration method in the aforementioned embodiment. Therefore, the specific implementation of this embodiment can refer to the aforementioned implementation, which will not be repeated here.

[0138] Based on the same inventive concept as in the aforementioned embodiment, an embodiment of the present application further provides a computer-readable storage medium storing a computer program. When the computer program is loaded and executed by a processor, a chip calibration method as provided in the embodiment of the present application is implemented.

[0139] Based on the same inventive concept as in the above-mentioned embodiment, an embodiment of the present application further provides an electronic device, including a processor and a memory, wherein:

[0140] The memory is used to store computer programs;

[0141] The processor is used to load and execute a computer program so that the electronic device executes the chip calibration method provided in the embodiment of the present application.

[0142] In some embodiments, the computer readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or various devices including one or any combination of the above memories. The computer may be various computing devices including intelligent terminals and servers.

[0143] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0144] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0145] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0146] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or system including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or system. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or system including the element.

[0147] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0148] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as a read-only memory / random access memory, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a multimedia terminal device (which can be a mobile phone, a computer, a television receiver, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0149] In summary, the chip calibration method, device, storage medium and electronic device provided by the present application include: initializing the configuration of the register; collecting data based on the calibration instruction to obtain the ADC digital output result; calculating the time interleaving error according to the ADC digital output result; wherein the time interleaving error includes the offset error, gain error or sampling clock offset between the sub-ADC channels; adjusting the register value of the sub-ADC channel and obtaining the register control code according to the time interleaving error; updating the register according to the register control code, and returning to the step of collecting data based on the calibration instruction to obtain the ADC digital output result until the iteration termination condition is met to obtain the register target value; according to the register target value, obtaining the target register to realize chip calibration. The present application first calculates the error of the entire link by directly collecting the digital results output by the ADC, and then optimizes and iterates in the analog domain according to the calculated time interleaving error, and adjusts the corresponding sub-ADC channel register value, and updates the register in the form of the register control code, so as to correct the offset error, gain error and clock offset between the sub-ADC channels, and finally realizes the calibration of the chip, so that the chip performance is improved.

[0150] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A chip calibration method, characterized in that: The following steps are involved: Initialize register configuration; Perform data acquisition based on the calibration instruction to obtain the ADC digital output result; Calculating a time interleaving error according to the ADC digital output result; wherein the time interleaving error includes an offset error, a gain error or a sampling clock offset between sub-ADC channels; According to the time interleaving error, adjusting the register value of the sub-ADC channel and obtaining a register control code; updating the register according to the register control code, and returning to the step of collecting data based on the calibration instruction and obtaining the ADC digital output result, until the iteration termination condition is met and the register target value is obtained; According to the register target value, a target register is obtained to implement chip calibration.

2. The chip calibration method according to claim 1, characterized in that: The adjusting the register value of the sub-ADC channel and obtaining the register control code according to the time interleaving error includes: According to the change direction of the magnitude of the time interleaving error, the iteration direction and the iteration step size; According to the iteration direction and the iteration step, the register value of the sub-ADC channel is adjusted and a register control code is obtained.

3. The chip calibration method according to claim 1, characterized in that: Before adjusting the register value of the sub-ADC channel and obtaining the register control code according to the time interleaving error, the method further includes: According to the adjustable range of the register, determine the register adjustment reference value; The adjusting the register value of the sub-ADC channel and obtaining the register control code according to the time interleaving error includes: According to the time interleaving error and the register adjustment reference value, the register value of the sub-ADC channel is adjusted and a register control code is obtained.

4. The chip calibration method according to claim 1, characterized in that: The configuration of the initialization register includes: According to the adjustable range of the register, the register is adjusted to an intermediate value state of the adjustable range of the register to achieve initialization configuration.

5. The chip calibration method according to claim 1, characterized in that: Before calculating the time interleaving error according to the ADC digital output result, the method further includes: Splitting the ADC digital output result at equal intervals to obtain multi-channel ADC data; The calculating the time interleaving error according to the sub-ADC data comprises: The time interleaving error is calculated according to the multiple ADC digital output results.

6. The chip calibration method according to claim 1, characterized in that: The step of calculating the time interleaving error according to the ADC digital output result comprises: According to the ADC digital output result, a time interleaving error is calculated by using an estimation method based on digital domain Fourier transform.

7. The chip calibration method according to claim 1, characterized in that: The iteration termination condition includes: the change of the adjustment variance between two adjacent iterations is less than a preset threshold value.

8. A chip calibration device, characterized in that: include: An initialization module, the initialization module is used to initialize the configuration of the register; An acquisition module, wherein the acquisition module is used to acquire data based on the calibration instruction to obtain an ADC digital output result; A calculation module, the calculation module is used to calculate a time interleaving error according to the ADC digital output result; wherein the time interleaving error includes an offset error, a gain error or a sampling clock offset between sub-ADC channels; An adjustment module, the adjustment module is used to adjust the register value of the sub-ADC channel and obtain a register control code according to the time interleaving error; An iteration module, the iteration module is used to update the register according to the register control code, and return to the data acquisition based on the calibration instruction to obtain the ADC digital output result until the iteration termination condition is met to obtain the register target value; A calibration module is used to obtain a target register according to the register target value to implement chip calibration.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is loaded and executed by a processor, the chip calibration method according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: comprising a processor and a memory, wherein: The memory is used to store computer programs; The processor is used to load and execute the computer program so that the electronic device performs the chip calibration method according to any one of claims 1 to 7.

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