Verification method for digital-analog hybrid simulation interface time sequence of ADC controller

Abstract

The invention discloses a method for verifying the time sequence of a digital-analog hybrid simulation interface of an ADC (Analog to Digital Converter) controller, which belongs to the technical field of chip verification, and comprises the following steps of: performing hybrid simulation on a digital circuit and an analog circuit by adopting a VCS + XA simulation tool hybrid simulation mode, instantiating an ADCIF (Analog to Digital Interchange Format) in a module-level verification environment taking a digit as a top layer to capture a key signal of the digital-analog interface, and verifying the time sequence of the digital-analog hybrid simulation interface of the ADC controller. By using an SVA assertion method, verification of a digital-analog interface time sequence is accurately and quickly completed. According to the invention, the problem that the verification is imperfect and insufficient due to the fact that numerous digital-analog interface time sequence problems in the pre-simulation process are not easy to discover because the behavior of a real analog circuit cannot be completely simulated in the prior art is solved. According to the invention, the digital ADC controller can normally generate resetting, sampling starting, conversion starting, conversion ending, channel switching and confirmation of the correctness of a sampling result, and the verification quality and the verification speed are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, in particular to a method for verifying the timing of a digital-analog hybrid simulation interface of an ADC controller. Background Art

[0002] At present, almost all chip fields involve the interaction of digital signals and analog signals, but the verification of digital-analog interfaces is relatively complicated. It is mainly limited to the behavioral-level models used for pre-simulation verification and cannot fully simulate the behavior of real analog circuits, resulting in many digital-analog interface timing problems not being easily discovered during the pre-simulation process, resulting in incomplete and insufficient verification.

[0003] The existing verification technology can no longer meet the current more complex chip digital-analog interface timing, and there is an urgent need to improve the existing verification. Summary of the invention

[0004] The purpose of the present invention is to provide a method for verifying the timing of a digital-analog hybrid simulation interface of an ADC controller, which uses a near-real analog circuit netlist as a simulation preference, fundamentally ensuring the correctness of the analog module circuit, and secondly introduces SVA into a module-level UVM verification environment of digital-analog hybrid simulation, so as to accurately and timely capture the interface timing in a large number of digital-analog tests, thereby completing the digital-analog interface simulation verification more quickly and accurately, and solving the problems raised in the above-mentioned background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions: A method for verifying the timing of a digital-analog hybrid simulation interface of an ADC controller comprises the following steps: Step 1: Prepare the files required for the digital-based module-level verification environment, which include the ADC controller to be verified, the standard AMBA bus agent that drives the internal registers of the ADC controller, the analog IP circuit netlist spice file corresponding to the ADC controller, the analog simulation configuration file, and the analog simulation control file, which are used to drive the analog netlist to generate stimulus; Step 2: According to the prepared files, build the ADC digital-analog hybrid simulation verification module-level environment based on the digital top layer using the UVM verification methodology. The digital design verification uses the VCS digital simulator; it includes the tb top layer, which is used to instantiate the ADC controller and analog circuit, adc_if, which is used to generate system reset, clock and make corresponding connections, and pass ADC_IF to the corresponding agent at the top layer; the env environment includes AMBA agent, adc_sequencer and adc_cfg, scoreboard components, and in the digital environment, it also includes the base class sequence and base class test. The entire UVM verification environment is started through the run_test entry of the tb top layer; Step 3: For analog netlist circuits, enable the analog circuit netlist simulation tool XA to simulate and verify the timing. XA is used in conjunction with the VCS simulator to achieve joint simulation of digital design files and analog design files, so that the analog-to-digital signal timing can be correctly sampled, thereby verifying whether the input of the digital part is correct; for digital circuit netlist simulation of ADC analog IP, provide simulation configuration files, simulation control files, and mutual conversion of digital-analog interface levels, and configuration related to upper and lower threshold voltage simulation; Step 4: Use VCS+XA joint simulation, and timely and accurately capture the key signals of the digital-analog interface in the ADC_IF instantiated at the top level of the verification environment, and generate relevant SVAs about the digital-analog interface in the IF for simulation judgment and verification testing; including reset signal, AD sampling signal, AD conversion start signal, AD conversion end signal, AD conversion channel switching signal, and AD voltage value change signal assertion; Step 5: Through the joint simulation of VCS+XA, digital stimulus and analog stimulus work together to complete the AD digital-to-analog conversion process. At the same time, the ADC_IF assertion SVA switch in the verification environment is turned on as the AD digital-to-analog conversion process is turned on. The digital-to-analog interface timing of each conversion is checked and verified in time to complete the correctness of the digital controller function and the feasibility of the analog circuit.

[0006] Preferably, an ADC digital-analog hybrid simulation verification module-level environment is built based on the digital top layer using UVM verification methodology, including an AMBA bus that drives ADC control, an ADC controller DUT to be tested, and a netlist in the analog ADC IP spice format for hybrid simulation verification; based on the above application of UVM verification methodology to build a verification environment, the DUT and the analog spice netlist are connected through ADC_IF.

[0007] Preferably, in the module-level environment of ADC mixed digital-analog simulation verification built with digital as the top layer, the analog spice netlist includes analog circuit behavior close to the real thing, which correctly generates the timing of the mixed digital-analog interface under the drive of the ADC controller, including reset, sampling, start, end and correct generation of AD conversion voltage data. The mixed digital-analog simulation is a real simulation verification close to the chip level.

[0008] Preferably, the ADC controller is used to correctly drive the analog IP through the interface to achieve voltage conversion of different channels, determine whether the behavior and function of the DUT to be verified are normal through the correct timing of the interface signal, and automatically detect and report unexpected behaviors in the design through assertion verification SVA.

[0009] Preferably, SVA is used in ADC_IF to accurately control and verify the complete timing of the digital-to-analog interface.

[0010] Preferably, the ADC controller is connected to the analog IPspice netlist through ADC_IF in a digital-based module-level verification environment and correctly performs the digital-to-analog interface AD ​​conversion process, including: As described above, the ADC controller correctly configures analog reset and generates clock; As described above, the ADC controller correctly configures the analog trigger to sample the selected channel AD; As described above, the ADC controller is correctly configured to simulate triggering the AD conversion of the selected channel; As described above, the ADC controller is correctly configured to simulate the switching of different channels; As described above, the ADC analog IP correctly returns the voltage value converted by the current channel.

[0011] Preferably, in a module-level verification environment, key signals of the digital-to-analog interface are captured in ADC_IF, and assertions are written to monitor and verify the digital-to-analog circuit interface timing of each normal AD conversion.

[0012] Preferably, the generated assertion includes constantly monitoring whether the reset signal of the spice netlist analog circuit is stable, whether the timing of starting sampling is normal, whether the timing of conversion start and conversion end is normal, whether the AD conversion voltage value generated by the analog circuit is stable, and whether the channel switching position of the digital controller remains stable.

[0013] Preferably, in a digital-to-analog interface module-level verification environment based on the digital top layer, the AD digital-to-analog voltage conversion test is repeated multiple times, and the digital-to-analog interface timing in all conversion processes is checked and verified by default through the assertions generated in ADC_IF.

[0014] Compared with the prior art, the present invention has the following beneficial effects: The present invention adopts a hybrid simulation mode of two simulation tools VCS+XA to perform hybrid simulation on digital circuits and analog circuits, and instantiates ADC_IF in a module-level verification environment with digital as the top layer to capture key signals of the digital-to-analog interface, and uses the SVA assertion method to accurately and quickly complete the verification of the digital-to-analog interface timing, ensuring that the digital ADC controller can normally generate reset, start sampling, start conversion, end conversion, channel switch, and confirm the correctness of the sampling result, thereby improving the quality and speed of verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a flow chart of the digital-analog hybrid simulation interface timing verification method of the ADC controller of the present invention; Figure 2 It is a schematic diagram of a module-level verification environment with numbers as the top layer of the present invention; Figure 3 The present invention is a flow chart of the algorithm for timing verification of the digital-analog hybrid simulation interface. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] In order to solve the problem that the existing digital-analog interface verification work is relatively complicated, it is mainly limited to the behavioral level model used for pre-simulation verification and cannot fully simulate the behavior of the real analog circuit, resulting in many digital-analog interface timing problems not being easily discovered during the pre-simulation process, which leads to imperfect and insufficient verification and cannot meet the current more complex chip digital-analog interface timing verification problems. Please refer to Figure 1-Figure 3 , this embodiment provides the following technical solutions: A method for verifying the timing of a digital-analog hybrid simulation interface of an ADC controller comprises the following steps: Step 1: Prepare the files required for the digital-based module-level verification environment, which include the ADC controller to be verified, the standard AMBA bus agent that drives the internal registers of the ADC controller, the analog IP circuit netlist spice file corresponding to the ADC controller, the analog simulation configuration file, and the analog simulation control file, which are used to drive the analog netlist to generate stimulus; Step 2: According to the prepared files, build the ADC digital-analog hybrid simulation verification module-level environment based on the digital top layer using the UVM verification methodology. The digital design verification uses the VCS digital simulator; it includes the tb top layer, which is used to instantiate the ADC controller and analog circuit, adc_if, which is used to generate system reset, clock and make corresponding connections, and pass ADC_IF to the corresponding agent at the top layer; the env environment includes AMBA agent, adc_sequencer and adc_cfg, scoreboard components, and in the digital environment, it also includes the base class sequence and base class test. The entire UVM verification environment is started through the run_test entry of the tb top layer; In this embodiment, the UVM verification methodology is used to build an ADC digital-analog hybrid simulation verification module-level environment based on the digital top layer, including an AMBA bus that drives the ADC control, an ADC controller DUT to be tested, and a netlist in the analog ADC IP spice format for hybrid simulation verification; based on the above application of the UVM verification methodology to build a verification environment, the DUT and the analog spice netlist are connected through ADC_IF.

[0018] In this embodiment, in the module-level environment of ADC digital-analog hybrid simulation verification built with digital as the top layer, the analog spice netlist includes analog circuit behaviors close to the real ones, which correctly generates the timing of the digital-analog hybrid interface under the drive of the ADC controller, including reset, sampling, start, end and correct generation of AD conversion voltage data. The digital-analog hybrid simulation is a real simulation verification close to the chip level.

[0019] Step 3: For analog netlist circuits, enable the analog circuit netlist simulation tool XA to simulate and verify the timing. XA is used in conjunction with the VCS simulator to achieve joint simulation of digital design files and analog design files, so that the analog-to-digital signal timing can be correctly sampled, thereby verifying whether the input of the digital part is correct; for digital circuit netlist simulation of ADC analog IP, provide simulation configuration files, simulation control files, and mutual conversion of digital-analog interface levels, and configuration related to upper and lower threshold voltage simulation; Step 4: Use VCS+XA joint simulation, and timely and accurately capture the key signals of the digital-analog interface in the ADC_IF instantiated at the top level of the verification environment, and generate relevant SVAs about the digital-analog interface in the IF for simulation judgment and verification testing; including reset signal, AD sampling signal, AD conversion start signal, AD conversion end signal, AD conversion channel switching signal, and AD voltage value change signal assertion; In this embodiment, the ADC controller is used to correctly drive the analog IP through the interface to realize the voltage conversion of different channels, and determine whether the behavior and function of the DUT to be verified are normal through the correct timing of the interface signal. The assertion verification SVA automatically detects and reports the unexpected behavior in the design. The observability and controllability of the verified chip are improved by embedding the checkpoints in the design. SVA is used in ADC_IF to accurately control and verify the complete timing of the digital-to-analog interface.

[0020] Step 5: Through the joint simulation of VCS+XA, digital stimulus and analog stimulus work together to complete the AD digital-to-analog conversion process. At the same time, the ADC_IF assertion SVA switch in the verification environment is turned on as the AD digital-to-analog conversion process is turned on. The digital-to-analog interface timing of each conversion is checked and verified in time to complete the correctness of the digital controller function and the feasibility of the analog circuit.

[0021] In this embodiment, the ADC controller is connected to the analog IP spice netlist through ADC_IF in a digital-based module-level verification environment and correctly performs the digital-to-analog interface AD ​​conversion process, including: As described above, the ADC controller correctly configures analog reset and generates clock; As described above, the ADC controller correctly configures the analog trigger to sample the selected channel AD; As described above, the ADC controller is correctly configured to simulate triggering the AD conversion of the selected channel; As described above, the ADC controller is correctly configured to simulate the switching of different channels; As described above, the ADC analog IP correctly returns the voltage value converted by the current channel.

[0022] In this embodiment, in a module-level verification environment, key signals of the digital-to-analog interface are captured in ADC_IF, and assertions are written to monitor and verify the digital-to-analog circuit interface timing of each normal AD conversion.

[0023] In this embodiment, the generated assertions include constantly monitoring whether the reset signal of the spice netlist analog circuit is stable, whether the timing of starting sampling is normal, whether the timing of conversion start and conversion end is normal, whether the AD conversion voltage value generated by the analog circuit is stable, and whether the channel switching position of the digital controller remains stable.

[0024] In this embodiment, in a digital-to-analog interface module-level verification environment based on the digital top layer, the AD digital-to-analog voltage conversion test is repeated multiple times, and the digital-to-analog interface timing in all conversion processes is checked and verified by default through the assertions generated in ADC_IF.

[0025] Therefore, the present invention adopts a hybrid simulation mode of VCS+XA two simulation tools to perform hybrid simulation on digital circuits and analog circuits, and instantiates ADC_IF in a module-level verification environment with digital as the top layer to capture key signals of the digital-to-analog interface, and uses the SVA assertion method to accurately and quickly complete the verification of the digital-to-analog interface timing, ensuring that the digital ADC controller can normally generate reset, start sampling, start conversion, end conversion, channel switch and confirm the correctness of the sampling result, thereby improving the quality and speed of verification.

[0026] In this embodiment, it can be seen that this verification method is based on a digital-analog hybrid simulation verification module-level platform with digital as the top layer, including: building a verification platform, capturing interface signals, generating SVA assertions, and timing verification of AD digital-analog interfaces, etc.; In this example, the signal types of the digital-to-analog interface can be divided into two categories: configuration interface signals, such as analog reset signals, the verification mainly considers whether the path from the digital circuit to the analog circuit is normal; in addition, there are control interface signals, such as sampling start signals, the verification mainly considers whether the digital to analog drive input and the load output of the analog module are normal.

[0027] First, obtain the analog circuit spice format netlist file (adc.spice) of the analog module ADC IP verified this time, as well as the analog simulation configuration file and analog simulation control file. Such files are generally provided by the analog engineer responsible for the module. The ports in the adc.spice file correspond to the ports of the digital controller, including configuration interfaces and control interfaces such as RST, CLK, SOC, EOC, CH[3:0], and D[11:0]. Secondly, the analog simulation configuration file includes the analog simulation accuracy (set_sim_level), whether the netlist file format is case-sensitive (set_sim_case), the level of the dump voltage, etc. The simulation control file includes the direction definition of the port signal, the voltage threshold definition of A2D and D2A, and the definition of the simulation file generation and storage path.

[0028] Secondly, prepare the digital top-level file tb, which mainly instantiates and connects the digital controller and analog ADC IP circuit netlist files, and also includes generating the system reset sys_rst and the system clock sys_clk; in addition, tb focuses on instantiating the digital interface ADC_IF to capture the key signals of the digital-to-analog interface during the AD digital-to-analog interface conversion process.

[0029] According to the digital-analog interface signal obtained in ADC_IF, SVA consistent with the Spec requirements is generated to check and verify the AD conversion process; For example, in the digital-to-analog interface, the sampling start signal SOC and the conversion end signal EOC have a timing relationship specified by the Spec. Taking the 12-bit ADC as an example, the generated assertions are as follows: property SOC_EOC; @(posedge sys_clk) $rose SOC |=> ##12 $rose EOC; endproperty assert property(SOC_EOC) else `uvm_error("ASSERT","SOC_EOC CHECKERROR") Among them, assert is the assertion keyword, and property is the type of the assertion; so the above generates a property type assertion. In addition, ADC_IF also includes assertions for data changes and controls such as RST, CH[3:0], and D[3:0].

[0030] According to the timing signal of the digital-analog port, the timing requirements of the Spec are expected. If all assertion checks based on the port timing check are completed and the preliminary test is passed, the analog mixed AD interface simulation can be performed. If there is an incomplete timing, continue to return to the previous step to finally achieve a complete check of the interface signal.

[0031] It should be noted that the verification method of the digital-analog interface SVA specifically includes: The analog netlist and configuration files related to analog are provided by analog engineers, and are configured to generate analog stimulus signals consistent with digital stimulus, such as analog power supply voltage VDD, analog power ground VSS, analog input channel voltage value AIN [x] = xV, analog reference voltage VREF, and a series of analog related configurations. The digital controller to be tested and the digital verification top layer are completed by digital engineers. The UVM language is used to build a UVM module-level verification environment based on the digital top layer. The digital controller and the analog circuit netlist are instantiated and connected based on the digital top layer tb. At the same time, ADC_IF is instantiated and passed to adc_env. adc_env obtains the handle of ADC_IF through uvm_get for verification and judgment; in ADC_IF, the SVA assertion for judging the interface timing is generated according to the real timing of the digital-to-analog interface.

[0032] In this implementation example, the entry run_test() function started by the uvm environment reserved by the tb top-level environment is used to perform the digital-analog mixed simulation AD voltage conversion test, wherein the sequence of digital excitation is executed by mounting on the sequencer; this includes: In this implementation example, the digital stimulus can correctly send out the RST signal required for AD testing; In this implementation example, the digital stimulus can correctly send out the CLK signal required for AD testing; In this implementation example, the digital stimulus can correctly send out the sampling-on SOC signal required for AD testing; In this implementation example, the analog stimulus can correctly send out the sampling end EOC signal required for AD testing; In this implementation example, the digital stimulus can correctly send the CH[3:0] signal for channel switching required for AD testing; In this implementation example, the analog stimulus can correctly send out the D[11:0] signal of the voltage conversion value of the current channel required for the AD test; After executing the corresponding test, both the digital stimulus and the analog stimulus are successfully sent. At this time, the digital-to-analog interface will perform the corresponding AD voltage value conversion, and the assertion in ADC_IF will always check whether the interface signal meets the Spec; if it is found that some functions are not tested, continue to return to the previous step to generate assertions until all signals of the digital-to-analog interface are fully tested, and the verification is completed.

[0033] Therefore, the present invention adopts a hybrid simulation mode of VCS+XA two simulation tools to perform hybrid simulation on digital circuits and analog circuits, and instantiates ADC_IF in a module-level verification environment with digital as the top layer to capture key signals of the digital-to-analog interface, and uses the SVA assertion method to accurately and quickly complete the verification of the digital-to-analog interface timing, ensuring that the digital ADC controller can normally generate reset, start sampling, start conversion, end conversion, channel switch and confirm the correctness of the sampling result, thereby improving the quality and speed of verification.

[0034] Compared with traditional pre-simulation testing, behavioral models are often used for interface timing of analog modules, but the quality of the models varies greatly, resulting in frequent false verification passes, and the actual bugs have not been discovered. This method uses the real circuit of the netlist provided by the simulation to replace the analog behavioral model, which will be closer to the actual situation than pre-simulation verification and make the verification more accurate; using the interface timing SVA verification methodology in the module-level verification environment will make the complex and abstract digital-analog interface timing more concrete, and complete the timing test verification more clearly and concisely. Compared with traditional verification methodology, using UVM verification methodology to build a verification environment will be more flexible and make the testing methods more diverse.

[0035] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0036] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for verifying the timing of a digital-analog hybrid simulation interface of an ADC controller, characterized in that: The steps include: Step 1: Prepare the files required for the digital-based module-level verification environment, which include the ADC controller to be verified, the standard AMBA bus agent that drives the internal registers of the ADC controller, the analog IP circuit netlist spice file corresponding to the ADC controller, the analog simulation configuration file, and the analog simulation control file, which are used to drive the analog netlist to generate stimulus; Step 2: According to the prepared files, build the ADC digital-analog hybrid simulation verification module-level environment based on the digital top layer using the UVM verification methodology. The digital design verification uses the VCS digital simulator; it includes the tb top layer, which is used to instantiate the ADC controller and analog circuit, adc_if, which is used to generate system reset, clock and make corresponding connections, and pass ADC_IF to the corresponding agent at the top layer; the env environment includes AMBA agent, adc_sequencer and adc_cfg, scoreboard components, and in the digital environment, it also includes the base class sequence and base class test. The entire UVM verification environment is started through the run_test entry of the tb top layer; Step 3: For analog netlist circuits, enable the analog circuit netlist simulation tool XA to simulate and verify the timing. XA is used in conjunction with the VCS simulator to achieve joint simulation of digital design files and analog design files, so that the analog-to-digital signal timing can be correctly sampled and verify whether the input of the digital part is correct; for digital circuit netlist simulation of ADC analog IP, provide simulation configuration files, simulation control files, and mutual conversion of digital-analog interface levels, and upper and lower threshold voltage simulation configuration; Step 4: Use VCS+XA joint simulation, and timely and accurately capture the key signals of the digital-analog interface in the ADC_IF instantiated at the top level of the verification environment, and generate relevant SVAs about the digital-analog interface in the IF for simulation judgment and verification testing; including reset signal, AD sampling signal, AD conversion start signal, AD conversion end signal, AD conversion channel switching signal, and AD voltage value change signal assertion; Step 5: Through the joint simulation of VCS+XA, digital stimulus and analog stimulus work together to complete the AD digital-to-analog conversion process. At the same time, the ADC_IF assertion SVA switch in the verification environment is turned on following the AD digital-to-analog conversion process. The digital-to-analog interface timing of each conversion is checked and verified.

2. The method for verifying the timing of a digital-analog hybrid simulation interface of an ADC controller as claimed in claim 1, characterized in that: Based on the digital top layer, the UVM verification methodology is used to build the ADC digital-analog hybrid simulation verification module-level environment, including the AMBA bus that drives the ADC control, the ADC controller DUT to be tested, and the analog ADC IP spice format netlist for hybrid simulation verification; the UVM verification methodology is used to build the verification environment, and the DUT and the analog spice netlist are connected through ADC_IF.

3. The method for verifying the timing of the digital-analog hybrid simulation interface of an ADC controller as claimed in claim 2, characterized in that: In the module-level environment of ADC mixed-analog simulation verification built with digital as the top layer, the analog spice netlist includes close-to-real analog circuit behavior, and generates the timing of the mixed-analog interface under the drive of the ADC controller, including reset, sampling, start, end and correct generation of AD conversion voltage data.

4. The method for verifying the timing of the digital-analog hybrid simulation interface of an ADC controller as claimed in claim 3, characterized in that: The ADC controller is used to correctly drive the analog IP through the interface to achieve voltage conversion of different channels. The correct timing of the interface signal is used to determine whether the behavior and function of the DUT to be verified are normal. The assertion verification SVA automatically detects and reports unexpected behaviors in the design.

5. The method for verifying the timing of the digital-analog hybrid simulation interface of an ADC controller as claimed in claim 4, characterized in that: SVA is used in ADC_IF to accurately control and verify the complete timing of the digital-to-analog interface.

6. The method for verifying the timing of the digital-analog hybrid simulation interface of an ADC controller as claimed in claim 5, characterized in that: The ADC controller is connected to the analog IP spice netlist through ADC_IF in a digital-based top-level module-level verification environment and correctly performs the digital-to-analog interface AD ​​conversion process, including: The ADC controller correctly configures analog reset and generates clock; The ADC controller correctly configures the analog trigger to sample the selected channel AD; The ADC controller correctly configures the analog trigger to convert the selected channel AD; Correct configuration of the ADC controller to simulate the triggering of the switching of different channels; The ADC analog IP correctly returns the voltage value converted by the current channel.

7. The method for verifying the timing of the digital-analog hybrid simulation interface of an ADC controller as claimed in claim 6, characterized in that: In the module-level verification environment, capture the key signals of the digital-to-analog interface in ADC_IF, and write assertions to monitor and verify the digital-to-analog circuit interface timing for each normal AD conversion.

8. The method for verifying the timing of the digital-analog hybrid simulation interface of an ADC controller as claimed in claim 7, characterized in that: The generated assertions include constantly monitoring whether the reset signal of the spice netlist analog circuit is stable, whether the timing of starting sampling is normal, whether the timing of conversion start and conversion end is normal, whether the AD conversion voltage value generated by the analog circuit is stable, and whether the channel switching position of the digital controller remains stable.

9. The method for verifying the timing of the digital-analog hybrid simulation interface of an ADC controller as claimed in claim 8, characterized in that: In the digital-based top-level digital-to-analog interface module-level verification environment, the AD digital-to-analog voltage conversion test is repeated many times, and the digital-to-analog interface timing in all conversion processes is checked and verified by default through the assertions generated in ADC_IF.

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