Storage block layout structure and memory

Abstract

The invention relates to the field of semiconductor structure design, in particular to a memory block layout structure and a memory, and the memory block layout structure comprises a plurality of memory array layout structures which are arranged in a first direction and are continuously arranged in a second direction to form the memory block layout structure; wherein each storage array layout structure is used for forming a storage array in the storage block, and the first direction is perpendicular to the second direction; the memory array layout structure is configured as a parallelogram region arranged based on a third direction and a fourth direction; the included angle alpha between the second direction and the fourth direction is smaller than 90 degrees, and the included angle beta between the third direction and the fourth direction is larger than 0 and smaller than 90 degrees. A plurality of word lines and a plurality of bit lines are arranged in each storage array layout structure, one of the plurality of word lines and the plurality of bit lines is arranged at intervals in the third direction and extends in the fourth direction, and the other one of the plurality of word lines and the plurality of bit lines is arranged at intervals in the fourth direction and extends in the third direction.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor structure design, and in particular to a storage block layout structure and a memory. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory. Its main working principle is to use the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0.

[0003] refer to Figure 1 In the 4F2 layout DRAM, the word line (WL) and the bit line (BL) are arranged vertically, and the intersection of the word line WL and the bit line BL is used to set the cell capacitor (Cell Cap). The cell capacitor couples the word line WL and the bit line BL at the intersection. Therefore, it can be seen that in order to adapt to the arrangement of the word line WL and the bit line BL, the arrangement of the cell capacitor adopts square stacking. Summary of the invention

[0004] The embodiments of the present disclosure provide a storage block layout structure and a memory to increase the storage capacity of DRAM under the same area.

[0005] An embodiment of the present disclosure provides a storage block layout structure for forming a storage block in a memory, comprising: a plurality of storage array layout structures, wherein the plurality of storage array layout structures are arranged in a first direction and are continuously arranged in a second direction to form a storage block layout structure; wherein each storage array layout structure is used to form a storage array in the storage block, and the first direction and the second direction are perpendicular to each other; the storage array layout structure is configured as a parallelogram area arranged based on a third direction and a fourth direction; wherein an angle α between the second direction and the fourth direction is less than 90°, and an angle 0 between the third direction and the fourth direction is less than β is less than 90°; a plurality of word lines and a plurality of bit lines are arranged in each storage array layout structure, wherein one of the plurality of word lines and the plurality of bit lines is arranged at intervals in the third direction and extends in the fourth direction, and the other is arranged at intervals in the fourth direction and extends in the third direction.

[0006] In the storage block layout structure provided in this embodiment, a new arrangement of word lines WL and bit lines BL is provided, so that the arrangement of unit capacitors is honeycomb-shaped, thereby achieving high-density stacking of unit capacitors and improving the storage capacity of DRAM under the same area.

[0007] Optionally, a plurality of storage array layout structures are arranged in the first direction to form a storage block layout structure, including: the plurality of storage array layout structures arranged in the first direction have the same position in the second direction.

[0008] Optionally, between every two storage array layout structures arranged in the first direction, there are also: multiple supplementary word line structures; each supplementary word line structure is configured to connect a word line in the storage array layout structures on both sides and couple to the word line driver of the memory through a conductive node; wherein the conductive node is arranged on the supplementary word line structure.

[0009] Optionally, the supplementary word line structure is configured to connect word lines with the same position relationship in the storage array layout structures on both sides.

[0010] Optionally, a plurality of storage array layout structures are arranged in the first direction to form a storage block layout structure, including: N storage array layout structures arranged in the first direction and continuously arranged in the third direction, N≥2.

[0011] Optionally, the memory array layout structures continuously arranged in the third direction share a word line, and the word line is coupled to a word line driver of the memory through a conductive node; wherein the conductive node is arranged on the word line at an edge position of any memory array layout structure.

[0012] Optionally, N storage array layout structures are arranged in the first direction and are continuously arranged in the third direction, including: two storage array layout structures continuously arranged in the third direction constitute a storage array layout structure group; the storage array layout structure group is arranged in the first direction and is continuously arranged in the second direction to constitute a storage block layout structure, and the multiple storage array layout structure groups arranged in the first direction have the same position in the second direction.

[0013] Optionally, two memory array layout structures in the memory array layout structure group share a word line, and the word line is coupled to a word line driver of the memory through a conductive node; wherein the conductive node is arranged on the word line between the two memory array layout structures.

[0014] Optionally, all storage array layout structures arranged in the first direction are arranged continuously in the third direction.

[0015] Optionally, each storage array layout structure includes a plurality of unit capacitor layout structures, and the plurality of unit capacitor layout structures are continuously arranged in the third direction and the fourth direction.

[0016] Optionally, an angle α between the second direction and the fourth direction is 0.

[0017] Optionally, the angle β between the third direction and the fourth direction is 60°.

[0018] Another embodiment of the present disclosure further provides a memory, in which each memory block of the memory is arranged based on the memory block layout structure provided in the above embodiment to increase the storage capacity of DRAM under the same area. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A method of arranging the square-stacked cell capacitors, word lines, and bit lines in a DRAM;

[0021] Figure 2 Another method of arranging cell capacitors in a honeycomb pattern in a DRAM, and also a method of arranging word lines and bit lines;

[0022] Figure 3 A schematic diagram of a memory layout structure provided in an embodiment of the present disclosure;

[0023] Figure 4 A schematic diagram of a storage array layout structure in a storage block layout structure provided in an embodiment of the present disclosure;

[0024] Figure 5 A schematic diagram illustrating "arrangement" and "continuous arrangement" provided for an embodiment of the present disclosure;

[0025] Figure 6 A schematic diagram of a storage array layout structure in another storage block layout structure provided in an embodiment of the present disclosure;

[0026] Figure 7 A schematic diagram of a layout structure of a first storage block layout structure provided in an embodiment of the present disclosure;

[0027] Figure 8 An embodiment of the present disclosure provides Figure 7 A schematic diagram of the conductive node arrangement of the word line and the word line driver in the structure shown;

[0028] Fig. 9 A schematic diagram of a layout structure of a second storage block layout structure provided in an embodiment of the present disclosure;

[0029] Fig.10 An embodiment of the present disclosure provides Fig. 9 A schematic diagram of the conductive node arrangement of the word line and the word line driver in the structure shown;

[0030] Fig.11 A schematic diagram of a layout structure of a third storage block layout structure provided in an embodiment of the present disclosure;

[0031] Fig.12 An embodiment of the present disclosure provides Fig.11 A schematic diagram of the conductive node arrangement of the word line and the word line driver in the structure shown;

[0032] Fig.13 A schematic diagram of a layout structure of a fourth storage block layout structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] As can be seen from the background technology, in a 4F2 layout DRAM, word lines (Word Line, WL) and bit lines (Bit Line, BL) are arranged vertically, and the intersection of the word line WL and the bit line BL is used to set a cell capacitor (Cell Cap). The cell capacitor couples the word line WL and the bit line BL at the intersection. It can be seen that in order to adapt to the arrangement of the word line WL and the bit line BL, the arrangement of the cell capacitor adopts square stacking.

[0034] At present, with the advancement of technology, the requirements for DRAM storage capacity are getting higher and higher, that is, the number of unit capacitors integrated in DRAM increases, while the use of square-stacked unit capacitors has a low utilization rate for the limited layout structure area of ​​the memory, which to some extent affects the improvement of DRAM storage capacity.

[0035] Compared with square stacking, honeycomb arrangement has a higher utilization rate of space. In one example, reference Figure 2 By adjusting the angle between the word line WL and the bit line BL, the arrangement of the cell capacitors is adjusted to a honeycomb arrangement without changing the cell capacitor layout structure. The cell capacitors arranged in a honeycomb arrangement have a greater utilization rate for the limited layout structure area of ​​the memory. By increasing the stacking density, the number of cell capacitors set in a limited area is increased, and the storage capacity of the DRAM is increased to a certain extent; however, the reference Figure 2 It can be found that the lengths of word lines WL and bit lines BL corresponding to different unit capacitors are different, resulting in certain electrical performance differences between word lines WL and bit lines BL in the memory, which increases the difficulty of subsequent design of word line WL and bit line BL driving in the memory.

[0036] Based on this technical problem, an embodiment of the present disclosure provides a storage block layout structure for forming a storage block in a memory to increase the storage capacity of DRAM under the same area.

[0037] It can be understood by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments can be combined with each other and referenced to each other without contradiction.

[0038] Figure 3 A schematic diagram of the layout structure of the memory provided in this embodiment, Figure 4 A schematic diagram of a storage array layout structure in a storage block layout structure provided in this embodiment, Figure 5 The schematic diagram for explaining the "arrangement" and "continuous arrangement" provided in this embodiment, Figure 6 A schematic diagram of a storage array layout structure in another storage block layout structure provided in this embodiment, Figure 7 A schematic diagram of the layout structure of the first storage block layout structure provided in this embodiment, Figure 8 The embodiment provided Figure 7 A schematic diagram of the conductive node arrangement of the word line and the word line driver in the structure shown, Fig. 9 A schematic diagram of a layout structure of a second storage block layout structure provided in this embodiment, Fig.10 The embodiment provided Fig. 9 A schematic diagram of the conductive node arrangement of the word line and the word line driver in the structure shown, Fig.11 A schematic diagram of a layout structure of a third storage block layout structure provided in this embodiment, Fig.12 The embodiment provided Fig.11 A schematic diagram of the conductive node arrangement of the word line and the word line driver in the structure shown, Fig.13 This is a schematic diagram of a layout structure of a fourth storage block layout structure provided in this embodiment. The storage block layout structure provided in this embodiment is described in detail below in conjunction with the accompanying drawings, as follows:

[0039] It should be noted that the present disclosure mentions a memory, a storage block, and a storage array. The relationship between the memory, the storage block, and the storage array is described as follows: In an example, for the same memory, the memory includes multiple storage blocks. Figure 3 , multiple storage blocks are arranged in two rows on opposite sides of the memory, and the remaining area after the storage blocks are arranged (the area between the two rows of storage blocks and the outer area of ​​the storage blocks) is used as the peripheral circuit area of ​​the memory; for the same storage block, the storage block includes multiple storage arrays arranged in an array, and each storage array is composed of multiple word lines and multiple bit lines; in addition, it should be noted that, Figure 3The example structure is only used by those skilled in the art to understand the inclusion relationship among the memory, storage block and storage array mentioned in the present disclosure, and does not constitute a specific position limitation.

[0040] refer to Figure 4 The storage block layout structure 100 provided in this embodiment is used to form a storage block in a memory, including:

[0041] A plurality of storage array layout structures 200 are arranged in a first direction X0 and are continuously arranged in a second direction Y0 to form a storage block layout structure 100; wherein each storage array layout structure 200 is used to form a storage array in a storage block, and the first direction X0 and the second direction Y0 are perpendicular to each other.

[0042] The storage array layout structure 200 is configured as a parallelogram area set based on the third direction X1 and the fourth direction Y1; wherein the angle α between the second direction Y0 and the fourth direction Y1 is less than 90°, and the angle 0 between the third direction X1 and the fourth direction Y1 is less than 90°.

[0043] Each memory array layout structure 200 is provided with a plurality of word lines WL and a plurality of bit lines BL. Among the plurality of word lines WL and the plurality of bit lines BL, one is arranged at intervals in the third direction X1 and extends in the fourth direction Y1, and the other is arranged at intervals in the fourth direction Y1 and extends in the third direction X1.

[0044] It should be noted that the above and subsequent descriptions of the storage block layout structure 100 include two layouts, namely, “arrangement” and “continuous arrangement”. Figure 4 For the storage array layout structure 200 in the parallelogram area, the storage array layout structure 200 in the parallelogram area includes two groups of parallel edges, and the two groups of parallel edges are respectively the A edge and the B edge set parallel to the third direction X1, and the C edge and the D edge set parallel to the fourth direction Y1.

[0045] For the layout mode of “arrangement”, “arrangement” refers to setting a plurality of storage array layout structures in corresponding directions, and there is no specific position limitation between the plurality of storage array layout structures.

[0046] In one example, refer to Figure 5 The storage array layout structure 200 set in the third direction X1 includes Z1, Z2 and Z4. Since there is no specific position requirement, it can be said that Z1, Z2 and Z4 are "arranged" in the third direction X1; the storage array layout structure 200 set in the fourth direction Y1 includes Z1, Z3 and Z5. Since there is no specific position requirement, it can be said that Z1, Z3 and Z5 are "arranged" in the fourth direction Y1.

[0047] For the layout mode of “continuous arrangement”, “continuous arrangement” means that a plurality of storage array layout structures are arranged in corresponding directions, and the edges of the plurality of storage array layout structures in non-corresponding directions are aligned with each other.

[0048] In one example, refer to Figure 5 The storage array layout structure 200 arranged in the third direction X1 includes Z1, Z2 and Z4. The "continuous arrangement" needs to ensure that the edges in the non-parallel direction (non-third direction X1) are aligned with each other. The D edge of the storage array layout structure Z2 is aligned with the C edge of the storage array layout structure Z1, that is, the storage array layout structures Z1 and Z2 are in a "continuous arrangement" relationship. The D edge of the storage array layout structure Z1 and the C edge of the storage array layout structure Z4 are not aligned, that is, the storage array layout structures Z1 and Z4 are only in an "arrangement" relationship, and do not satisfy the "continuous arrangement" relationship. The storage array layout structure 200 arranged in the fourth direction Y1 includes Z1, Z3 and Z5. The "continuous arrangement" needs to ensure that the edges in the non-parallel direction (non-fourth direction Y1) are aligned with each other. The B edge of the storage array layout structure Z1 is aligned with the A edge of the storage array layout structure Z3, that is, the storage array layout structures Z1 and Z3 are in a "continuous arrangement" relationship, and the B edge of the storage array layout structure Z5 is not aligned with the A edge of the storage array layout structure Z1, that is, the storage array layout structures Z1 and Z5 are only in an "arrangement" relationship, which does not satisfy the "continuous arrangement" relationship.

[0049] For the storage block layout structure 100 provided in this embodiment, a new arrangement of word lines WL and bit lines BL is provided, and the angle between the word lines WL and the bit lines BL is an acute angle. In addition, the arrangement of unit capacitors coupled to the word lines WL and the bit lines BL is adjusted from a square arrangement to a honeycomb arrangement. The honeycomb arrangement has a higher stacking density than the square arrangement, thereby achieving high-density stacking of unit capacitors, increasing the number of unit capacitors of DRAM under the same area, that is, increasing the storage capacity of DRAM under the same area.

[0050] Continue to refer Figure 4 In the storage array layout structure 200 provided in this embodiment, each storage array layout structure 200 includes a plurality of unit capacitor layout structures 20, and the plurality of unit capacitor layout structures 20 are continuously arranged in the third direction X1 and the fourth direction Y1, so as to form a storage array layout structure 200 in a parallelogram area, wherein the unit capacitor layout structure 20 is used to form a unit capacitor in the storage array, and the unit capacitor layout structure is configured as a parallelogram area arranged based on the third direction X1 and the fourth direction Y1, wherein the lengths of the unit capacitor layout structures arranged in the third direction X1 and the fourth direction Y1 are equal.

[0051] The unit capacitor layout structure 20 is set to a parallelogram area parallel to the word line WL and the bit line BL to match the parallelogram area of ​​the constructed storage array layout structure 200; in addition, the lengths of the unit capacitor layout structure 20 in the third direction X1 and the fourth direction Y1 are equal, so that the lengths of the bit line BL and the word line WL contacted by the unit capacitor layout structure 20 are the same, and the lengths of the word line and the bit line corresponding to each unit capacitor are unified, which is convenient for the subsequent driving design of the word line WL and the bit line BL of the memory.

[0052] In some embodiments, reference Figure 6 , the angle α between the second direction Y0 and the fourth direction Y1 is 0, and the angle β between the third direction X1 and the fourth direction Y1 is 60°; in addition, the word line WL extends in the third direction X1, and the bit line BL extends in the second direction Y0 to satisfy the row and column relationship between the word line WL and the bit line BL.

[0053] It should be noted that in the subsequent description of this embodiment, this example is used as an example for description only, which is only used for those skilled in the art to understand the storage block layout structure 100 provided by the present disclosure. Those skilled in the art can use other α and β to replace the corresponding angles to obtain other storage block layout structures.

[0054] For the memory array layout structure 200 arranged in the first direction X0, in one example, refer to Figure 7 The plurality of memory array layout structures 200 arranged in the first direction X0 have the same position in the second direction Y0.

[0055] Specifically, for the plurality of memory array layout structures 200 arranged in the first direction X0 , the C side of each memory array layout structure 200 has the same position in the second direction Y0 , and the D side of each memory array layout structure 200 has the same position in the second direction Y0 .

[0056] It should be noted that the understanding of “same position” means that in the diagram of the corresponding storage array layout structure 200, after a plane index coordinate system is established with the first direction X0 and the second direction Y0 as axes, the coordinates of the corresponding axis in the second direction Y0 are consistent, that is, the positions in the second direction Y0 are the same; similarly, the coordinates of the corresponding axis in the first direction X0 are consistent, that is, the positions in the first direction X0 are the same.

[0057] for Figure 7 Schematic memory block layout structure 100, refer to Figure 8, between every two storage array layout structures 200 arranged in the first direction X0, it also includes: a plurality of supplementary word line structures 301, each supplementary word line structure 301 is configured to connect a word line WL in the storage array layout structures 200 on both sides, and is coupled to the word line driver of the memory through a conductive node 302, wherein the conductive node 302 is set on the supplementary word line structure 301.

[0058] For the conductive node 302, in an example, a memory may include multiple wafers, including: an array wafer and a logic wafer, wherein only word lines WL, bit lines BL and cell capacitors Cell Cap are set on the array wafer, and the logic wafer is used to control and read and write the array wafer; in a specific application, the array wafer and the logic wafer are connected by hybrid bonding, wherein the word line driver SWD is connected to the connection node of the word line WL in the array transistor, namely the conductive node 302, by hybrid bonding.

[0059] Furthermore, the supplementary word line structure 301 is configured to connect the word lines WL with the same position relationship in the memory array layout structure 200 on both sides.

[0060] Regarding the understanding of “same position relationship”, “same position relationship” refers to word lines located at the same position in different memory array layout structures 200. For example, the memory array includes 200 word lines WL, which are the 1st word line, the 2nd word line... the 200th word line in the second direction Y0; connecting the word lines WL at the same position means connecting the i-th word line in the memory arrays on both sides.

[0061] For the memory, the on / off of the word line WL needs to be controlled by the word line driver, and the word line driver is arranged between the storage array layout structures 200 in the extension direction of the word line WL; since the multiple storage array layout structures 200 in the third direction X1 are not arranged continuously, there is no intersection between the word lines WL with the same position relationship in the adjacent storage array layout structures 200, and they cannot be connected to the same word line driver, so it is necessary to introduce a supplementary word line structure 301 to connect the word lines WL with the same position relationship, so as to connect them to the same word line driver.

[0062] refer to Figure 3 and Figure 7 Since the layout structure of the storage block is still rectangular, the storage block layout structure formed based on the parallelogram area storage array layout structure 200 cannot be implemented. Figure 3The rectangular layout structure shown, therefore, the memory block layout structure 100 has an edge area where the memory array layout structure 200 cannot be set. In some embodiments, the edge area of ​​the memory block layout structure 100 can be incorporated into the peripheral circuit area and laid out as the peripheral circuit area of ​​the memory.

[0063] for Figure 7 For example, assuming that the length of the side A of the storage array layout structure 200 is a, the length of the side C is c, the number of storage array layout structures 200 arranged in the first direction X0 of the storage block layout structure 100 is x, and the number of storage array layout structures 200 continuously arranged in the second direction Y0 is y, then the area S1 of the edge region = 2x*asin60°*acos60° / 2 = xa 2 sin60°cos60°, the area S2 of the storage block layout structure 100 = axsin60°*(cy+acos60°), the proportion of the edge area to the area of ​​the storage block layout structure 100 Z = xa 2 sin60°cos60° / 2[axsin60°*(cy+acos60°)], wherein the size of acos60° is negligible relative to the size of c*y, that is, the proportion Z of the edge area in the area of ​​the storage block layout structure 100 is approximately a / 2cy.

[0064] For the memory array layout structure 200 arranged in the first direction X0, in one example, refer to Fig. 9 , N memory array layout structures 200 are arranged in the first direction X0, and are continuously arranged in the third direction X1, N≥2. Specifically, N memory array layout structures 200 are continuously arranged in the third direction X1, and the position of the N+1th memory array layout structure 200 and the first memory array layout structure 200 in the second direction Y0 is the same.

[0065] for Fig. 9 Schematic memory block layout structure 100, refer to Fig.10 Since N memory array layout structures 200 are arranged continuously in the third direction X1, and the word line WL extends in the third direction X1, the arrangement of the word line WL is the same as the arrangement of the memory array layout structures 200 arranged continuously. At this time, the memory array layout structures 200 arranged continuously in the third direction X1 share the word line WL, and the word line WL is coupled to the word line driver of the memory through the conductive node 302; wherein the conductive node 302 is arranged on the word line WL at the edge position of any memory array layout structure 200.

[0066] Compared to Figure 7 Example, Fig. 9In the example storage block layout structure 100, the introduction of the supplementary word line structure is avoided, and the wiring of the storage block layout structure 100 is relatively simple. However, since N storage array layout structures 200 are continuously arranged in the third direction X1, the area of ​​the edge region in the storage block is larger.

[0067] for Fig. 9 For example, assuming that the length of the side A of the storage array layout structure 200 is a, the length of the side C is c, the number of storage array layout structures 200 arranged in the first direction X0 of the storage block layout structure 100 is x, and the number of storage array layout structures 200 continuously arranged in the second direction Y0 is y, then the area S1 of the edge region is 2x / N*aNsin60°*aNcos60° / 2=xNa 2 sin60°cos60°, the area of ​​the storage block layout structure 100 S2=axsin60°*(cy+aNcos60°), the proportion of the edge area to the area of ​​the storage block layout structure 100 Z=xNa 2 sin60°cos60° / [axsin60°*(cy+aNcos60°)], wherein the size of aNcos60° is negligible relative to the size of c*y, that is, the proportion Z of the edge area in the area of ​​the storage block layout structure 100 is approximately aN / 2cy.

[0068] In some embodiments, reference Fig.11 , N storage array layout structures 200 are arranged in a first direction X0 and are continuously arranged in a third direction X1, including: two storage array layout structures 200 continuously arranged in the third direction X1 constitute a storage array layout structure group 400, the storage array layout structure group 400 is arranged in the first direction X0, and is continuously arranged in the second direction Y0 to constitute a storage block layout structure 100, and the multiple storage array layout structure groups 400 arranged in the first direction X0 have the same position in the second direction Y0.

[0069] for Fig.10 Schematic memory block layout structure 100, refer to Fig.12 The two memory array layout structures 200 in the memory array layout structure group 400 share a word line WL, and the word line WL is coupled to a word line driver of the memory through a conductive node 302 , wherein the conductive node 302 is disposed on the word line WL between the two memory array layout structures 200 .

[0070] Compared to Fig. 9 Example, Fig.11In the exemplary memory layout structure 100 , every two memory array layout structures 200 are arranged consecutively in the third direction X1 . The number of memory array layout structures 200 arranged consecutively in the third direction X1 is relatively small, and the area of ​​the edge region is also relatively small.

[0071] for Fig.11 For example, similarly, assuming that the length of the side A of the storage array layout structure 200 is a, the length of the side C is c, the number of storage array layout structures 200 arranged in the first direction X0 of the storage block layout structure 100 is x, and the number of storage array layout structures 200 continuously arranged in the second direction Y0 is y, then the area S1 of the edge region = 2x / 2*2asin60°*2acos60° / 2 = 2xa 2 sin60°cos60°, the area of ​​the storage block layout structure 100 S2=axsin60°*(cy+aNcos60°), the proportion of the edge area to the area of ​​the storage block layout structure 100 Z=2xa 2 sin60°cos60° / axsin60°*(cy+aNcos60°), wherein the size of aNcos60° is negligible relative to the size of c*y, that is, the proportion Z of the edge area in the area of ​​the storage block layout structure 100 is approximately a / cy.

[0072] In some embodiments, reference Fig.13 All storage array layout structures 200 arranged in the first direction X0 are continuously arranged in the third direction X1. It should be noted that the N storage array layout structures 200 arranged in the first direction X0 are continuously arranged in the third direction X1. There are many specific combinations, which are not given one by one in this embodiment, and the examples in this embodiment do not limit the number of N.

[0073] The storage block layout structure 100 provided in this embodiment provides a new arrangement of word lines WL and bit lines BL, wherein the angle between the word lines WL and the bit lines BL is an acute angle. In addition, the arrangement of unit capacitors coupled to the word lines WL and the bit lines BL is adjusted from a square arrangement to a honeycomb arrangement. The honeycomb arrangement has a higher stacking density than the square arrangement, thereby achieving high-density stacking of unit capacitors, increasing the number of unit capacitors of DRAM under the same area, that is, increasing the storage capacity of DRAM under the same area.

[0074] In addition, the unit capacitor layout structure 20 is set to a parallelogram area parallel to the word line WL and the bit line BL to match the parallelogram area of ​​the constructed storage array layout structure 200; in addition, the lengths of the unit capacitor layout structure 20 in the third direction X1 and the fourth direction Y1 are equal, so that the lengths of the bit line BL and the word line WL contacted by the unit capacitor layout structure 20 are the same, and the lengths of the word line and the bit line corresponding to each unit capacitor are unified, which is convenient for the subsequent drive design of the word line WL and the bit line BL of the memory.

[0075] It should be noted that the features disclosed in the storage block layout structure provided in the above embodiments can be arbitrarily combined without conflict to obtain a new storage block layout structure embodiment.

[0076] Another embodiment of the present disclosure provides a memory, in which each memory block of the memory is arranged based on the memory block layout structure provided in the above embodiment to increase the storage capacity of DRAM under the same area.

[0077] Specifically, refer to Figure 3 For the same memory, the memory includes a plurality of memory blocks, and the plurality of memory blocks are arranged in two rows on opposite sides of the memory, and the remaining area after the memory blocks are arranged (the area between the memory blocks and the outer area of ​​the memory blocks) is used as the peripheral circuit area of ​​the memory; for the same memory block, the memory block includes a plurality of memory arrays, and each memory array is composed of a plurality of word lines and a plurality of bit lines.

[0078] In some examples, the memory may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphic double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type dual synchronous dynamic random access memory DDR2 SDRAM, a double data rate type triple synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, a thyristor random access memory TRAM, etc.; or may be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc.

[0079] Each storage block is formed based on the storage block layout structure 100 provided in the above embodiment, and the specific reference is Figure 4The storage block layout structure 100 includes: a plurality of storage array layout structures 200, the plurality of storage array layout structures 200 are arranged in a first direction X0, and are continuously arranged in a second direction Y0 to form the storage block layout structure 100; wherein each storage array layout structure 200 is used to form a storage array in a storage block, and the first direction X0 and the second direction Y0 are perpendicular to each other. The storage array layout structure 200 is configured as a parallelogram region arranged based on a third direction X1 and a fourth direction Y1; wherein the angle α between the second direction Y0 and the fourth direction Y1 is less than 90°, and the angle 0 between the third direction X1 and the fourth direction Y1 is less than 90°. A plurality of word lines WL and a plurality of bit lines BL are arranged in each storage array layout structure 200, and one of the plurality of word lines WL and the plurality of bit lines BL is arranged at intervals in the third direction X1 and extends in the fourth direction Y1, and the other is arranged at intervals in the fourth direction Y1 and extends in the third direction X1.

[0080] For each storage block, a new arrangement of word lines WL and bit lines BL is provided, and the angle between the word lines WL and the bit lines BL is an acute angle. In addition, the arrangement of unit capacitors coupled to the word lines WL and the bit lines BL is adjusted from a square arrangement to a honeycomb arrangement. The honeycomb arrangement has a higher stacking density than the square arrangement, thereby achieving high-density stacking of unit capacitors, increasing the number of unit capacitors of DRAM under the same area, that is, increasing the storage capacity of DRAM under the same area.

[0081] In some embodiments, reference Figure 4 Each storage array layout structure 200 includes a plurality of unit capacitor layout structures 20, and the plurality of unit capacitor layout structures 20 are continuously arranged in the third direction X1 and the fourth direction Y1, thereby forming a storage array layout structure 200 in a parallelogram area, wherein the unit capacitor layout structure 20 is used to form a unit capacitor in the storage array, and the unit capacitor layout structure is configured as a parallelogram area arranged based on the third direction X1 and the fourth direction Y1, wherein the lengths of the unit capacitor layout structures arranged in the third direction X1 and the fourth direction Y1 are equal.

[0082] The unit capacitor layout structure 20 is set to a parallelogram area parallel to the word line WL and the bit line BL to match the parallelogram area of ​​the constructed storage array layout structure 200; in addition, the lengths of the unit capacitor layout structure 20 in the third direction X1 and the fourth direction Y1 are equal, so that the lengths of the bit line BL and the word line WL contacted by the unit capacitor layout structure 20 are the same, and the lengths of the word line and the bit line corresponding to each unit capacitor are unified, which is convenient for the subsequent driving design of the word line WL and the bit line BL of the memory.

[0083] For the memory array layout structure 200 arranged in the first direction X0, in one example, refer to Figure 7 The plurality of memory array layout structures 200 arranged in the first direction X0 have the same position in the second direction Y0.

[0084] for Figure 7 For example, assuming that the length of the side A of the storage array layout structure 200 is a, the length of the side C is c, the number of storage array layout structures 200 arranged in the first direction X0 of the storage block layout structure 100 is x, and the number of storage array layout structures 200 continuously arranged in the second direction Y0 is y, then the area S1 of the edge region = 2x*asin60°*acos60° / 2 = xa 2 sin60°cos60°, the area S2 of the storage block layout structure 100 = axsin60°*(cy+acos60°), the proportion of the edge area to the area of ​​the storage block layout structure 100 Z = xa 2 sin60°cos60° / [axsin60°*(cy+acos60°)], wherein the size of acos60° is negligible relative to the size of c*y, that is, the proportion Z of the edge area in the area of ​​the storage block layout structure 100 is approximately a / 2cy.

[0085] In addition, for Figure 7 For example, refer to Figure 8 Since the multiple memory array layout structures 200 in the third direction X1 are not arranged continuously, there are parallel word lines WL in adjacent memory array layout structures 200, and there is no intersection between the parallel word lines WL, and they cannot be connected to the same word line driver. Therefore, it is necessary to introduce a supplementary word line structure 301 to connect the parallel word lines WL, so as to connect them to the same word line driver.

[0086] For the memory array layout structure 200 arranged in the first direction X0, in one example, refer to Fig. 9 , N memory array layout structures 200 are arranged in the first direction X0 and are continuously arranged in the third direction X1, N≥2.

[0087] for Fig. 9 For example, assuming that the length of the side A of the storage array layout structure 200 is a, the length of the side C is c, the number of storage array layout structures 200 arranged in the first direction X0 of the storage block layout structure 100 is x, and the number of storage array layout structures 200 continuously arranged in the second direction Y0 is y, then the area S1 of the edge region is 2x / N*aNsin60°*aNcos60° / 2=xNa 2sin60°cos60°, the area of ​​the storage block layout structure 100 S2=axsin60°*(cy+aNcos60°), the proportion of the edge area to the area of ​​the storage block layout structure 100 Z=xNa 2 sin60°cos60° / [axsin60°*(cy+aNcos60°)], wherein the size of aNcos60° is negligible relative to the size of c*y, that is, the proportion Z of the edge area in the area of ​​the storage block layout structure 100 is approximately aN / 2cy.

[0088] In addition, for Fig. 9 For example, refer to Fig.10 Since N consecutive memory array layout structures 200 are arranged in a row in the third direction X1, and the word lines WL extend in the third direction X1, the arrangement of the word lines WL is the same as that of the consecutively arranged memory array layout structures 200. At this time, the memory array layout structures 200 arranged in a row in the third direction X1 share the word lines WL, thus avoiding the introduction of a supplementary word line structure, and the wiring of the memory block layout structure 100 is relatively simple.

[0089] In some embodiments, reference Fig.11 , N storage array layout structures 200 are arranged in a first direction X0 and are continuously arranged in a third direction X1, including: two storage array layout structures 200 continuously arranged in the third direction X1 constitute a storage array layout structure group 400, the storage array layout structure group 400 is arranged in the first direction X0, and is continuously arranged in the second direction Y0 to constitute a storage block layout structure 100, and the multiple storage array layout structure groups 400 arranged in the first direction X0 have the same position in the second direction Y0.

[0090] for Fig.11 For example, assuming that the length of the side A of the storage array layout structure 200 is a, the length of the side C is c, the number of storage array layout structures 200 arranged in the first direction X0 of the storage block layout structure 100 is x, and the number of storage array layout structures 200 continuously arranged in the second direction Y0 is y, then the area S1 of the edge region = 2x / 2*2asin60°*2acos60° / 2 = 2xa 2 sin60°cos60°, the area of ​​the storage block layout structure 100 S2=axsin60°*(cy+aNcos60°), the proportion of the edge area to the area of ​​the storage block layout structure 100 Z=2xa 2 sin60°cos60° / axsin60°*(cy+aNcos60°), wherein the size of aNcos60° is negligible relative to the size of c*y, that is, the proportion Z of the edge area in the area of ​​the storage block layout structure 100 is approximately a / cy.

[0091] In addition, for Fig.11 Examples, references Fig.12 The two storage array layout structures 200 in the storage array layout structure group 400 share the word line WL, avoiding the introduction of a supplementary word line structure. The wiring of the storage block layout structure 100 is relatively simple, and the proportion Z of the edge area to the area of ​​the storage block layout structure 100 is relatively small.

[0092] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A storage block layout structure for forming a storage block in a memory, characterized in that: include: A plurality of storage array layout structures, wherein the plurality of storage array layout structures are arranged in a first direction and are continuously arranged in a second direction to form the storage block layout structure; wherein each of the storage array layout structures is used to form a storage array in the storage block, and the first direction and the second direction are perpendicular to each other; The storage array layout structure is configured as a parallelogram area arranged based on a third direction and a fourth direction; wherein an angle α between the second direction and the fourth direction is less than 90°, and an angle 0 between the third direction and the fourth direction is less than β less than 90°; Each of the storage array layout structures is provided with a plurality of word lines and a plurality of bit lines, wherein one of the plurality of word lines and the plurality of bit lines is arranged at intervals in the third direction and extends in the fourth direction, and the other is arranged at intervals in the fourth direction and extends in the third direction.

2. The storage block layout structure according to claim 1, characterized in that: The plurality of storage array layout structures are arranged in a first direction to form the storage block layout structure, including: the plurality of storage array layout structures arranged in the first direction have the same position in the second direction.

3. The storage block layout structure according to claim 2, characterized in that: include: Between every two of the memory array layout structures arranged in the first direction, there are also: a plurality of supplementary word line structures; Each of the supplementary word line structures is configured to connect a word line in the memory array layout structures on both sides and be coupled to a word line driver of the memory through a conductive node; Wherein, the conductive node is arranged on the supplementary word line structure.

4. The storage block layout structure according to claim 3, characterized in that: The supplementary word line structure is configured to connect word lines with the same position relationship in the storage array layout structures on both sides.

5. The storage block layout structure according to claim 1, characterized in that: The plurality of storage array layout structures are arranged in a first direction to form the storage block layout structure, including: N storage array layout structures arranged in the first direction and continuously arranged in the third direction, N≥2.

6. The storage block layout structure according to claim 5, characterized in that: include: The memory array layout structures arranged continuously in the third direction share a common word line, and the word line is coupled to a word line driver of the memory through a conductive node; Wherein, the conductive node is arranged on the word line at an edge position of any of the storage array layout structures.

7. The storage block layout structure according to claim 5, characterized in that: The N storage array layout structures arranged in the first direction and arranged continuously in the third direction include: Two of the storage array layout structures arranged continuously in the third direction constitute a storage array layout structure group; The storage array layout structure groups are arranged in the first direction and are continuously disposed in the second direction to form the storage block layout structure. The plurality of storage array layout structure groups arranged in the first direction have the same position in the second direction.

8. The storage block layout structure according to claim 7, characterized in that: include: Two of the memory array layout structures in the memory array layout structure group share a word line, and the word line is coupled to a word line driver of the memory through a conductive node; Wherein, the conductive node is arranged on the word line between two storage array layout structures.

9. The storage block layout structure according to claim 5, characterized in that: All the storage array layout structures arranged in the first direction are continuously arranged in the third direction.

10. The storage block layout structure according to any one of claims 1 to 9, characterized in that: Each of the storage array layout structures includes a plurality of unit capacitor layout structures, and the plurality of unit capacitor layout structures are continuously arranged in the third direction and the fourth direction; the unit capacitor layout structure is configured as a parallelogram area arranged based on the third direction and the fourth direction, wherein the lengths of the unit capacitor layout structures arranged in the third direction and the fourth direction are the same.

11. The storage block layout structure according to any one of claims 1 to 9, characterized in that: An angle α between the second direction and the fourth direction is 0.

12. The storage block layout structure according to any one of claims 1 to 9, characterized in that: The angle β between the third direction and the fourth direction is 60°.

13. A memory, characterized in that: Each storage block of the memory is arranged based on the storage block layout structure according to any one of claims 1 to 12.

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