Trigger

Abstract

The embodiment of the invention discloses a trigger, relates to the technical field of integrated circuits, and aims to improve the working performance of the trigger. The trigger comprises a sensitive amplifier module, a pulse generation module and an output latch module, the output end of the sensitive amplifier module and the output end of the pulse generation module are respectively connected with the input end of the output latch module; wherein the sensitive amplifier module is configured to receive input data and perform data sampling under the control of a clock signal when a scanning enable signal is at a low level; and the pulse generation module is configured to generate a pulse control signal when a scanning enable signal is at a high level so as to control the output latch module to sample input data according to the pulse control signal. The method is suitable for storing data.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a trigger. Background Art

[0002] Triggers are basic components widely used in digital circuits, usually composed of two-stage latches. In some high-performance applications, such as high-performance chip design, in order to improve the operating speed and power efficiency of the circuit, in related technologies, sampling is simply based on the trigger circuit structure of the sense amplifier (SA).

[0003] However, when applied to chip signal testing scenarios, especially the requirements of scan logic testing, the sensitive amplifier used in the trigger becomes a multi-stage series structure due to the addition of scan input. As each additional stage of the amplification link is added, the noise will also be amplified, and the multi-stage series connection will gradually increase the signal transmission delay, affecting the working performance of the sensitive amplifier, and then affecting the working performance of the trigger. Summary of the invention

[0004] In view of this, an embodiment of the present application provides a trigger to facilitate improving the working performance of the trigger.

[0005] An embodiment of the present application provides a trigger, comprising: a sensitive amplifier module, a pulse generating module and an output latch module; the output end of the sensitive amplifier module and the output end of the pulse generating module are respectively connected to the input end of the output latch module; wherein the sensitive amplifier module is configured to receive input data and perform data sampling under the control of a clock signal when a scan enable signal is at a low level; and the pulse generating module is configured to generate a pulse control signal when a scan enable signal is at a high level, so as to control the output latch module to sample input data according to the pulse control signal.

[0006] According to a specific implementation method of an embodiment of the present application, the output latch module includes a first latch module and a second latch module; the first latch module is connected to the output end of the sensitive amplifier module, and the first latch module is configured to output or latch the data sampled by the sensitive amplifier module when the scan enable signal is at a low level; the input end of the second latch module is connected to the output end of the pulse generation module, and is configured to output or latch the input data according to the pulse control signal when the scan enable signal is at a high level.

[0007] According to a specific implementation method of an embodiment of the present application, the first latch module includes a first sampling unit; the first sampling unit includes an enable switch, a mutually exclusive gate circuit and a clock drive switch; wherein the power supply input end of the enable switch is used to connect to a power supply, the signal input end is used to input a scan enable signal, and the output end is connected to the power supply end of the mutually exclusive gate circuit; the control end of the mutually exclusive gate circuit is connected to the output end of the sensitive amplifier module, and the ground end is connected to the output end of the clock drive switch; the clock drive switch is configured to control the switching of the working state of the first latch module according to the clock signal, so as to output or latch the data sampled by the sensitive amplifier module when the scan enable signal is at a low level.

[0008] According to a specific implementation of the embodiment of the present application, the enable switch includes a first P-type metal oxide semiconductor; the mutually exclusive gate circuit includes a second P-type metal oxide semiconductor and a first N-type metal oxide semiconductor, and the clock drive switch includes a second N-type metal oxide semiconductor; wherein the source of the first P-type metal oxide semiconductor is used to connect to a power supply, the gate is used to input a scan enable signal, and the drain is connected to the source of the second P-type metal oxide semiconductor; the gate of the second P-type metal oxide semiconductor is connected to the output end of the sensitive amplifier module, and the drain is connected to the source of the first N-type metal oxide semiconductor; the gate of the first N-type metal oxide semiconductor is connected to the output end of the sensitive amplifier module, and the drain is connected to the source of the second N-type metal oxide semiconductor; the gate of the second N-type metal oxide semiconductor is used to input a clock signal, and the drain is a ground terminal.

[0009] According to a specific implementation method of an embodiment of the present application, the output latch module also includes a first NOT gate; the input end of the first NOT gate is respectively connected to the drain of the second P-type metal oxide semiconductor and the source of the first N-type metal oxide semiconductor, and the output end serves as the output end of the trigger.

[0010] According to a specific implementation of the embodiment of the present application, the first latch module also includes a first latch unit; the first latch unit includes a third P-type metal oxide semiconductor, a fourth P-type metal oxide semiconductor, the first N-type metal oxide semiconductor and a third N-type metal oxide semiconductor; the source of the third P-type metal oxide semiconductor is connected to the drain of the first P-type metal oxide semiconductor, the gate is connected to the output end of the first NOT gate, and the drain is connected to the source of the fourth P-type metal oxide semiconductor; the gate of the fourth P-type metal oxide semiconductor is used to input a clock signal, and the drain is connected to the source of the first N-type metal oxide semiconductor; the source of the third N-type metal oxide semiconductor is connected to the drain of the first N-type metal oxide semiconductor, the gate is connected to the output end of the first NOT gate, and the drain serves as a ground terminal.

[0011] According to a specific implementation of the embodiment of the present application, the second latch module includes a second sampling unit; the second sampling unit includes a fifth P-type metal oxide semiconductor, a sixth P-type metal oxide semiconductor, a fourth N-type metal oxide semiconductor and a fifth N-type metal oxide semiconductor; the source of the fifth P-type metal oxide semiconductor is used to connect to a power supply, the gate is connected to the first output end of the pulse generation module, and the drain is connected to the source of the sixth P-type metal oxide semiconductor; the gate of the sixth P-type metal oxide semiconductor is used to input scan input data, and the drain is respectively connected to the source of the fourth N-type metal oxide semiconductor and the input end of the first NOT gate; the gate of the fourth N-type metal oxide semiconductor is used to input scan input data, and the drain is connected to the source of the fifth N-type metal oxide semiconductor; the gate of the fifth N-type metal oxide semiconductor is connected to the second output end of the pulse generation module, and the drain serves as a ground end.

[0012] According to a specific implementation of the embodiment of the present application, the second latch module includes a second latch unit; the second latch unit includes a seventh P-type metal oxide semiconductor, an eighth P-type metal oxide semiconductor, a sixth N-type metal oxide semiconductor and a seventh N-type metal oxide semiconductor; the source of the seventh P-type metal oxide semiconductor is used to connect to a power supply, the gate is connected to the output end of the first NOT gate, and the drain is connected to the source of the eighth P-type metal oxide semiconductor; the gate of the eighth P-type metal oxide semiconductor is connected to the second output end of the pulse generation module, and the drain is respectively connected to the source of the sixth N-type metal oxide semiconductor and the input end of the first NOT gate; the gate of the sixth N-type metal oxide semiconductor is connected to the output end of the first NOT gate, and the drain is connected to the source of the seventh N-type metal oxide semiconductor; the gate of the seventh N-type metal oxide semiconductor is connected to the first output end of the pulse generation module, and the drain serves as a ground end.

[0013] According to a specific implementation method of an embodiment of the present application, the pulse generation module includes: a NAND gate, a delay unit, a NOR gate and a second NOR gate; the first input end of the NAND gate is used to input a scan enable signal, and the second input end is used to input a clock signal; the delay unit includes a cascade-connected inverter and a buffer, and the input end is connected to the output end of the NAND gate, and is used to delay the signal output from the output end of the NAND gate; the first input end of the NOR gate is connected to the output end of the delay unit, and the second input end is connected to the output end of the NAND gate; the output end of the NOR gate serves as the second output end of the pulse generation module; the second NOR gate is connected to the output end of the NOR gate, and the output end of the NOR gate serves as the first output end of the pulse generation module.

[0014] According to a specific implementation method of an embodiment of the present application, the sensitive amplifier module includes: a sensitive amplifier module body and a level pull-down circuit; the control end of the level pull-down circuit is used to input a scan enable signal, and the power supply end is connected to the output end of the sensitive amplifier module body; the level pull-down circuit is used to pull down the voltage output by the output end of the sensitive amplifier module body when the scan enable signal is at a high level, so that the second latch module samples the input data and outputs or latches it according to the pulse control signal.

[0015] According to a specific implementation of an embodiment of the present application, the sense amplifier module body includes: a differential input pair, a pre-charging unit and a sampling control circuit; the differential input pair includes an eighth N-type metal oxide semiconductor and a ninth N-type metal oxide semiconductor, the gate of the eighth N-type metal oxide semiconductor is used to receive a first state signal of input data, and the gate of the ninth N-type metal oxide semiconductor is used to receive a second state signal of input data, and the first state signal and the second state signal are differential signals to each other; the pre-charging unit includes a first pre-charging circuit and a second pre-charging circuit; the first pre-charging circuit is connected to the source of the eighth N-type metal oxide semiconductor, and the second pre-charging circuit is connected to the source of the ninth N-type metal oxide semiconductor; the first pre-charging circuit is used to pre-charge the source of the eighth N-type metal oxide semiconductor when the clock signal is at a low level; the second pre-charging circuit is used to pre-charge the ninth N-type metal oxide semiconductor when the clock signal is at a low level The sampling control circuit comprises a first sampling control circuit and a second sampling control circuit, wherein the first sampling control circuit is connected to the second sampling control circuit; a first end of the first sampling control circuit is connected to the drain of the eighth N-type metal oxide semiconductor, and a second end is connected to the source of the eighth N-type metal oxide semiconductor; the first sampling control circuit is used to control the eighth N-type metal oxide semiconductor to be turned on when the clock signal is at a high level, so as to adopt a first state signal for sampling input data, and output the sampled first state signal to the first latch module; a first end of the second sampling control circuit is connected to the drain of the ninth N-type metal oxide semiconductor, and a second end is connected to the source of the ninth N-type metal oxide semiconductor, and the second sampling control circuit is used to control the ninth N-type metal oxide semiconductor to be turned on when the clock signal is at a high level, so as to adopt a second state signal for sampling input data, and output the sampled second state signal to the first latch module.

[0016] The trigger of the present embodiment is achieved by connecting the output end of the sensitive amplifier module and the output end of the pulse generating module to the input end of the output latch module respectively; wherein the sensitive amplifier module is configured to receive input data and perform data sampling under the control of the clock signal when the scan enable signal is at a low level, and the pulse generating module is configured to generate a pulse control signal when the scan enable signal is at a high level to control the output latch module to sample the input data according to the pulse control signal. Since the pulse generating module generates a pulse control signal when the scan enable signal is at a high level to control the output latch module to sample the input data according to the pulse control signal, that is, the pulse generating module and the output latch module work together to realize the scanning function, and the realization of the scanning function is independent of the sensitive amplifier module. Therefore, the trigger of the present embodiment ensures the performance of the sensitive amplifier module while realizing the addition of the scanning function. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 It is a structural schematic diagram of a trigger in the prior art; Figure 2 A schematic diagram of the structure of a trigger provided in a specific embodiment of the present application; Figure 3 A schematic diagram of the structure of a second latch module in a trigger provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The embodiments of the present application are described in detail below in conjunction with the accompanying drawings. It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0020] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0021] See also Figure 1As mentioned in the background art, in the prior art, in order to add a scanning function to a trigger based on a sense amplifier, it is necessary to connect the sense amplifier structure in multiple stages in series, such as Figure 1 The N-type metal oxide semiconductor (N-channel Metal-Oxide-Semiconductor) N01 receiving the input data D and the N-type metal oxide semiconductor N02 receiving the scan unenable signal SEN are connected in series. In this way, when the trigger is in a normal working state, for example, the input data D=1, when the clock signal is 1, the N-type metal oxide semiconductor N01 and the N-type metal oxide semiconductor N02 need to be turned on to sample and output the data D=1. That is, because the trigger has a scan function, the sensitivity of the sense amplifier structure is reduced, which in turn affects the working performance of the trigger. In addition, in order to resist random fluctuations, the sense amplifier structure uses large-area transistors. In this way, increasing the number of stages will greatly increase the area of ​​the trigger.

[0022] Based on this, the inventors discovered during the research process that the scanning function can be separated from the sense amplifier structure, that is, the working state of the sense amplifier is independent of the scanning state, so as to ensure the performance of the sense amplifier structure while adding the scanning function. In addition, it is convenient to reduce the area of ​​the trigger.

[0023] In order to enable those skilled in the art to better understand the technical concept, implementation plan and beneficial effects of the embodiments of the present application, specific embodiments are described in detail below.

[0024] Figure 2 A schematic diagram of the structure of a trigger provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the structural diagram of the trigger of this embodiment may include: a sensitive amplifier module 1, a pulse generating module 2 and an output latch module 3; the output end of the sensitive amplifier module 1 and the output end of the pulse generating module 2 are respectively connected to the input end of the output latch module 3; wherein, The sensitive amplifier module 1 is configured to receive input data and perform data sampling under the control of the clock signal when the scan enable signal is at a low level; the pulse generation module 2 is configured to generate a pulse control signal when the scan enable signal is at a high level to control the output latch module 3 to sample the input data according to the pulse control signal.

[0025] The sense amplifier module 1 of this embodiment can amplify input data.

[0026] When the scan enable signal is at a low level, the trigger is in a normal working state; when the scan enable signal is at a high level, the trigger is in a scanning state, that is, the trigger is in a scan test state. The low level can be 0, and the high level can be 1.

[0027] It can be understood that whether the trigger is in normal working state or scanning state, it includes sampling input data and latching state (keeping the output unchanged).

[0028] When the scan enable signal is at a low level, the trigger is in a normal working state. At this time, the sense amplifier module 1 receives input data and performs data sampling under the control of the clock signal. Further, the input data sampled by the sense amplifier module 1 can be output through the output latch module 3.

[0029] When the scan enable signal is at a high level, the pulse generating module 2 generates a pulse control signal according to the scan enable signal, thereby controlling the output latch module 3 to sample input data according to the pulse control signal.

[0030] In this embodiment, the output end of the sensitive amplifier module 1 and the output end of the pulse generating module 2 are respectively connected to the input end of the output latch module 3; wherein, the sensitive amplifier module 1 is configured to receive input data and perform data sampling under the control of the clock signal when the scan enable signal is at a low level, and the pulse generating module 2 is configured to generate a pulse control signal when the scan enable signal is at a high level to control the output latch module 3 to sample the input data according to the pulse control signal. Since the pulse generating module 2 generates a pulse control signal when the scan enable signal is at a high level to control the output latch module 3 to sample the input data according to the pulse control signal, that is, the pulse generating module 2 and the output latch module 3 work together to realize the scanning function, and the realization of the scanning function is independent of the sensitive amplifier module. Therefore, the trigger of this embodiment ensures the performance of the sensitive amplifier module 1 while realizing the addition of the scanning function, and further facilitates the guarantee of the working performance of the trigger.

[0031] In normal working state and scanning working state, the trigger can share a latch module. In this way, the latch module needs to switch between two states. In this case, the latch module will be more complicated. In order to simplify the structure of the latch module, in some examples, the output latch module 3 can include a first latch module 30 and a second latch module 32.

[0032] The first latch module 30 is connected to the output end of the sensitive amplifier module 1, and the first latch module 30 is configured to output or latch the data sampled by the sensitive amplifier module 1 when the scan enable signal is at a low level; the input end of the second latch module 32 is connected to the output end of the pulse generation module 2, and is configured to output or latch the input data sampled according to the pulse control signal when the scan enable signal is at a high level.

[0033] When the scan enable signal is at a low level, the first latch module 30 can output or latch the data sampled by the sense amplifier module 1. Whether the data sampled by the sense amplifier module 1 is output or latched can be controlled by a clock signal.

[0034] When the scan enable signal is at a high level, the second latch module 32 samples the input data and outputs or latches it according to the pulse control signal. In some examples, when the pulse control signal is in a first state, the second latch module 32 outputs the sampled input data. When the pulse control signal is in a second state, the output of the second latch module 32 remains unchanged, that is, it is in a latched state.

[0035] The sampling unit for the first latch module 30 to complete the output of the data sampled by the sensitive amplifier module 1 can sample any circuit structure. To simplify the structure of the sampling unit, in some examples, the first latch module 30 includes a first sampling unit 30a; the first sampling unit 30a includes an enable switch P7, a mutually exclusive gate circuit 30aa and a clock drive switch 30ab; wherein the power supply input end of the enable switch P7 is used to connect to a power supply, the signal input end is used to input a scan enable signal, and the output end is connected to the power supply end of the mutually exclusive gate circuit 30aa; the control end of the mutually exclusive gate circuit 30aa is connected to the output end of the sensitive amplifier module, and the ground end is connected to the output end of the clock drive switch 30ab; the clock drive switch 30ab is configured to control the switching of the working state of the first latch module 30 according to the clock signal, so as to output or latch the data sampled by the sensitive amplifier module 1 when the scan enable signal is at a low level.

[0036] In this embodiment, the enable switch P7, the exclusive gate circuit 30aa and the clock drive switch 30ab cooperate with each other to achieve the function of outputting or latching the data sampled by the sense amplifier module 1 when the scan enable signal is at a low level.

[0037] In a specific example, the enabling switch P7 includes a first P-type metal oxide semiconductor P7; the mutually exclusive gate circuit 30aa includes a second P-type metal oxide semiconductor P8 and a first N-type metal oxide semiconductor N7, and the clock driving switch 30ab includes a second N-type metal oxide semiconductor N8; wherein, The source of the first P-type metal oxide semiconductor P7 is used to connect to a power source, the gate is used to input a scan enable signal, and the drain is connected to the source of the second P-type metal oxide semiconductor P8; The gate of the second P-type metal oxide semiconductor P8 is connected to the output end of the sense amplifier module 1, and the drain is connected to the source of the first N-type metal oxide semiconductor N7; The gate of the first N-type metal oxide semiconductor N7 is connected to the output end of the sense amplifier module 1, and the drain is connected to the source of the second N-type metal oxide semiconductor N8; The gate of the second N-type metal oxide semiconductor N8 is used to input a clock signal, and the drain is a ground terminal.

[0038] P-type metal oxide semiconductor (PMOS, P-channel Metal-Oxide-Semiconductor) refers to a MOS tube with an n-type substrate and a p-channel, which relies on the flow of holes to transport current; N-type metal oxide semiconductor (NMOS, N-channelMetal-Oxide-Semiconductor) refers to a MOS tube with a p-type substrate and a p-channel, which relies on the flow of holes to transport current.

[0039] When the scan enable signal is at a low level, the first PMOS transistor P7 is turned on; when the clock signal is at a high level, the second NMOS transistor N8 is turned on.

[0040] The gate of the second PMOS tube P8 and the gate of the first NMOS tube N7 are respectively connected to the output end of the sense amplifier module 1. When the output end of the sense amplifier module 1 outputs a high level, the second PMOS tube P8 is turned off and the first NMOS tube N7 is turned on. In this way, the voltage of the source of the first NMOS tube N7 is pulled down. When the output end of the sense amplifier module 1 outputs a low level, the second PMOS tube P8 is turned on and the first NMOS tube N7 is turned off. In this way, the voltage of the drain of the second PMOS tube P8 is pulled up, so as to facilitate the output of the data sampled by the sense amplifier module 1.

[0041] In one example, the output latch module 3 may further include a first NOT gate 34; the input end of the first NOT gate 34 is respectively connected to the drain of the second P-type metal oxide semiconductor P8 and the source of the first N-type metal oxide semiconductor N7, and the output end serves as the output end of the trigger.

[0042] The voltage of the drain of the second PMOS tube P8 and the voltage of the source of the first NMOS tube N7 can be inverted through the first NOT gate 34. When the output end of the sense amplifier module 1 outputs a high level, the voltage of the source of the first NMOS tube N7 is pulled down, and then through the first NOT gate 34, the voltage outputted by the output end of the trigger is a high level; when the output end of the sense amplifier module 1 outputs a low level, the voltage of the drain of the second PMOS tube P8 is pulled up, and then through the first NOT gate 34, the voltage outputted by the output end of the trigger is a low level, thereby realizing the output of the data sampled by the sense amplifier module 1.

[0043] The latch unit for completing latching in the first latch module 30 can sample any circuit structure. To simplify the structure of the latch unit, in some examples, the first latch module 30 can also include a first latch unit 30b; the first latch unit 30b includes a third P-type metal oxide semiconductor P9, a fourth P-type metal oxide semiconductor P10, a first N-type metal oxide semiconductor N7 and a third N-type metal oxide semiconductor N9; the source of the third P-type metal oxide semiconductor P9 is connected to the drain of the first P-type metal oxide semiconductor P7, the gate is connected to the output end of the first NOT gate, and the drain is connected to the source of the fourth P-type metal oxide semiconductor P10; the gate of the fourth P-type metal oxide semiconductor P10 is used to input a clock signal, and the drain is connected to the source of the first N-type metal oxide semiconductor N7; the source of the third N-type metal oxide semiconductor N9 is connected to the drain of the first N-type metal oxide semiconductor N7, the gate is connected to the output end of the first NOT gate, and the drain serves as a ground terminal.

[0044] When the scan enable signal is at a high level, the first PMOS transistor P7 is turned off; when the clock signal is at a low level, the second NMOS transistor N8 is turned off, so that the first sampling unit 30a is in an open circuit state as a whole.

[0045] When the clock signal is at a low level, the fourth PMOS tube P10 is turned on, and the gate of the first NMOS tube N7 is connected to the output end of the sense amplifier module 1. When the clock signal is at a low level, the output end of the sense amplifier module 1 outputs a high level, and the first NMOS tube N7 is turned on. Therefore, the circuit corresponding to the first latch unit 30b is the third PMOS tube P9 and the third NMOS tube N9, and the third PMOS tube P9 and the third NMOS tube N9 are respectively connected to the output end of the first NOT gate. When the output end of the first NOT gate outputs a high level, the third PMOS tube P9 is turned off and the third NMOS tube N9 is turned on. In this way, the input end of the first NOT gate is pulled low, and further, the output end of the first NOT gate is at a high level; when the output end of the first NOT gate outputs a low level, the third PMOS tube P9 is turned on and the third NMOS tube N9 is turned off. In this way, the output end of the first NOT gate is pulled high, and further, the output end of the first NOT gate is at a low level, thereby realizing latching.

[0046] In the scanning working state, in order to simplify the structure of the second latch module 32, in one embodiment, the second latch module 32 includes a second sampling unit 32a; the second sampling unit 32a includes a fifth P-type metal oxide semiconductor P11, a sixth P-type metal oxide semiconductor P12, a fourth N-type metal oxide semiconductor N12 and a fifth N-type metal oxide semiconductor N13; the source of the fifth P-type metal oxide semiconductor P11 is used to connect to the power supply, the gate is connected to the first output end of the pulse generating module 2, and the drain is connected to the source of the sixth P-type metal oxide semiconductor P12; the gate of the sixth P-type metal oxide semiconductor P12 is used to input scanning input data, and the drain is respectively connected to the source of the fourth N-type metal oxide semiconductor N12 and the input end of the first NOT gate; the gate of the fourth N-type metal oxide semiconductor N12 is used to input scanning input data, and the drain is connected to the source of the fifth N-type metal oxide semiconductor N13; the gate of the fifth N-type metal oxide semiconductor N13 is connected to the second output end of the pulse generating module 2, and the drain is used as the ground end.

[0047] When the first output end of the pulse generating module 2 outputs a low level and the second output end outputs a high level, the fifth PMOS tube P11 and the fifth NMOS tube N13 are turned on. If the scanned input data is a high level, the input end of the first NOT gate is pulled low, and then the output end of the first NOT gate is a high level; if the scanned input data is a low level, the input end of the first NOT gate is pulled high, and then the output end of the first NOT gate is a low level, thereby sampling the scanned input data and outputting it.

[0048] The latch unit for completing latching by the second latch module 32 can sample any circuit structure. To simplify the structure of the latch unit, in some examples, the second latch module 32 includes a second latch unit 32b; the second latch unit 32b includes a seventh P-type metal oxide semiconductor P13, an eighth P-type metal oxide semiconductor P14, a sixth N-type metal oxide semiconductor N10 and a seventh N-type metal oxide semiconductor N11; the source of the seventh P-type metal oxide semiconductor P13 is used to connect to a power supply, the gate is connected to the output end of the first NOT gate, and the drain is connected to the source of the eighth P-type metal oxide semiconductor P14; the gate of the eighth P-type metal oxide semiconductor P14 is connected to the second output end of the pulse generating module 2, and the drain is respectively connected to the source of the sixth N-type metal oxide semiconductor N10 and the input end of the first NOT gate; the gate of the sixth N-type metal oxide semiconductor N10 is connected to the output end of the first NOT gate, and the drain is connected to the source of the seventh N-type metal oxide semiconductor N11; the gate of the seventh N-type metal oxide semiconductor N11 is connected to the first output end of the pulse generating module 2, and the drain is used as a ground terminal.

[0049] When the first output terminal of the pulse generating module 2 outputs a high level and the second output terminal outputs a low level, the fifth PMOS transistor P11 and the fifth NMOS transistor N13 are turned off, so that the output terminal of the NOR gate is not affected by the sixth PMOS transistor P12 and the fourth NMOS transistor N12.

[0050] When the first output end of the pulse generating module 2 outputs a high level and the second output end outputs a low level, the eighth PMOS tube P14 and the seventh NMOS tube N11 are turned on, so that the circuit corresponding to the second latch unit 32b is the seventh PMOS tube P13 and the sixth NMOS tube N10, and the seventh PMOS tube P13 and the sixth NMOS tube N10 are respectively connected to the output end of the first NOT gate. When the output end of the first NOT gate outputs a high level, the seventh PMOS tube P13 is turned off and the sixth NMOS tube N10 is turned on. In this way, the input end of the first NOT gate is pulled low, and further, the output end of the first NOT gate is a high level; when the output end of the first NOT gate outputs a low level, the seventh PMOS tube P13 is turned on and the sixth NMOS tube N10 is turned off. In this way, the output end of the first NOT gate is pulled high, and further, the output end of the first NOT gate is a low level, thereby realizing latching.

[0051] In a specific example, when SE=1 and CK is a rising edge, a pulse signal SECK or SECKB is generated by a pulse generation module. In the stage of SECK=1 and SECKB=0, the second sampling unit works to sample and scan the input data and output it; when SE=1 and the clock signal is in a state other than a rising edge, the second latch unit 32b works, that is, it works in a latched state.

[0052] See also Figure 2 In a specific example, the pulse generation module includes: a NAND gate, a delay unit, and a NOR gate and a second NOR gate; the first input end of the NAND gate is used to input a scan enable signal, and the second input end is used to input a clock signal; the delay unit includes a cascade-connected inverter and a buffer, and the input end is connected to the output end of the NAND gate, and is used to delay the signal output from the output end of the NAND gate; the first input end of the NOR gate is connected to the output end of the delay unit, and the second input end is connected to the output end of the NAND gate; the output end of the NOR gate serves as the second output end of the pulse generation module; the second NOR gate is connected to the output end of the NOR gate, and the output end of the NOR gate serves as the first output end of the pulse generation module.

[0053] In one embodiment, the sensitive amplifier module 1 may include: a sensitive amplifier module body 10 and a level pull-down circuit 12; the control end of the level pull-down circuit 12 is used to input a scan enable signal, and the power supply end is connected to the output end of the sensitive amplifier module body 10; the level pull-down circuit 12 is used to pull down the voltage output by the output end of the sensitive amplifier module body 10 when the scan enable signal is at a high level, so that the second latch module 32 samples the input data and outputs or latches it according to the pulse control signal.

[0054] See also Figure 3 When SE=1, the working principle of the circuit is as follows: SE=1, no matter what state the clock signal is in, the voltage SL outputted from the output end of the sense amplifier module body 10 is pulled down to 0 by the level-lowering circuit 12, the entire sense amplifier module body 10 is in a stable state, and the first PMOS tube P7 and the first NMOS tube N7 are turned off, the voltage outputted from the output end of the sense amplifier module body 10 no longer affects the entire output latch module 3, and thus, only the second latch module 32 of the output latch module 3 works.

[0055] In one embodiment, the sense amplifier module body 10 may include: a differential input pair, a pre-charging unit, and a sampling control circuit.

[0056] The differential input pair includes an eighth N-type metal oxide semiconductor N0 and a ninth N-type metal oxide semiconductor N3, the gate of the eighth N-type metal oxide semiconductor N0 is used to receive a first state signal of input data, and the gate of the ninth N-type metal oxide semiconductor N3 is used to receive a second state signal of input data, and the first state signal and the second state signal are differential signals.

[0057] The pre-charging unit includes a first pre-charging circuit 10a and a second pre-charging circuit 10b; the first pre-charging circuit 10a is connected to the source of the eighth N-type metal oxide semiconductor N0, and the second pre-charging circuit 10b is connected to the source of the ninth N-type metal oxide semiconductor N3; the first pre-charging circuit 10a is used to pre-charge the source of the eighth N-type metal oxide semiconductor N0 when the clock signal is at a low level; the second pre-charging circuit 10b is used to pre-charge the source of the ninth N-type metal oxide semiconductor N3 when the clock signal is at a low level.

[0058] The sampling control circuit includes a first sampling control circuit and a second sampling control circuit, the first sampling control circuit and the second sampling control circuit are connected; the first end of the first sampling control circuit is connected to the drain of the eighth N-type metal oxide semiconductor N0, and the second end is connected to the source of the eighth N-type metal oxide semiconductor N0; the first sampling control circuit is used to control the eighth N-type metal oxide semiconductor N0 to be turned on when the clock signal is at a high level, so as to adopt a first state signal for sampling input data, and output the sampled first state signal to the first latch module 30; the first end of the second sampling control circuit is connected to the drain of the ninth N-type metal oxide semiconductor N3, and the second end is connected to the source of the ninth N-type metal oxide semiconductor N3, and the second sampling control circuit is used to control the ninth N-type metal oxide semiconductor N3 to be turned on when the clock signal is at a high level, so as to adopt a second state signal for sampling input data, and output the sampled second state signal to the first latch module 30.

[0059] In this embodiment, when the first state signal is at a high level, the second state signal is at a low level; when the first state signal is at a low level, the second state signal is at a high level.

[0060] The input data in this embodiment may be data inputted into the input terminal when the trigger is in a normal working state.

[0061] like Figure 2 As shown, in a specific example, the first pre-charging circuit 10a includes two PMOS tubes connected in series, wherein the source of one PMOS tube P0 is used to connect to the power supply, the gate is used to input the scan enable signal, the source is connected to the source of the other PMOS tube P1, the gate of the PMOS tube P1 is used to input the clock signal, and the drain is connected to the source of the eighth NMOS tube N0.

[0062] When the trigger is in normal working state, the scan enable signal is at a low level, then the PMOS tube P0 is turned on, and when the clock signal is at a low level, the PMOS tube P1 is turned on, then the source of the eighth NMOS tube N0 is pulled high, that is, the voltage of the source of the eighth NMOS tube N0 is at a high level, that is, the source of the eighth NMOS tube N0 is pre-charged when the clock signal is at a low level.

[0063] like Figure 2 As shown, in a specific example, the second pre-charging circuit 10b includes PMOS tubes connected in series, wherein the source of one PMOS tube P4 is used to connect to a power supply, the gate is used to input a scan enable signal, the source is connected to the source of another PMOS tube P5, the gate of the PMOS tube P5 is used to input a clock signal, and the drain is connected to the source of the ninth NMOS tube N3.

[0064] The principle that the second pre-charging circuit 10b pre-charges the source of the ninth NMOS transistor N3 when the clock signal is at a low level is the same as the principle that the first pre-charging circuit 10a pre-charges the source of the eighth NMOS transistor N0.

[0065] When the clock signal is at a low level, the differential input pair is precharged, so that when the clock signal is at a high level, it can quickly enter the state of adopting the input data, thereby improving the working performance of the sensitive amplifier module.

[0066] See also Figure 2 In a specific example, the first sampling control circuit may include a PMOS tube P2, an NMOS tube N1 and an NMOS tube N2; the source of the NMOS tube N1 is connected to the drain of the eighth NMOS tube N0, the gate is used to input the clock signal, and the drain is connected to the source of the NMOS tube N2; the gate of the NMOS tube N2 is connected to the gate of the PMOS tube P2, and the drain is used as a ground terminal; the source of the PMOS tube P2 is used to connect to the power supply, and the drain is connected to the source of the eighth NMOS tube N0.

[0067] The second sampling control circuit may include a PMOS tube P3, an NMOS tube N4 and an NMOS tube N5; the source of the NMOS tube N4 is connected to the drain of the ninth NMOS tube N3, the gate is used to input a clock signal, and the drain is connected to the source of the NMOS tube N5; the gate of the NMOS tube N5 is connected to the gate of the PMOS tube P3, and the drain serves as a ground terminal; the source of the PMOS tube P3 is used to connect to a power supply, and the drain is connected to the source of the ninth NMOS tube N3.

[0068] The drain of the PMOS tube P2 is connected to the source of the ninth NMOS tube N3.

[0069] The drain of the PMOS transistor P2 or the source of the eighth NMOS transistor N0 is connected to the input end of the first latch module 30 as the output end of the sense amplifier module 1 .

[0070] The solution of the present application is described in detail below with a specific embodiment.

[0071] See also Figure 2, when the trigger works in normal state, the scan enable signal is 0, that is, SE=0, the sense-amp works normally, just like the common high-performance trigger (SA-DFF) based on sense-amplifier design. Specific process: when CK=0, the entire sense-amp part is precharged, SL=SR=1, at this time the second half is in latched state, qf_x ensures that the output latch remains unchanged. When CK rises from 0 to 1, the sense-amp works, at this time the sampling input, for example (D=1, SE=0), SL is discharged to 0, and then SR=1 is ensured by the P-type metal oxide semiconductor controlled by SL. At the same time, after CK=1, the output SL=0 is transmitted to the qf node.

[0072] When the trigger is working in the scan test state, the scan enable signal is 1, that is, when SE=0, SE=1, the working principle of the circuit is as follows: SE=1, no matter CK is 0 or 1 or rising edge or falling edge, SL is pulled down to 0 by N6, SR is charged to 1 by P3, and the pre-charge part no longer works because SE=1, and the overall sense-amp is in a stable state. At this time, the output latch is turned off by P7 (SE=1) and N7 (SL=0), and SL no longer has any effect on the output latch. In this case, the entire SA-SDF can be simplified to Figure 3 From the circuit diagram, we can see that this is a simple pulse-latch structure.

[0073] like Figure 3 As shown in the figure, when SE=1 and CK is a rising edge, the pulse generator module 2 (pulse generator) generates SECK / SECKB with a certain pulse width. In the stage of SECK=1 and SECKB=0, SI is sampled and output. When SE=1, the clock signal is in other states except the rising edge, and the output remains unchanged, that is, latched.

[0074] This embodiment proposes a novel SA-SDF structure, which adds a scan function while ensuring the performance of the SA-DFF main body as much as possible.

[0075] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0076] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0077] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A trigger, characterized in that: include: A sensitive amplifier module, a pulse generation module and an output latch module; The output end of the sense amplifier module and the output end of the pulse generation module are respectively connected to the input end of the output latch module; wherein, The sense amplifier module is configured to receive input data and perform data sampling under the control of a clock signal when the scan enable signal is at a low level; The pulse generating module is configured to generate a pulse control signal when the scan enable signal is at a high level, so as to control the output latch module to sample input data according to the pulse control signal.

2. The trigger according to claim 1, characterized in that: The output latch module includes a first latch module and a second latch module; The first latch module is connected to the output end of the sense amplifier module, and the first latch module is configured to output or latch the data sampled by the sense amplifier module when the scan enable signal is at a low level; The input end of the second latch module is connected to the output end of the pulse generating module, and is configured to sample input data and output or latch it according to the pulse control signal when the scan enable signal is at a high level.

3. The trigger according to claim 2, characterized in that: The first latch module includes a first sampling unit; the first sampling unit includes an enable switch, a mutex gate circuit and a clock drive switch; wherein, The power supply input end of the enable switch is used to connect to a power supply, the signal input end is used to input a scan enable signal, and the output end is connected to the power supply end of the mutually exclusive gate circuit; The control end of the mutually exclusive gate circuit is connected to the output end of the sensitive amplifier module, and the ground end is connected to the output end of the clock drive switch; The clock drive switch is configured to control switching of the working state of the first latch module according to a clock signal, so as to output or latch the data sampled by the sense amplifier module when the scan enable signal is at a low level.

4. The trigger according to claim 3, characterized in that: The enabling switch includes a first P-type metal oxide semiconductor; the mutually exclusive gate circuit includes a second P-type metal oxide semiconductor and a first N-type metal oxide semiconductor, and the clock driving switch includes a second N-type metal oxide semiconductor; wherein, The source of the first P-type metal oxide semiconductor is used to connect to a power source, the gate is used to input a scan enable signal, and the drain is connected to the source of the second P-type metal oxide semiconductor; The gate of the second P-type metal oxide semiconductor is connected to the output end of the sensitive amplifier module, and the drain is connected to the source of the first N-type metal oxide semiconductor; The gate of the first N-type metal oxide semiconductor is connected to the output end of the sense amplifier module, and the drain is connected to the source of the second N-type metal oxide semiconductor; The gate of the second N-type metal oxide semiconductor is used to input a clock signal, and the drain is a ground terminal.

5. The trigger according to claim 4, characterized in that: The output latch module further includes a first NOT gate; the input end of the first NOT gate is respectively connected to the drain of the second P-type metal oxide semiconductor and the source of the first N-type metal oxide semiconductor, and the output end serves as the output end of the trigger.

6. The trigger according to claim 5, characterized in that: The first latch module further includes a first latch unit; The first latch unit includes a third P-type metal oxide semiconductor, a fourth P-type metal oxide semiconductor, the first N-type metal oxide semiconductor and a third N-type metal oxide semiconductor; The source of the third P-type metal oxide semiconductor is connected to the drain of the first P-type metal oxide semiconductor, the gate is connected to the output end of the first NOT gate, and the drain is connected to the source of the fourth P-type metal oxide semiconductor; The gate of the fourth P-type metal oxide semiconductor is used to input a clock signal, and the drain is connected to the source of the first N-type metal oxide semiconductor; The source of the third N-type metal oxide semiconductor is connected to the drain of the first N-type metal oxide semiconductor, the gate is connected to the output end of the first NOT gate, and the drain serves as a ground terminal.

7. The trigger according to claim 6, characterized in that: The second latch module includes a second sampling unit; The second sampling unit includes a fifth P-type metal oxide semiconductor, a sixth P-type metal oxide semiconductor, a fourth N-type metal oxide semiconductor and a fifth N-type metal oxide semiconductor; The source of the fifth P-type metal oxide semiconductor is used to connect to a power source, the gate is connected to the first output terminal of the pulse generating module, and the drain is connected to the source of the sixth P-type metal oxide semiconductor; The gate of the sixth P-type metal oxide semiconductor is used to input scan input data, and the drain is respectively connected to the source of the fourth N-type metal oxide semiconductor and the input end of the first NOT gate; The gate of the fourth N-type metal oxide semiconductor is used to input scan input data, and the drain is connected to the source of the fifth N-type metal oxide semiconductor; The gate of the fifth N-type metal oxide semiconductor is connected to the second output terminal of the pulse generating module, and the drain serves as a ground terminal.

8. The trigger according to claim 7, characterized in that: The second latch module includes a second latch unit; The second latch unit includes a seventh P-type metal oxide semiconductor, an eighth P-type metal oxide semiconductor, a sixth N-type metal oxide semiconductor and a seventh N-type metal oxide semiconductor; The source of the seventh P-type metal oxide semiconductor is used to connect to a power source, the gate is connected to the output end of the first NOT gate, and the drain is connected to the source of the eighth P-type metal oxide semiconductor; The gate of the eighth P-type metal oxide semiconductor is connected to the second output terminal of the pulse generating module, and the drain is respectively connected to the source of the sixth N-type metal oxide semiconductor and the input terminal of the first NOT gate; The gate of the sixth N-type metal oxide semiconductor is connected to the output end of the first NOT gate, and the drain is connected to the source of the seventh N-type metal oxide semiconductor; The gate of the seventh N-type metal oxide semiconductor is connected to the first output terminal of the pulse generating module, and the drain serves as a ground terminal.

9. The trigger according to claim 8, characterized in that: The pulse generation module comprises: a NAND gate, a delay unit and a NOR gate; The first input terminal of the NAND gate is used to input a scan enable signal, and the second input terminal is used to input a clock signal; The delay unit includes an inverter and a buffer connected in cascade, and an input end is connected to the output end of the NAND gate, and is used to delay the signal output from the output end of the NAND gate; The first input end of the NOR gate is connected to the output end of the delay unit, and the second input end is connected to the output end of the NAND gate; the output end of the NOR gate serves as the second output end of the pulse generation module; The second NOT gate is connected to the output end of the NOR gate, and the output end of the NOT gate serves as the first output end of the pulse generating module.

10. The trigger according to claim 2, characterized in that: The sensitive amplifier module comprises: a sensitive amplifier module body and a level-pulling circuit; the control end of the level-pulling circuit is used to input a scan enable signal, and the power supply end is connected to the output end of the sensitive amplifier module body; The level-lowering circuit is used to lower the voltage outputted from the output end of the sense amplifier module body when the scan enable signal is at a high level, so that the second latch module samples the input data and outputs or latches it according to the pulse control signal.

11. The trigger according to claim 10, characterized in that: The sensitive amplifier module body includes: a differential input pair, a pre-charging unit and a sampling control circuit; The differential input pair includes an eighth N-type metal oxide semiconductor and a ninth N-type metal oxide semiconductor, the gate of the eighth N-type metal oxide semiconductor is used to receive a first state signal of input data, the gate of the ninth N-type metal oxide semiconductor is used to receive a second state signal of input data, and the first state signal and the second state signal are differential signals to each other; The pre-charging unit includes a first pre-charging circuit and a second pre-charging circuit; the first pre-charging circuit is connected to the source of the eighth N-type metal oxide semiconductor, and the second pre-charging circuit is connected to the source of the ninth N-type metal oxide semiconductor; the first pre-charging circuit is used to pre-charge the source of the eighth N-type metal oxide semiconductor when the clock signal is at a low level; the second pre-charging circuit is used to pre-charge the source of the ninth N-type metal oxide semiconductor when the clock signal is at a low level; The sampling control circuit comprises a first sampling control circuit and a second sampling control circuit, wherein the first sampling control circuit and the second sampling control circuit are connected; The first end of the first sampling control circuit is connected to the drain of the eighth N-type metal oxide semiconductor, and the second end is connected to the source of the eighth N-type metal oxide semiconductor; the first sampling control circuit is used to control the eighth N-type metal oxide semiconductor to be turned on when the clock signal is at a high level, so as to sample the first state signal of the input data, and output the sampled first state signal to the first latch module; The first end of the second sampling control circuit is connected to the drain of the ninth N-type metal oxide semiconductor, and the second end is connected to the source of the ninth N-type metal oxide semiconductor. The second sampling control circuit is used to control the ninth N-type metal oxide semiconductor to be turned on when the clock signal is at a high level, so as to adopt a second state signal for sampling the input data, and output the sampled second state signal to the first latch module.

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