Self-adaptive level circuit, chip and electronic equipment

Abstract

The invention provides a self-adaptive level circuit, a chip and an electronic device, the self-adaptive level circuit is applied to a first chip, and the first chip comprises at least two power supply ends; the adaptive level circuit comprises a level matching unit and at least two level control subunits; a level matching unit obtains a first level signal of a second chip communicating with the first chip through a first power supply end of the at least two power supply ends, the first level signal is compared with at least one second level signal of the at least one second power supply end, and a first control signal is generated, the second power supply end is the power supply end except the first power supply end in the at least two power supply ends; generating a target selection signal according to the first control signal, wherein the target selection signal is used for determining a target level control subunit from the at least two level control subunits; and the target level control subunit adjusts the level of the target level control subunit to a first level which is the same as that of the second chip according to the target selection signal.

Description

Technical Field

[0001] The present application belongs to the field of communication technology, and specifically relates to an adaptive level circuit, chip and electronic equipment. Background Art

[0002] At present, the power supply levels of each IC manufacturer are inconsistent during design. In actual application, they cannot be simply connected directly with wires, otherwise it will cause serious problems such as burning chips, leakage, data errors, etc.

[0003] The existing solution is to design an external circuit to connect between different chips so that level conversion can be achieved between different chips through the external circuit, which increases the size of the circuit board. Summary of the invention

[0004] The present application provides an adaptive level circuit, a chip and an electronic device, in order to add a level adaptation function to the chip.

[0005] In a first aspect, the present application provides an adaptive level circuit, which is applied to a first chip, wherein the first chip includes at least two power supply terminals; the adaptive level circuit includes a level matching unit and at least two level control subunits; The level matching unit obtains a first level signal of a second chip communicating with the first chip through a first power supply terminal of the at least two power supply terminals, compares the first level signal with at least one second level signal of at least one second power supply terminal, and generates a first control signal, wherein the second power supply terminal is a power supply terminal other than the first power supply terminal of the at least two power supply terminals; generates the target selection signal according to the first control signal, and the target selection signal is used to determine a target level control subunit from the at least two level control subunits; The target level control subunit adjusts its own level to the same first level as that of the second chip according to the target selection signal.

[0006] In combination with the first scheme, in one embodiment, the level matching unit includes a comparison subunit and at least two signal generating subunits; the comparison subunit includes at least two signal interfaces, the at least two signal interfaces are connected to the at least two power supply ends, and each signal interface is used to obtain a level signal; the comparison subunit obtains the first level signal from the first power supply end through the first signal interface of the at least two signal interfaces, and compares the first level signal with the at least one second level signal to generate the first control signal; the at least two signal generating subunits are matched with the first control signal respectively, and the target signal generating subunit that successfully matches among the at least two signal generating subunits generates the target selection signal according to the first control signal.

[0007] In combination with the first scheme, in one embodiment, the comparison subunit includes at least one comparator, which obtains a first level signal and at least one second level signal; the at least one comparator is used to perform at least one level comparison on the first level signal and the at least one second level signal to generate the first control signal.

[0008] In combination with the first scheme, in one embodiment, at least two signal generating subunits include a first signal generating subunit and a second signal generating subunit, and the first signal generating subunit and the second signal generating subunit are matched with the first control signal respectively. When the voltage of the first control signal is the same as the on-voltage of the first signal generating subunit, the first signal generating subunit generates the target selection signal according to the first control signal; when the voltage of the first control signal is the same as the on-voltage of the second signal generating subunit, the second signal generating subunit generates the target selection signal according to the first control signal.

[0009] In combination with the first scheme, in one embodiment, the first signal generating subunit includes a first switch tube, a second switch tube, a first resistor, a second resistor, a third resistor and a first capacitor: the controlled end of the first switch tube is connected to one end of the first resistor and the output end of the comparison subunit to access the first control signal; the input end of the first switch tube is connected to one end of the second resistor, one end of the third resistor and one end of the first capacitor, the other end of the second resistor, the other end of the first capacitor and the input end of the second switch tube are all connected to the first power supply, the other end of the third resistor is connected to the controlled end of the second switch tube, the output end of the second switch tube is connected to the communication bus, and the other end of the first resistor and the output end of the first switch tube are both grounded.

[0010] In combination with the first scheme, in one embodiment, the second signal generating subunit includes a third switch tube, a fourth resistor, a fifth resistor and a second capacitor; the controlled end of the first switch tube, one end of the fourth resistor, one end of the fifth resistor and one end of the second capacitor are all connected to the output end of the comparison subunit to access the first control signal; the other end of the fourth resistor, the other end of the second capacitor and the input end of the third switch tube are all connected to the second power supply, the other end of the fifth resistor is connected to the controlled end of the third switch tube, and the output end of the third switch tube is connected to the communication bus.

[0011] In combination with the first scheme, in one embodiment, the levels between the at least two level control subunits are different; the at least two level control subunits are connected to the at least two signal generating subunits in a one-to-one correspondence to obtain a target selection signal from the corresponding signal generating subunit; when the target level control subunit among the at least two level control subunits receives the target selection signal, the level of the first chip is adjusted to the same first level as the second chip according to the target selection signal.

[0012] In combination with the first scheme, in one embodiment, the target selection signal includes a first selection signal and a second selection signal; the at least two level control subunits include a first level control subunit and a second level control subunit; the first level control subunit includes a fourth switch tube, a fifth switch tube, a sixth resistor and a seventh resistor; the second level control subunit includes an eighth resistor and a ninth resistor; the data bus includes a first segment data bus and a second segment data bus, and the clock bus includes a first segment clock bus and a second segment clock bus; the first end of the sixth resistor and the first end of the seventh resistor are both connected to the first selection signal, and the other end of the sixth resistor is connected to the controlled end of the fourth switch tube; the input end and the output end of the fourth switch tube are respectively connected to the first segment data bus and the second segment data bus; the other end of the seventh resistor is connected to the controlled end of the fifth switch tube; the input end and the output end of the fifth switch tube are respectively connected to the first segment clock bus and the second segment clock bus; one end of the eighth resistor and one end of the ninth resistor are both connected to the first selection signal, the other end of the eighth resistor is connected to the first segment data bus, and the other end of the ninth resistor is connected to the first segment clock bus.

[0013] In a second aspect, the present application provides a chip, comprising the adaptive level circuit as described in the first aspect.

[0014] In a third aspect, the present application provides an electronic device, comprising the adaptive level circuit as described in the first aspect, or comprising the chip as described in the second aspect.

[0015] It can be seen that in the present application, the adaptive level circuit is applied to the first chip, and the first chip includes at least two power supply terminals; the adaptive level circuit includes a level matching unit and at least two level control subunits; the level matching unit obtains the first level signal of the second chip communicating with the first chip through the first power supply terminal of the at least two power supply terminals, compares the first level signal with at least one second level signal of at least one second power supply terminal, and generates a first control signal, wherein the second power supply terminal is a power supply terminal other than the first power supply terminal of the at least two power supply terminals; generates a target selection signal according to the first control signal, and the target selection signal is used to determine the target level control subunit from at least two level control subunits; the target level control subunit adjusts its own level to the same first level as the second chip according to the target selection signal. In this way, the chip can be provided with a level adaptive function, so that the chip can automatically adjust its own level to the same level as other chips in the communication, and no additional external circuit needs to be designed for assistance, and the circuit board size is reduced while realizing the level adaptive function. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 is a connection diagram of the first chip and the second chip communicating with each other provided in an embodiment of the present application; Figure 2 This is a schematic diagram of the first structure of the adaptive level circuit provided in the embodiment of the present application; Figure 3 is a second structural schematic diagram of the adaptive level circuit provided in an embodiment of the present application; Figure 4 is a first circuit diagram of a comparison subunit provided in an embodiment of the present application; Figure 5 is a second circuit diagram of a comparison subunit provided in an embodiment of the present application; Figure 6 is a third circuit diagram of the comparison subunit provided in the embodiment of the present application; Figure 7 is a circuit diagram of a first signal generating subunit provided in an embodiment of the present application; Figure 8 is a circuit diagram of a second signal generating subunit provided in an embodiment of the present application; Fig. 9is a circuit diagram of a first level control subunit and a second level control subunit provided in an embodiment of the present application; Fig.10 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, systems, products or devices.

[0020] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0021] At present, the power supply level of each IC manufacturer is inconsistent during design. In actual application, it cannot be simply connected directly with wires, otherwise it will cause serious problems such as chip burning, leakage, data errors, etc. The existing solution is to design external circuits to connect different chips so that different chips can achieve level conversion through the external circuit, which increases the size of the circuit board.

[0022] To solve the above problems, an embodiment of the present application provides an adaptive level circuit. The adaptive level circuit can be applied to the scenario of adaptive level matching between chips. The level matching unit can obtain the first level signal of the second chip communicating with the first chip through the first power supply terminal of at least two power supply terminals, compare the first level signal with at least one second level signal of at least one second power supply terminal, and generate a first control signal, wherein the second power supply terminal is a power supply terminal other than the first power supply terminal of at least two power supply terminals; generate a target selection signal according to the first control signal, and the target selection signal is used to determine the target level control subunit from at least two level control subunits; the target level control subunit adjusts its own level to the same first level as the second chip according to the target selection signal. In this way, the chip can be provided with a level adaptive function, so that the chip can automatically adjust its own level to the same as other chips in the communication, and there is no need to design additional external circuits for assistance, while realizing the level adaptive function and reducing the size of the circuit board. This solution can be applied to a variety of scenarios, including but not limited to the application scenarios mentioned above.

[0023] The following introduces the system architecture involved in the embodiments of the present application.

[0024] IIC (Inter-Integrated Circuit, also known as I2C or I²C) is a simple and flexible serial communication protocol used to connect microcontrollers and external devices such as sensors, memory, displays, etc.

[0025] Rationale Two-wire system: I2C uses two wires for communication: serial data line (SDA) and serial clock line (SCL). The data on the SDA line is transmitted synchronously under the clock signal of the SCL line.

[0026] Master-slave structure: In I2C communication, devices are divided into master devices (usually microcontrollers) and slave devices (such as sensors or memories). The master device is responsible for initiating communication and controlling the timing of communication, while the slave device responds to the instructions of the master device.

[0027] Address addressing: Each I2C device has a unique 7-bit or 10-bit address. The master device selects the communication object by sending the address of the target device.

[0028] Communication Process Start condition (Start): The master device sends a start signal, that is, the SDA line changes from high level to low level, while the SCL line remains in the high level state.

[0029] Send address and read / write bit: The master device sends the address of the target device and specifies whether to read or write data.

[0030] Address Confirmation (ACK): After receiving the address, the slave device will send an acknowledgement signal (ACK) to indicate that it is ready to communicate with the master device.

[0031] Data Transfer: The master or slave sends or receives data bits on the edges of the SCL clock signal.

[0032] Stop condition (Stop): The master device sends a stop signal, that is, the SDA line changes from low level to high level, while the SCL line remains in the high level state.

[0033] advantage Bidirectional communication (half-duplex): I2C supports the master device to send data to the slave device, and supports the slave device to send data to the master device, with bidirectional communication capability.

[0034] Multi-device connection: The I2C bus supports multiple devices connected to the same bus, and the communication partner can be selected by the device address.

[0035] Application Areas Sensor Interface: Many sensors like temperature sensor, humidity sensor, accelerometer etc. use I2C interface to communicate with microcontroller.

[0036] The specific methods are introduced in detail below.

[0037] See also Figures 1 to 3The present application also provides an adaptive level circuit, which is applied to a first chip IC1, wherein the first chip IC1 includes at least two power supply terminals; the adaptive level circuit includes a level matching unit 210 and at least two level control subunits 220; the at least two power supply terminals include a first power supply terminal VCC1 and at least one second power supply terminal VCC2, the first power supply terminal VCC1 and at least one second power supply terminal VCC2 are respectively connected to the level matching unit 210, and the output terminal of the level matching unit 210 is respectively connected to the at least two level control subunits 220; the level matching unit 210 obtains the first power supply terminal VCC1 of the at least two power supply terminals to communicate with the first chip IC1 The first level signal VCC_01 of the second chip IC2 is received by the first control signal CTR1, and the first level signal VCC_01 is compared with at least one second level signal VCC_02 of at least one second power supply terminal VCC2 to generate a first control signal CTR1, wherein the second power supply terminal VCC2 is a power supply terminal other than the first power supply terminal VCC1 among the at least two power supply terminals; the target selection signal is generated according to the first control signal CTR1, and the target selection signal is used to determine a target level control subunit from the at least two level control subunits 220; the target level control subunit adjusts its own level to the same first level as the second chip IC2 according to the target selection signal.

[0038] In a specific implementation, the adaptive level circuit is integrated in the first chip IC1. When the first chip IC1 communicates with the second chip IC2, the first power supply terminal VCC1 of at least two power supply terminals on the first chip IC1 having the same power supply level as the second chip IC2 will obtain the first level signal VCC_01 of the second chip IC2, and then transmit it to the level matching unit 210.

[0039] If no other chip is connected, at least one second power supply terminal VCC2 other than the first power supply terminal VCC1 among the at least two power supply terminals is left floating, that is, the second level signal VCC_02 is 0; the level matching unit 210 compares the first level signal VCC_01 with the 0 level, and outputs the first control signal CTR1 that is the same as the first level signal VCC_01.

[0040] If the second power supply terminal VCC2 is also connected to other chips (for example, the third chip), then the level signal that the second power supply terminal VCC2 is connected to other chips is obtained, and the second level signal VCC_02 is greater than 0; the first level signal VCC_01 is compared with the second level signal VCC_02 by the level matching unit 210; if the first level signal VCC_01 is greater than the second level signal VCC_02, the first control signal CTR1 that is the same as the first level signal VCC_01 is output; if the first level signal VCC_01 is less than the second level signal VCC_02, the first control signal CTR1 that is the same as the second level signal VCC_02 is output.

[0041] It is understandable that there can be multiple second power supply terminals VCC2 to obtain multiple second level signals VCC_02, and the first level signal VCC_01 is compared with multiple second level signals VCC_02 for multiple times, and finally the first level signal VCC_01 and the multiple second level signals VCC_02 with the largest level are output to obtain the first control signal CTR1. The first level signal is essentially the power supply voltage of the second chip, and the second level signal is essentially the power supply voltage of the third chip and other chips connected to the communication bus; therefore, it is understandable that the first level signal and the second level signal can be 1.8V (such as Figure 1 VCC_1V8) can also be 3.3V (such as Figure 1 The VCC_3V3), or the voltage value, Figure 1 This is just one of them and is not limited here.

[0042] Further, the first chip further includes a data port SDA and a clock port SCL, the data port is connected to the data bus IC1_SDA, and the clock port is connected to the clock bus IC1_SCL. After obtaining the first control signal CTR1, a target selection signal is generated by the first control signal CTR1 to determine a target level control subunit from at least two level control subunits 220, and the target level control subunit is controlled accordingly to adjust the level of the first chip IC1 to the same first level as the second chip IC2.

[0043] It can be seen that in this embodiment, the level matching unit 210 obtains the first level signal VCC_01 of the second chip IC2 communicating with the first chip IC1 through the first power supply terminal VCC1 of at least two power supply terminals, compares the first level signal VCC_01 with at least one second level signal VCC_02 of at least one second power supply terminal VCC2, and generates a first control signal CTR1, wherein the second power supply terminal VCC2 is a power supply terminal other than the first power supply terminal VCC1 of at least two power supply terminals; generates a target selection signal according to the first control signal CTR1, and the target selection signal is used to determine a target level control subunit from at least two level control subunits 220; and the target level control subunit adjusts its own level to the same first level as the second chip IC2 according to the target selection signal. In this way, the chip can be provided with a level adaptation function, so that the chip can automatically adjust its own level to the same level as other chips in communication, and no additional external circuit needs to be designed for assistance, thereby reducing the size of the circuit board while realizing the level adaptation function.

[0044] For an example, see Figure 3 The level matching unit 210 includes a comparison subunit 211 and at least two signal generating subunits 212; the comparison subunit 211 includes at least two signal interfaces; the at least two signal interfaces include a first signal interface P1 and at least one second signal interface P2, the first power supply terminal VCC1 is connected to the first signal interface P1, the at least one second power supply terminal VCC2 is connected to the at least one second signal interface P2 in a one-to-one correspondence, the output end of the comparison subunit is connected to the control end of the at least two signal generating subunits, the at least two signal generating subunits are connected to the at least two level control subunits in a one-to-one correspondence, and the at least two signal generating subunits are connected in series on the communication bus.

[0045] The comparing subunit 211 obtains the first level signal VCC_01 from the first power supply terminal VCC1 through the first signal interface P1 among the at least two signal interfaces, and compares the first level signal VCC_01 with the at least one second level signal VCC_02 to generate the first control signal CTR1; the at least two signal generating subunits 212 respectively match the first control signal CTR1, and the target signal generating subunit that successfully matches among the at least two signal generating subunits 212 generates the target selection signal according to the first control signal CTR1.

[0046] In a specific implementation, at least two signal interfaces of the comparison subunit 211 are connected to at least two power supply terminals of the first chip IC1 in a one-to-one correspondence, and the first signal interface P1 of the at least two signal interfaces obtains the first level signal VCC_01 of the first power supply terminal VCC1, while the other signal interface (which can be recorded as the second signal interface P2) obtains the second level signal VCC_02 through the second power supply terminal VCC2. Then, the comparison subunit 211 compares the first level signal VCC_01 with the second level signal VCC_02 to generate a first control signal CTR1, and outputs the first control signal CTR1 to at least two signal generation subunits 212, which are matched with the first control signal CTR1; if the on-voltage of a certain signal generation subunit 212 is the same as the first control signal CTR1, the signal generation subunit 212 is determined to be a target signal generation subunit, and the target signal generation subunit is turned on under the control of the first control signal CTR1 and generates a target selection signal, which is output to the corresponding level control subunit 220.

[0047] For details, please refer to Figure 4-Figure 6 The comparison subunit includes at least one comparator, which obtains a first level signal VCC_01 and at least one second level signal VCC_02; the at least one comparator is used to perform at least one level comparison on the first level signal VCC_01 and the at least one second level signal VCC_02 to generate the first control signal CTR1.

[0048] Optional, see Figure 4 When the comparison subunit 211 includes a comparator (ie, the first comparator U1A), the comparator obtains the first level signal VCC_01 and the second level signal VCC_02 for comparison to generate the first control signal CTR1.

[0049] See also Figure 5 and Figure 6 When the comparison subunit 211 includes multiple comparators, the multiple comparators are combined to form a multi-stage comparator, and the multi-stage comparator can compare the first level signal VCC_01 with multiple second level signals VCC_02 to obtain the first control signal CTR1.

[0050] The case of multiple comparators is described by taking two comparators and three comparators as examples.

[0051] See also Figure 5When the comparison subunit 211 includes two comparators, they are respectively recorded as the first comparator U1A and the second comparator U2A. The first input end of the first comparator U1A is the first signal interface P1, which is used to access the first level signal VCC_01; the output end of the first comparator U1A is connected to the first input end of the second comparator U2A; the second input end of the first comparator U1A and the second input end of the second comparator U2A are both the second signal interface P2, which can access the corresponding second level signal VCC_02 (the second level signal VCC_02 can be left floating at 0, or it can be the level signal of other chips except the first chip IC1 and the second chip IC2), and the output end of the second comparator U2A is respectively connected to at least two signal generation subunits 212.

[0052] Specifically, the first comparator U1A first compares the first level signal VCC_01 with the second level signal VCC_02 connected to the second input terminal of the first comparator U1A, outputs the largest level signal therebetween as the first signal to be compared OUT1, and outputs the first signal to be compared OUT1 to the first input terminal of the second comparator U2A; then the second comparator U2A compares the connected second level signal VCC_02 with the first signal to be compared OUT1, obtains the largest level signal therebetween as the first control signal CTR1, and outputs the first control signal CTR1 to at least two signal generating sub-units 212 through the second comparator U2A.

[0053] See also Figure 6 When the comparison subunit 211 includes three comparators, they are respectively recorded as the first comparator U1A, the second comparator U2A and the third comparator U3A. The first input end of the first comparator U1A is the first signal interface P1, which is used to access the first level signal VCC_01; the second input end of the first comparator U1A and the first input end and the second input end of the second comparator U2A are both the second signal interface P2, which can access the corresponding second level signal VCC_02 (the second level signal VCC_02 can be left floating at 0, or it can be a level signal of other chips except the first chip IC1 and the second chip IC2); the output end of the first comparator U1A is connected to the first input end of the third comparator U3A, the output end of the second comparator U2A is connected to the second input end of the third comparator U3A, and the output end of the third comparator U3A is respectively connected to at least two signal generation subunits 212.

[0054] Specifically, the first comparator U1A first compares the first level signal VCC_01 with the second level signal VCC_02 connected to the second input terminal of the first comparator U1A, outputs the largest level signal therebetween as the first signal to be compared OUT1, and outputs the first signal to be compared OUT1 to the first input terminal of the third comparator U3A; then the second comparator U2A compares the two connected second level signals VCC_02, outputs the largest level signal therebetween as the second signal to be compared OUT2, and outputs the second signal to be compared OUT2 to the second input terminal of the third comparator U3A; finally, the third comparator U3A compares the first signal to be compared OUT1 with the second signal to be compared OUT2, obtains the largest level signal therebetween as the first control signal CTR1, and outputs the first control signal CTR1 to at least two signal generating sub-units 212 through the third comparator U3A.

[0055] It is understandable that at least two signal generating subunits 212 need to be set, corresponding to at least two different levels, so that level matching and level adjustment are necessary. The following example of two signal generating subunits 212 is used to illustrate the working principle of at least two signal generating subunits 212 in this application.

[0056] In one possible embodiment, please refer to Figure 3 , at least two signal generating subunits 212 include a first signal generating subunit and a second signal generating subunit, the first signal generating subunit and the second signal generating subunit are matched with the first control signal CTR1 respectively, when the voltage of the first control signal CTR1 is the same as the turn-on voltage of the first signal generating subunit, the first signal generating subunit generates the target selection signal according to the first control signal CTR1; when the voltage of the first control signal CTR1 is the same as the turn-on voltage of the second signal generating subunit, the second signal generating subunit generates the target selection signal according to the first control signal CTR1.

[0057] For details, please refer to Figure 7, the first signal generating subunit includes a first switch tube Q1, a second switch tube Q2, a first resistor R1, a second resistor R2, a third resistor R3 and a first capacitor C1: the controlled end of the first switch tube Q1 is connected to one end of the first resistor R1 and the output end of the comparison subunit 211 to access the first control signal CTR1; the input end of the first switch tube Q1 is connected to one end of the second resistor R2, one end of the third resistor R3 and one end of the first capacitor C1, the other end of the second resistor R2, the other end of the first capacitor C1 and the input end of the second switch tube Q2 are all connected to the first power supply, the other end of the third resistor R3 is connected to the controlled end of the second switch tube Q2, the output end of the second switch tube Q2 is connected to the communication bus, and the other end of the first resistor R1 and the output end of the first switch tube Q1 are both grounded. Please refer to Figure 8 The second signal generating subunit includes a third switch tube Q3, a fourth resistor R4, a fifth resistor R5 and a second capacitor C2; one end of the fourth resistor R4, one end of the fifth resistor R5 and one end of the second capacitor C2 are all connected to the output end of the comparison subunit 211 to access the first control signal CTR1; the other end of the fourth resistor R4, the other end of the second capacitor C2 and the input end of the third switch tube Q3 are all connected to the second power supply; the other end of the fifth resistor R5 is connected to the controlled end of the third switch tube Q3, and the output end of the third switch tube Q3 is connected to the communication bus.

[0058] In a specific implementation, the turn-on voltages of the first switch tube Q1 and the third switch tube Q3 are different. When the comparison subunit 211 outputs the first control signal CTR1, the controlled end of the first switch tube Q1 and the controlled end of the third switch tube Q3 simultaneously receive the first control signal CTR1; at this time, if the voltage of the first control signal CTR1 satisfies the turn-on voltage of the first switch tube Q1, the first switch tube Q1 will be driven to turn on, thereby turning on the second switch tube Q2, and the first voltage of the first power supply will be output as the target selection signal to the corresponding level control subunit 220. If the voltage of the first control signal CTR1 satisfies the turn-on voltage of the third switch tube Q3, the third switch tube Q3 will be driven to turn on, thereby outputting the second voltage of the second power supply as the target selection signal to the corresponding level control subunit 220. Among them, the first voltage can be 1.8V, and the second voltage can be 3.3V. It can be understood that the voltage values ​​of the first voltage and the second voltage can be selected according to actual conditions, which are only explained here without specific limitation.

[0059] It is understandable that the number of signal generation subunits 212 can be more than two, and can be set according to the number of voltages to be adapted. For example, if three levels of 1.8V, 3.3V and 5V need to be adapted, three signal generation subunits 212 can be set to adapt to the three levels. Similarly, if more levels need to be adapted, more signal generation subunits 212 can be set, which is not limited here.

[0060] It can be seen that in this embodiment, the level of the second chip IC2 can be automatically matched by the signal generating subunit 212, which improves the intelligence of the signal generating subunit 212 and improves the reliability of the adaptive level circuit.

[0061] The technical solution of the present application is described below using the IIC bus as an example. It can be understood that the solution of the present application can also be applied to other bus or chip communication scenarios. IIC is only used to explain the solution and is not limited here.

[0062] In one possible embodiment, see Figure 3 and Fig. 9 , the levels of the at least two level control subunits 220 are different; the at least two level control subunits 220 are connected to the at least two signal generating subunits 212 in a one-to-one correspondence to obtain the target selection signal from the corresponding signal generating subunit 212; when the target level control subunit in the at least two level control subunits 220 receives the target selection signal, the level of the first chip IC1 is adjusted to the same first level as the second chip IC2 according to the target selection signal.

[0063] Specifically, the target selection signal includes a first selection signal OUT3 and a second selection signal OUT4; the at least two level control subunits 220 include a first level control subunit 221 and a second level control subunit 222; the first level control subunit 221 includes a fourth switch tube Q4, a fifth switch tube Q5, a sixth resistor R6 and a seventh resistor R7; the second level control subunit 222 includes an eighth resistor R8 and a ninth resistor R9; the data bus includes a first segment data bus IC1_SDA and a second segment data bus IC2_SDA, and the clock bus includes a first segment clock bus IC1_SCL and a second segment clock bus IC2_SCL; the first end of the sixth resistor R6 and the first end of the seventh resistor R7 are both connected to the first selection signal OUT3 , the other end of the sixth resistor R6 is connected to the controlled end of the fourth switch tube Q4; the input end and the output end of the fourth switch tube Q4 are respectively connected to the first segment data bus IC1_SDA and the second segment data bus IC2_SDA; the other end of the seventh resistor R7 is connected to the controlled end of the fifth switch tube Q5; the input end and the output end of the fifth switch tube Q5 are respectively connected to the first segment clock bus IC1_SCL and the second segment clock bus IC2_SCL; one end of the eighth resistor R8 and one end of the ninth resistor R9 are both connected to the second selection signal OUT4, the other end of the eighth resistor R8 is connected to the first segment data bus IC1_SDA, and the other end of the ninth resistor R9 is connected to the first segment clock bus IC1_SCL.

[0064] In a specific implementation, the number of the level control subunits 220 is consistent with the number of the signal generation subunits 212, that is, at least two level control subunits 220 are connected to at least two signal generation subunits 212 in a one-to-one correspondence. Taking two level control subunits 220 as an example, the first level control subunit 221 is connected to the first signal generation subunit, and the second level control subunit 222 is connected to the second signal generation subunit. When the first signal generation subunit generates a target selection signal, the first level control subunit 221 obtains the target selection signal, and turns on the fourth switch tube Q4 according to the target selection signal to pull up the data sum clock bus to the first voltage, so that the communication bus between the first chip IC1 and the second chip IC2 is the first level. When the second signal generation subunit generates a target selection signal, the second level control subunit 222 obtains the target selection signal, and turns on the fifth switch tube Q5 according to the target selection signal to pull up the data bus and the clock bus to the second voltage, so that the communication bus between the first chip IC1 and the second chip IC2 is the first level.

[0065] It can be seen that in this embodiment, based on the control of the target selection signal, the level of the first chip IC1 can be adjusted to the first level of the second chip IC2 communicating therewith, and at least two level control subunits 220 correspond to different levels respectively, thereby improving the isolation of the level adjustment.

[0066] In a possible embodiment, the level matching unit 210 may be a data processing unit inside the first chip IC1, which obtains a first level signal VCC_01 of a second chip IC2 communicating with the first chip IC1 through a first power supply terminal VCC1 of the at least two power supply terminals, compares the first level signal VCC_01 with at least one second level signal VCC_02 of at least one second power supply terminal VCC2, and generates a first control signal CTR1; generates the target selection signal according to the first control signal CTR1, and the target selection signal is used to determine a target level control subunit from the at least two level control subunits 220; and the target level control subunit adjusts its own level to the same first level as that of the second chip IC2 according to the target selection signal.

[0067] Further, when the level matching unit is the data processing unit, during the communication process, after the level adjustment of the first chip IC1 is completed, the first level is monitored. The first level is continuously collected to obtain a set of sampling signals to form a first sampling signal set, and an autocorrelation function is calculated based on the first sampling signal set to obtain multiple similarity values. For two adjacent similarity values, if the currently calculated similarity value is the same as the previously calculated similarity value, it is determined that the first chip IC1 is still communicating with the second chip IC2, and if the autocorrelation function value becomes smaller, it is determined that the level has changed.

[0068] In order to avoid the level fluctuation from falsely triggering the shutdown mechanism of the data processing unit for the signal generation subunit 212, the calculated multiple similarity values ​​are statistically analyzed to determine the proportion of the similarity values ​​equal to the first similarity value in the multiple similarity values. After comparing the proportion with the preset value, it is determined whether to trigger the shutdown mechanism to improve the accuracy of the shutdown mechanism triggering. If the proportion is less than the preset value, the shutdown mechanism is triggered, the target selection signal is stopped from being output to the target level control subunit, the new first level signal VCC_01 is re-acquired for corresponding level matching processing, a new target selection signal is obtained, and then the new target selection signal is output to the target level control subunit, and the monitoring of the first level is entered again, and the cycle is carried out as an example. If the proportion is greater than or equal to the preset value, the sampling of the next cycle is continued to be performed to calculate the new proportion to determine whether the shutdown mechanism needs to be triggered in the next cycle.

[0069] In addition, the level matching unit may also include a comparison subunit, at least two signal generation subunits 212 and the data processing unit at the same time, and the data processing unit is connected to the at least two signal generation subunits 212 respectively to control the switch of the at least two signal generation subunits 212; at the same time, the data processing unit is also connected to the communication bus or the first signal interface P1 of the comparison subunit to detect the first level. Specifically, during the communication process, after the level adjustment of the first chip IC1 is completed, the data processing unit acquires and monitors the first level. The data processing unit collects the first level to obtain a first sampling signal set; calculates the autocorrelation function according to the first sampling signal set to obtain multiple similarity values; determines the proportion of similarity values ​​equal to the first similarity value in the multiple similarity values; wherein the first similarity value is the first similarity value calculated in the multiple similarity values; if the proportion is greater than the preset value, a shutdown signal is sent to the target signal generation subunit to control the target signal generation subunit to shut down.

[0070] In a specific implementation, the first level is continuously collected to obtain a group of sampling signals to form a first sampling signal set, and an autocorrelation function is calculated based on the first sampling signal set to obtain multiple similarity values. For two adjacent similarity values, if the currently calculated similarity value is the same as the previously calculated similarity value, it is determined that the first chip IC1 is still communicating with the second chip IC2, and if the autocorrelation function value becomes smaller, it is determined that the level has changed. In order to avoid the level fluctuation from falsely triggering the shutdown mechanism of the data processing unit for the signal generation subunit 212, the multiple similarity values ​​calculated are counted, and the proportion of the similarity values ​​equal to the first similarity value in the multiple similarity values ​​is determined. After comparing the proportion with the preset value, it is determined whether to trigger the shutdown mechanism to improve the accuracy of the shutdown mechanism triggering. If the proportion is less than the preset value, the shutdown mechanism is triggered, the target selection signal is stopped from being output to the target level control subunit, and the new first level signal VCC_01 is re-acquired for corresponding level matching processing to obtain a new target selection signal, and then the new target selection signal is output to the target level control subunit, and the monitoring of the first level is entered again, and the cycle is carried out as an example. If the proportion is greater than or equal to the preset value, the sampling of the next cycle is continued to be performed to calculate a new proportion to determine whether the shutdown mechanism needs to be triggered in the next cycle.

[0071] Specifically, the calculation process of the similarity value is as follows: For a set of sampled signals collected , autocorrelation function Defined as: , where t is the sampling interval and T is the current time; The collected set of sampled signals The initial sampling signal in and the next moment Integrate to get a similarity value; then continue to let = , and then With the next moment Integrate and obtain the next similarity value, and so on, until each sampling signal in the group of sampling signals is calculated. The proportion of equal autocorrelation function values ​​between the calculated multiple autocorrelation function values ​​is calculated. If the proportion is greater than the preset value, it is determined that the level has changed. If the proportion is less than or equal to the preset value, it is determined that the level has not changed.

[0072] It can be seen that in this embodiment, the data processing unit samples the first level to obtain a sampling value, and calculates the autocorrelation function of two sampling values ​​of adjacent power supply cycles, and determines whether the first level has changed based on the calculated autocorrelation function, thereby avoiding repeated level comparison and calculation of the target selection signal when no change occurs, thereby reducing the calculation amount of the data processing unit.

[0073] The present application also provides a chip, including the above-mentioned adaptive level circuit. Specifically, the chip in this embodiment can be the above-mentioned first chip, and the first chip can be a main control chip of a master device, or a slave control chip in a slave device, or a communication chip used for communication, which is not limited here. When the first chip is a master control chip, the connected second chip and other chips are all slave control chips; when the first chip is a slave control chip, the connected second chip and other chips include a master control chip and a slave control chip.

[0074] When the adaptive level circuit is applied to the master chip, the level matching unit obtains at least one first level signal of at least one slave chip, and generates a first selection signal according to the at least one first level signal; the level control unit adjusts its own level to the same first level as that of the target chip according to the first selection signal, and the target chip is one of the at least one slave chip; When the adaptive level circuit is applied to a slave chip, the level matching unit obtains the second level signal of the master chip and generates a second selection signal according to the second level signal; the level control unit adjusts its own level to the same second level as the master chip or the slave chip according to the second selection signal.

[0075] It can be seen that in this embodiment, a level adaptation function can be provided for the chip, so that the chip can automatically adjust its own level to be the same as other chips in the communication, and there is no need to design additional external circuits for assistance, thereby reducing the size of the circuit board while realizing the level adaptation function.

[0076] The present application also provides an electronic device, including the above-mentioned adaptive level circuit, or including the above-mentioned chip.

[0077] like Fig.10 As shown, the electronic device 10 includes at least one processor 11; a display screen 12; and a memory 13, and may also include a communications interface 15 and a bus 14. The processor 11, the display screen 12, the memory 13 and the communications interface 15 can communicate with each other through the bus 14. The display screen 12 is configured to display a preset user guide interface in the initial setting mode. The communication interface 15 can transmit information. The processor 11 can call the logic instructions in the memory 13 to execute the method in the above embodiment. It can be understood that the processor can be the first chip IC1 mentioned above.

[0078] Optionally, the electronic device 10 may be a mobile electronic device, or an electronic device or other device, which is not limited to any particular device.

[0079] In addition, the logic instructions in the memory 13 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0080] The memory 13, as a computer-readable storage medium, can be configured to store software programs, computer executable programs, such as program instructions or modules corresponding to the methods in the embodiments of the present disclosure. The processor 11 executes functional applications and data processing by running the software programs, instructions or modules stored in the memory 13, that is, implementing the methods in the above embodiments.

[0081] The memory 13 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and at least one application required for a function; the data storage area may store data created according to the use of the electronic device 10, etc. In addition, the memory 13 may include a high-speed random access memory and may also include a non-volatile memory. For example, a variety of media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, may also be a transient storage medium.

[0082] An embodiment of the present application also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute part or all of the steps of any method described in the above method embodiments, and the above computer includes an electronic device.

[0083] The embodiment of the present application also provides a computer program product, the computer program product includes a non-transitory computer-readable storage medium storing a computer program, the computer program is operable to cause a computer to execute some or all of the steps of any method described in the method embodiment. The computer program product may be a software installation package, and the computer includes an electronic device.

[0084] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0085] In the several embodiments provided in the present application, it should be understood that the disclosed methods, devices and systems can be implemented in other ways. For example, the device embodiments described above are merely schematic; for example, the division of the units is only a logical function division, and there may be other division methods in actual implementation; for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0086] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0087] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0088] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform some steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a volatile memory or a non-volatile memory. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM) and direct RAM bus RAM (DR RAM). Various media that can store program code are available.

[0089] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions without departing from the spirit and scope of the present invention, and can make various changes and modifications, including the combination of the above-mentioned different functions and implementation steps, including software and hardware implementation methods, all of which are within the scope of protection of the present invention.

Claims

1. An adaptive level circuit, characterized in that: Applied to a first chip, the first chip includes at least two power supply terminals; the adaptive level circuit includes a comparison subunit, at least two signal generation subunits and at least two level control subunits; the comparison subunit includes at least two signal interfaces; The at least two power supply terminals include a first power supply terminal and at least one second power supply terminal, the at least two signal interfaces include a first signal interface and at least one second signal interface, the first power supply terminal is connected to the first signal interface, the at least one second power supply terminal is connected to the at least one second signal interface in a one-to-one correspondence, the output terminal of the comparison subunit is connected to the control terminal of the at least two signal generation subunits, the at least two signal generation subunits are connected to the at least two level control subunits in a one-to-one correspondence, and the at least two signal generation subunits are connected in series on the communication bus; The first chip acquires a first level signal of a second chip communicating with the first chip through the first power supply terminal, and transmits the first level signal to the comparison subunit through the first signal interface; The comparison subunit compares the first level signal with at least one second level signal of at least one second power supply terminal to generate a first control signal, wherein the second power supply terminal is a power supply terminal other than the first power supply terminal among the at least two power supply terminals; the at least one second level signal includes a level signal of at least one third chip, or includes at least one zero level signal; the second chip and at least one third chip are both connected to the communication bus of the first chip; The at least two signal generating subunits are matched with the first control signal respectively, and a target signal generating subunit that successfully matches among the at least two signal generating subunits generates a target selection signal according to the first control signal, wherein the target selection signal is used to determine a target level control subunit from the at least two level control subunits; The target level control subunit adjusts its own level to the same first level as that of the second chip according to the target selection signal.

2. The adaptive level circuit according to claim 1, characterized in that: It also includes a data processing unit, the data processing unit is respectively connected to the at least two signal generating subunits, and connected to the communication bus or the first signal interface of the comparing subunit; The data processing unit collects the first level to obtain a first sampling signal set; Calculating an autocorrelation function according to the first sampling signal set to obtain a plurality of similarity values; Determine the proportion of similarity values ​​in the multiple similarity values ​​that are equal to the first similarity value; wherein the first similarity value is the first calculated similarity value in the multiple similarity values; If the proportion is less than a preset value, a shutdown signal is sent to the target signal generating subunit to control the target signal generating subunit to be shut down.

3. The adaptive level circuit according to claim 1, characterized in that: The comparison subunit includes at least one comparator, which obtains a first level signal and at least one second level signal; the at least one comparator is used to perform at least one level comparison on the first level signal and the at least one second level signal to generate the first control signal.

4. The adaptive level circuit according to claim 1, characterized in that: The at least two signal generating subunits include a first signal generating subunit and a second signal generating subunit, The first signal generating subunit and the second signal generating subunit are matched with the first control signal respectively. When the voltage of the first control signal is the same as the on-voltage of the first signal generating subunit, the first signal generating subunit generates the target selection signal according to the first control signal; when the voltage of the first control signal is the same as the on-voltage of the second signal generating subunit, the second signal generating subunit generates the target selection signal according to the first control signal.

5. The adaptive level circuit according to claim 4, characterized in that: The first signal generating subunit includes a first switch tube, a second switch tube, a first resistor, a second resistor, a third resistor and a first capacitor: The controlled end of the first switch tube is connected to one end of the first resistor and the output end of the comparison subunit to access the first control signal; the input end of the first switch tube is connected to one end of the second resistor, one end of the third resistor and one end of the first capacitor, the other end of the second resistor, the other end of the first capacitor and the input end of the second switch tube are all connected to the first power supply, the other end of the third resistor is connected to the controlled end of the second switch tube, the output end of the second switch tube is connected to the communication bus, and the other end of the first resistor and the output end of the first switch tube are both grounded.

6. The adaptive level circuit according to claim 4, characterized in that: The second signal generating subunit includes a third switch tube, a fourth resistor, a fifth resistor and a second capacitor; The controlled end of the third switch tube, one end of the fourth resistor, one end of the fifth resistor and one end of the second capacitor are all connected to the output end of the comparison subunit to access the first control signal; The other end of the fourth resistor, the other end of the second capacitor and the input end of the third switch tube are all connected to the second power supply, the other end of the fifth resistor is connected to the controlled end of the third switch tube, and the output end of the third switch tube is connected to the communication bus.

7. The adaptive level circuit according to any one of claims 2 to 6, characterized in that: The levels of the at least two level control subunits are different; the at least two level control subunits are connected to the at least two signal generation subunits in a one-to-one correspondence to obtain the target selection signal from the corresponding signal generation subunit; When the target level control subunit of the at least two level control subunits receives the target selection signal, the level of the first chip is adjusted to the same first level as that of the second chip according to the target selection signal.

8. The adaptive level circuit according to claim 7, characterized in that: The target selection signal includes a first selection signal and a second selection signal; the at least two level control subunits include a first level control subunit and a second level control subunit; The first level control subunit includes a fourth switch tube, a fifth switch tube, a sixth resistor and a seventh resistor; The second level control subunit includes an eighth resistor and a ninth resistor; the data bus includes a first segment data bus and a second segment data bus, and the clock bus includes a first segment clock bus and a second segment clock bus; The first end of the sixth resistor and the first end of the seventh resistor are both connected to the first selection signal, and the other end of the sixth resistor is connected to the controlled end of the fourth switch tube; the input end and the output end of the fourth switch tube are respectively connected to the first segment data bus and the second segment data bus; the other end of the seventh resistor is connected to the controlled end of the fifth switch tube; the input end and the output end of the fifth switch tube are respectively connected to the first segment clock bus and the second segment clock bus; One end of the eighth resistor and one end of the ninth resistor are both connected to the first selection signal, the other end of the eighth resistor is connected to the first data bus, and the other end of the ninth resistor is connected to the first clock bus.

9. A chip, characterized in that: The method comprises an adaptive level circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that: The method comprises the adaptive level circuit as claimed in any one of claims 1 to 8, or comprises the chip as claimed in claim 9.

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