Low-temperature drift time delay circuit for asynchronous time sequence

Abstract

The invention discloses a low-temperature drift time delay circuit for an asynchronous time sequence, relates to the technical field of analog integrated circuits, and aims to solve the problem that the conversion precision of an SAR ADC asynchronous time sequence circuit is reduced due to the fact that an existing time delay circuit is influenced by temperature. The circuit at least comprises a temperature detection coding circuit, an inverter chain circuit and a regulating tube circuit. The regulating tube circuit is respectively connected with the inverter chain circuit and the temperature detection coding circuit, and the regulating tube circuit comprises a plurality of NMOS (N-channel Metal Oxide Semiconductor) tubes which are connected in parallel; the temperature detection coding circuit at least comprises a temperature sensor, a flash memory analog-to-digital converter and a digital coding logic circuit; the flash memory analog-to-digital converter is used for converting the temperature voltage signal into a thermometer code; the digital coding logic circuit is used for converting the thermometer code into a first control code, and the first control code is used for controlling the conduction and cut-off of an NMOS tube in the adjusting tube circuit. According to the low-temperature drift delay circuit provided by the invention, the delay time can be adjusted according to the temperature, and the conversion precision of an asynchronous sequential circuit is improved.

Description

Technical Field

[0001] The invention relates to the technical field of analog integrated circuits, and in particular to a low-temperature drift delay circuit for asynchronous timing. Background Art

[0002] The control logic of the SAR ADC successive approximation analog-to-digital converter is to uniformly latch the digital code generated by the comparator output result of each comparison cycle with a latch, and uniformly output the final digital code after a sampling cycle is completed. The control logic is mainly divided into synchronous control logic and asynchronous control logic. Asynchronous control logic is to generate a clock control signal that can meet the operating frequency of the capacitor array module and the comparator module of the digital-to-analog converter based on the combinational logic through the low-frequency signal generated inside the circuit, which can reduce the time waste of each comparison cycle and reduce the power consumption of the overall system. The delay module in the asynchronous control logic circuit is used to leave enough time for the establishment of the capacitor DAC. Its delay time directly determines the frequency of the conversion. The traditional delay module uses multiple inverters in cascade to achieve the delay effect, but this delay unit is greatly affected by temperature. With the increase of temperature, the increase in the lattice vibration amplitude of the MOS device will lead to a decrease in electron mobility and reduce the speed of signal establishment. The on-resistance of MOSFET is usually thermally dependent, and its temperature coefficient is a positive number. At high temperatures, the on-resistance will increase, and the signal establishment time will also increase. Therefore, the delay time of the delay module at high temperatures will be longer than that at normal temperatures.

[0003] The ambient temperature outside the chip and the heat generated by the chip's internal operation will cause the ADC to work in a high temperature environment. Since the delay module controls the conversion frequency of the SAR ADC, the increase in delay at high temperatures will increase the SAR ADC conversion time. This may result in the problem that the conversion of all cycles cannot be completed within the designed comparison time, resulting in a decrease in conversion accuracy. In the existing circuit simulation design, it is usually ensured that the conversion of all cycles can be completed under high temperature conditions. The delay time of the delay module at normal and low temperature conditions will be shorter than that at high temperature, and the conversion rate will be faster. All comparison cycles can be completed in a shorter time. However, the capacitor DAC small signal has insufficient settling time at normal and low temperature conditions, which affects the conversion accuracy. Summary of the invention

[0004] The object of the present invention is to provide a low temperature drift delay circuit for asynchronous timing, so as to solve the problem that the conversion accuracy of the SAR ADC asynchronous timing circuit is reduced due to the influence of temperature on the existing delay circuit.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A low temperature drift delay circuit for asynchronous timing, comprising at least: a temperature detection encoding circuit, an inverter chain circuit and a regulating tube circuit;

[0007] The regulating tube circuit is respectively connected to the inverter chain circuit and the temperature detection encoding circuit, and the regulating tube circuit includes a plurality of NMOS tubes connected in parallel;

[0008] The temperature detection coding circuit at least includes a temperature sensor, a flash memory analog-to-digital converter and a digital coding logic circuit; the temperature sensor is connected to the input end of the flash memory analog-to-digital converter, the output end of the flash memory analog-to-digital converter is connected to the input end of the digital coding logic circuit, and the output end of the digital coding logic circuit is connected to the regulating tube circuit;

[0009] The flash analog-to-digital converter is used to convert the temperature voltage signal detected by the temperature sensor into a thermometer code;

[0010] The digital coding logic circuit is used to convert the thermometer code into a first control code; the first control code is used to control the conduction and cutoff of the NMOS tube in the regulating tube circuit; the smaller the number of NMOS tubes that are turned on, the smaller the delay time of the low temperature drift delay circuit.

[0011] Compared with the prior art, the present invention provides a low temperature drift delay circuit for asynchronous timing, which at least includes: a temperature detection coding circuit, an inverter chain circuit and a regulating tube circuit; the regulating tube circuit is respectively connected to the inverter chain circuit and the temperature detection coding circuit, and the regulating tube circuit includes a plurality of parallel NMOS tubes; the temperature detection coding circuit at least includes a temperature sensor, a flash memory analog-to-digital converter and a digital coding logic circuit; the temperature sensor is connected to the input end of the flash memory analog-to-digital converter, the output end of the flash memory analog-to-digital converter is connected to the input end of the digital coding logic circuit, and the output end of the digital coding logic circuit is connected to the regulating tube circuit; the flash memory analog-to-digital converter is used to convert the temperature voltage signal detected by the temperature sensor into a thermometer code; the digital coding logic circuit is used to convert the thermometer code into a first control code; the present application implements monitoring of temperature changes through a temperature sensor, adopts a flash memory analog-to-digital converter and a digital coding logic circuit to convert the temperature signal into a control code, and controls the conduction number of NMOS tubes in the regulating tube circuit through the control code to adjust the delay time, thereby realizing a delay circuit whose delay time can be adjusted according to temperature, avoiding the influence of temperature on the delay circuit in the SAR ADC asynchronous logic circuit, thereby improving SAR. Conversion accuracy of ADC asynchronous timing circuit.

[0012] Optionally, the temperature detection encoding circuit further includes a unit gain buffer, the input end of the unit gain buffer is connected to the output end of the temperature sensor, and the output end of the unit gain buffer is connected to the input end of the flash memory analog-to-digital converter.

[0013] Optionally, the flash memory analog-to-digital converter includes multiple dynamic comparators and a reference voltage generating circuit arranged between a power supply and the multiple dynamic comparators, the first input end of each dynamic comparator is connected to the reference voltage generating circuit, the second input end of the dynamic comparator is connected to the output end of the unit gain buffer, the dynamic comparator includes a comparator and a latch, the output end of the comparator is connected to the input end of the latch, the output end of the latch is connected to the input end of the digital coding logic circuit, the clock signal input end of the comparator is connected to the first clock signal, the clock signal input end of the latch is connected to the second clock signal, and the rising edge arrival time of the second clock signal is later than the rising edge arrival time of the first clock signal.

[0014] Optionally, the inverter chain circuit includes multiple inverters connected in parallel, the inverter chain circuit includes a first inverter and a second inverter, and the regulating tube circuit includes a first regulating tube and a second regulating tube; the first regulating tube and the second regulating tube both include multiple NMOS tubes connected in parallel; the number of NMOS tubes in the first regulating tube is the same as the number of NMOS tubes in the second regulating tube; the first inverter is composed of a first PMOS tube and a first NMOS tube; the second inverter is composed of a second PMOS tube and a second NMOS tube; the drain of the first regulating tube is connected to the drain of the first PMOS tube, and the source of the first regulating tube is connected to the drain of the first NMOS tube; the gate of the first regulating tube is connected to the temperature detection coding circuit, the drain of the second regulating tube is connected to the drain of the second PMOS tube, and the source of the second regulating tube is connected to the drain of the second NMOS tube; the gate of the second regulating tube is connected to the temperature detection coding circuit.

[0015] Optionally, the low-temperature drift delay circuit also includes a first RC circuit and a second RC circuit, and the inverter chain circuit also includes a third inverter and a fourth inverter; the third inverter is composed of a third PMOS tube and a third NMOS tube, and the fourth inverter is composed of a fourth PMOS tube and a fourth NMOS tube, the first RC circuit is respectively connected to the third PMOS tube and the third NMOS tube, and the second RC circuit is respectively connected to the fourth PMOS tube and the fourth NMOS tube.

[0016] Optionally, the low temperature drift delay circuit also includes a digital adjustment circuit, and the adjustment tube circuit also includes a third adjustment tube and a fourth adjustment tube; the third adjustment tube and the fourth adjustment tube each include a plurality of NMOS tubes connected in parallel, and the inverter chain circuit also includes a fifth inverter and a sixth inverter, the fifth inverter is composed of a fifth PMOS tube and a fifth NMOS tube, and the sixth inverter is composed of a sixth PMOS tube and a sixth NMOS tube, and the digital adjustment circuit is used to configure a second control code according to the output waveform of the low temperature drift delay circuit, and control the number of NMOS tubes that are turned on in the third adjustment tube and the fourth adjustment tube.

[0017] Optionally, the reference voltage generating circuit includes a reset switch, a first resistor, a second resistor, a third resistor and a fourth resistor connected in series in sequence, the reset switch is connected to a power supply, and the fourth resistor is grounded; multiple dynamic comparators include a first dynamic comparator, a second dynamic comparator and a third dynamic comparator, the first input end of the first dynamic comparator is connected to the wire between the first resistor and the second resistor, the first input end of the second dynamic comparator is connected to the wire between the second resistor and the third resistor, the first input end of the third dynamic comparator is connected to the wire between the third resistor and the fourth resistor, the switching frequency of the reset switch is the same as the frequency of the first clock signal, and the reset switch is turned on before the rising edge of the first clock signal arrives.

[0018] Optionally, the first RC circuit includes a fifth resistor, a sixth resistor and a first capacitor, and the second RC circuit includes a seventh resistor, an eighth resistor and a second capacitor; one end of the fifth resistor is connected to the drain of the third PMOS tube, the other end of the fifth resistor is respectively connected to one end of the sixth resistor, the gate of the fourth PMOS tube and one end of the first capacitor, the other end of the sixth resistor is connected to the drain of the third NMOS tube, the gate of the third NMOS tube is connected to the gate of the third PMOS tube, the wire between the gate of the third NMOS tube and the gate of the third PMOS tube is connected to the output of the second inverter, and the gate of the third NMOS tube is connected to the gate of the third PMOS tube. The source is grounded, the source of the third PMOS tube is connected to the power supply, and the other end of the first capacitor is grounded; one end of the seventh resistor is connected to the drain of the fourth PMOS tube, the other end of the seventh resistor is respectively connected to one end of the eighth resistor and one end of the second capacitor, the other end of the eighth resistor is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the gate of the fourth PMOS tube, the wire between the gate of the fourth NMOS tube and the gate of the fourth PMOS tube is connected to the output of the third inverter, the source of the fourth NMOS tube is grounded, the source of the fourth PMOS tube is connected to the power supply, and the other end of the second capacitor is grounded.

[0019] Optionally, the temperature sensor is used to generate a temperature voltage signal that varies with temperature based on the characteristic that the voltage between the base and the emitter of the transistor is negatively correlated with the temperature.

[0020] Optionally, two input terminals of each dynamic comparator are connected to capacitors to ground. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0022] Figure 1 It is a structural schematic diagram of a SARADC asynchronous control logic circuit in the prior art;

[0023] Figure 2 A graph showing the output waveform of an inverter chain delay circuit changing with temperature in the prior art;

[0024] Figure 3 A schematic diagram of the structure of a low temperature drift delay circuit for asynchronous timing provided by the present invention;

[0025] Figure 4 A schematic diagram of the structure of the temperature detection encoding circuit provided by the present invention;

[0026] Figure 5 A timing diagram of the Flash ADC circuit provided by the present invention;

[0027] Figure 6 This is a comparison chart of the delay time provided by the present invention versus temperature.

[0028] Reference numerals:

[0029] 1-temperature detection encoding circuit, 2-first RC circuit, 3-second RC circuit, 4-digital adjustment circuit, 5-temperature sensor, 6-unit gain buffer, 7-flash memory analog-to-digital converter, 71-reference voltage generating circuit, 72-first dynamic comparator, 73-second dynamic comparator, 74-third dynamic comparator, 8-digital encoding logic circuit, MN1-first regulating tube, MN2-second regulating tube, MN3-third regulating tube, MN4-fourth regulating tube, M1-first NMOS tube, M7 first PMOS tube, M2-second NMOS tube, M8-second PMOS tube, M3-third NMOS tube, M9-third PMOS tube, M4-fourth NMOS tube, M10-fourth PMOS tube, M5-fifth NMOS tube, M11-fifth PMOS tube, M6-sixth NMOS tube, M12-sixth PMOS tube, RST-reset switch. DETAILED DESCRIPTION

[0030] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0031] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0032] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0033] Before introducing the embodiments of the present invention, the following definitions are given for the relevant terms involved in the embodiments of the present invention:

[0034] Flash ADC, or flash analog-to-digital converter, is a high-speed analog-to-digital converter that converts the input analog signal into a binary number in one step based on the working principle of comparators and encoders. It contains a series of comparators, each of which is associated with a reference voltage. When the input analog signal is compared by the comparator, each comparator will generate a digital output that represents the magnitude relationship between the input signal and the reference voltage. These digital outputs are encoded by the encoder and finally output a binary number that represents the magnitude of the input analog signal.

[0035] Figure 1It is an asynchronous control logic circuit of SAR ADC in the prior art. The comparator output signals VP and VN are always at two levels, one high and one low. They are at a high level after reset. The two can be used as clock signals for asynchronous timing by performing a NAND operation. Valid is at a low level during reset, and becomes a high level after the comparator outputs the result. NCLKs is the system sampling clock signal. When it is at a low level, the control logic circuit is reset. Valid triggers each D flip-flop in turn to generate output signals Clk1-Clkn. Clk1-Clkn is used to control the digital logic circuit. Clkc is the clock signal that controls the comparison and reset of the comparator. When all comparison cycles are completed, Clkc outputs a low level.

[0036] The delay module in the above structure is used to leave enough time for the capacitor DAC to establish. Its delay time directly determines the frequency of conversion, so it is necessary to strictly consider the impact of various PVT conditions on the delay. The traditional delay module uses multiple inverters in cascade to achieve the delay effect, but this delay unit is greatly affected by temperature. As the temperature rises, the increase in the lattice vibration amplitude of the MOS device will lead to a decrease in electron mobility and reduce the speed of signal establishment. The on-resistance of MOSFET is usually thermally dependent, and its temperature coefficient is a positive number. At high temperatures, the on-resistance will increase, and the signal establishment time will also increase. Therefore, the delay time of the delay module at high temperatures will be longer than at normal temperatures. For example Figure 2 It can be seen that the delay time of the delay module of the common inverter chain structure varies greatly with temperature, and the maximum deviation can reach 23%.

[0037] The ambient temperature outside the chip and the heat generated by the internal operation of the chip may cause the ADC to operate in a high temperature environment. Since the delay module controls the conversion frequency of the SAR ADC, the increase in delay under high temperature will increase the SAR ADC conversion time. This may result in the inability to complete the conversion of all cycles within the designed comparison time, resulting in a decrease in conversion accuracy.

[0038] To solve the above problems, the present invention proposes a low-temperature drift delay circuit for asynchronous timing, which is applied to the SARADC asynchronous timing control logic circuit, monitors the temperature change in real time through a temperature sensor, converts the temperature signal into a digital code to control the number of MOS tubes turned on, and then realizes a low-temperature drift delay circuit. In addition, the delay time can be manually adjusted through register configuration. The following is a detailed description.

[0039] See also Figure 3 and Figure 4A low temperature drift delay circuit for asynchronous timing of the present invention comprises a temperature detection coding circuit 1, an inverter chain circuit, a regulating tube circuit, a first RC circuit 2, a second RC circuit 3, and a digital adjustment circuit 4; the regulating tube circuit is respectively connected to the inverter chain circuit and the temperature detection coding circuit 1, and the regulating tube circuit comprises a plurality of parallel NMOS tubes; the regulating tube circuit may comprise a first regulating tube MN1, a second regulating tube MN2, a third regulating tube MN3, and a fourth regulating tube MN4. The first regulating tube MN1, the second regulating tube MN2, the third regulating tube MN3, and the fourth regulating tube MN4 all comprise a plurality of parallel-connected NMOS tubes of the same size; the number of NMOS tubes in the first regulating tube is the same as the number of NMOS tubes in the second regulating tube, the number of NMOS tubes in the third regulating tube is the same as the number of NMOS tubes in the fourth regulating tube; when the number of NMOS tubes turned on increases, the parasitic capacitance at the inverter C1 point increases, slowing down the signal establishment time, increasing the delay time of the inverter chain circuit, and thus increasing the delay of the low temperature drift delay circuit. When the first control code Vd<7:0> is 00000001, the regulating tube circuit is in the minimum delay state, and then the low temperature drift delay circuit is in the minimum delay state. When the first control code Vd<7:0> is 11111111, the regulating tube circuit is in the maximum delay state, and then the low temperature drift delay circuit is in the maximum delay state. It should be understood that the places where the wires are connected in the figure are represented by black dots, and the places without black dots indicate that the two wires are not connected.

[0040] The temperature detection coding circuit 1 includes a temperature sensor 5, a flash memory analog-to-digital converter 7 and a digital coding logic circuit 8; the temperature sensor 5 is connected to the input end of the flash memory analog-to-digital converter 7, the output end of the flash memory analog-to-digital converter 7 is connected to the input end of the digital coding logic circuit 8, and the output end of the digital coding logic circuit 8 is connected to the regulating tube circuit;

[0041] The flash analog-to-digital converter 7 is used to convert the temperature voltage signal detected by the temperature sensor 5 into a thermometer code;

[0042] The digital coding logic circuit 8 is used to convert the thermometer code into a first control code; the first control code is used to control the conduction and cutoff of the NMOS tubes in the first and second regulating tubes of the regulating tube circuit; the smaller the number of NMOS tubes turned on, the smaller the delay time of the low temperature drift delay circuit.

[0043] In the above structure, the thermometer codes converted by the flash analog-to-digital converter 7 are "000", "001", "011" and "111".

[0044] The present application monitors temperature changes through a temperature sensor, uses a flash memory analog-to-digital converter and a digital coding logic circuit to convert the temperature signal into a control code, and controls the conduction number of NMOS tubes in the regulating tube circuit through the control code to adjust the delay time, thereby realizing a delay circuit in which the delay time can be adjusted according to the temperature, avoiding the influence of temperature on the delay circuit in the SAR ADC asynchronous logic circuit, thereby improving the conversion accuracy of the SAR ADC asynchronous timing circuit.

[0045] As an optional manner, the temperature detection encoding circuit 1 may further include a unit gain buffer 6, the input end of the unit gain buffer 6 is connected to the output end of the temperature sensor 5, and the output end of the unit gain buffer 6 is connected to the input end of the flash analog-to-digital converter 7. The output end of the temperature sensor 5 is connected to the unit gain buffer to improve the load capacity.

[0046] See also Figure 3 The inverter chain circuit in the above structure includes a plurality of inverters connected in parallel. The inverter chain circuit may include a first inverter, a second inverter, a third inverter, a fourth inverter, a fifth inverter and a sixth inverter. The number of inverters in the inverter chain can be set according to demand. The first inverter is composed of a first PMOS tube M7 and a first NMOS tube M1. The second inverter is composed of a second PMOS tube M8 and a second NMOS tube M2. The third inverter is composed of a third PMOS tube M9 and a third NMOS tube M3. The fourth inverter is composed of a fourth PMOS tube M10 and a fourth NMOS tube M4. The fifth inverter is composed of a fourth PMOS tube M11 and a fourth NMOS tube M5. The phase shifter is composed of a fifth PMOS tube M11 and a fifth NMOS tube M5, the sixth inverter is composed of a sixth PMOS tube M12 and a sixth NMOS tube M6, the drain of the first regulating tube MN1 is connected to the drain of the first PMOS tube M7, the source of the first regulating tube MN1 is connected to the drain of the first NMOS tube M1; the gate of the first regulating tube MN1 is connected to the temperature detection coding circuit 1, the drain of the second regulating tube MN2 is connected to the drain of the second PMOS tube M8, the source of the second regulating tube MN2 is connected to the drain of the second NMOS tube M2; the gate of the second regulating tube MN2 is connected to the temperature detection coding circuit 1. The first RC circuit 2 is respectively connected to the third PMOS tube M9 and the third NMOS tube M3, and the second RC circuit 3 is respectively connected to the fourth PMOS tube M10 and the fourth NMOS tube M4. The source of the first PMOS tube M7, the source of the second PMOS tube M8, the source of the third PMOS tube M9, the source of the fourth PMOS tube M10, the source of the fifth PMOS tube M11 and the source of the sixth PMOS tube M12 are connected to the power supply, and the source of the first NMOS tube M1, the source of the second NMOS tube M2, the source of the third NMOS tube M3, the source of the fourth NMOS tube M4, the source of the fifth NMOS tube M5 and the source of the sixth NMOS tube M6 are grounded.

[0047] In the above structure, the first RC circuit 2 includes a fifth resistor R5, a sixth resistor R6 and a first capacitor Ca, and the second RC circuit 3 includes a seventh resistor R7, an eighth resistor R8 and a second capacitor Cb; one end of the fifth resistor R5 is connected to the drain of the third PMOS tube M9, the other end of the fifth resistor R5 is respectively connected to one end of the sixth resistor R6, one end of the first capacitor Ca and a wire between the gate of the fourth PMOS tube M10 and the gate of the fourth NMOS tube M4, the other end of the sixth resistor R6 is connected to the drain of the third NMOS tube M3, the gate of the third NMOS tube M3 is connected to the gate of the third PMOS tube M9, and the output end of the second inverter is connected to the gate of the third NMOS tube M3 and the gate of the third PMOS tube M9. The first capacitor Ca is connected to the gate of the fourth PMOS tube M9, and the other end of the first capacitor Ca is grounded; one end of the seventh resistor R7 is connected to the drain of the fourth PMOS tube M10, the other end of the seventh resistor R7 is respectively connected to one end of the eighth resistor R8 and one end of the second capacitor Cb, the other end of the seventh resistor R7 is connected to the gate of the fifth PMOS tube M11 and the gate of the fifth NMOS tube M5, the other end of the eighth resistor R8 is connected to the drain of the fourth NMOS tube M4, the gate of the fourth NMOS tube M4 is connected to the gate of the fourth PMOS tube M10, the wire between the gate of the fourth NMOS tube M4 and the gate of the fourth PMOS tube M10 is connected to the output of the third inverter, and the other end of the second capacitor Cb is grounded. The gate of the third regulating tube MN3 and the gate of the fourth regulating tube MN4 are connected to the output end of the digital adjustment circuit 4, the drain of the fifth PMOS tube M11 is connected to the drain of the third regulating tube MN3, the source of the third regulating tube MN3 is connected to the drain of the fifth NMOS tube M5, the gate of the fifth PMOS tube M11 is connected to the gate of the fifth NMOS tube M5, the wire between the gate of the fifth PMOS tube M11 and the gate of the fifth NMOS tube M5 is connected to the output of the fourth inverter, the drain of the sixth PMOS tube M12 is connected to the drain of the fourth regulating tube MN4, the source of the fourth regulating tube MN4 is connected to the source of the sixth NMOS tube M6, the gate of the sixth PMOS tube M12 is connected to the gate of the sixth NMOS tube M6, and the wire between the gate of the sixth PMOS tube M12 and the gate of the sixth NMOS tube M6 is connected to the output of the fifth inverter.

[0048] In the above structure, the total resistance of the first RC circuit 2 is greater than the on-resistance of the third PMOS tube M9 and the third NMOS tube M3, and the total resistance of the second RC circuit 3 is greater than the on-resistance of the fourth PMOS tube M10 and the fourth NMOS tube M4. Adding an RC circuit to the delay circuit composed of the inverter chain circuit improves the stability of the delay to a certain extent. The RC device changes little with temperature. When RC is large, the signal establishment time at the inverter output end is mainly determined by RC, which reduces the influence of temperature on the delay circuit.

[0049] The digital trimming circuit 4 in the above structure is used to configure the second control code according to the output waveform of the low temperature drift delay circuit, and the second control code is used to control the number of NMOS tubes that are turned on in the third regulating tube and the fourth regulating tube. The digital trimming circuit uses a register to configure the control code input into the encoding circuit, and also uses the NMOS tube to adjust the delay time. When the PVT condition change of the SAR ADC affects the delay circuit, a small delay adjustment can be provided.

[0050] The flash memory analog-to-digital converter 7 in the above structure includes multiple dynamic comparators and a reference voltage generating circuit arranged between a power supply and the multiple dynamic comparators. The first input end of each dynamic comparator is connected to the reference voltage generating circuit, and the second input end of the dynamic comparator is connected to the output end of the unit gain buffer. The dynamic comparator includes a comparator and a latch. The output end of the comparator is connected to the input end of the latch, and the output end of the latch is connected to the input end of the digital coding logic circuit. The clock signal input end of the comparator is connected to the first clock signal CLK1, and the clock signal input end of the latch is connected to the second clock signal CLK2.

[0051] The reference voltage generating circuit in the above structure includes a reset switch RST, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4 connected in series in sequence, the reset switch RST is connected to a power supply, and the fourth resistor R4 is grounded; multiple dynamic comparators include a first dynamic comparator 72, a second dynamic comparator 73 and a third dynamic comparator 74, the first input end of the first dynamic comparator is connected to the wire between the first resistor R1 and the second resistor R2, the first input end of the second dynamic comparator is connected to the wire between the second resistor R2 and the third resistor R3, and the first input end of the third dynamic comparator is connected to the wire between the third resistor R3 and the fourth resistor R4.

[0052] like Figure 5 As shown, since the temperature change speed is generally slow, in order to save power consumption, the low-speed clock CLK1 is used to limit the sampling speed of the flash analog-to-digital converter FlashADC. The latch can only open the latch signal after the voltage signal comparison is completed, so CLK1 needs to be delayed before it can be used to control the latch switch, that is, after CLK1 is delayed to obtain CLK2, CLK2 controls the switch of the latch. The switching frequency of the reset switch RST is the same as the frequency of the first clock signal CLK1. The switching signal of the reset switch is turned on before the rising edge of the first clock signal CLK1 arrives, generating a stable Vref reference voltage. The arrival time of the rising edge of the second clock signal CLK2 is later than the arrival time of the rising edge of the first clock signal CLK1.

[0053] The temperature sensor in the above structure is based on the voltage V between the base and emitter of the transistor.BE The characteristic of being negatively correlated with temperature produces a temperature voltage signal that changes approximately linearly with temperature.

[0054] Both input terminals of the comparator in each dynamic comparator in the above structure are connected to the ground capacitor, which can effectively reduce the kickback noise of the comparator.

[0055] In the specific implementation process, the circuit first automatically detects the chip temperature and inputs the temperature voltage signal into the flash analog-to-digital converter. The flash analog-to-digital converter converts the temperature voltage signal into a 3-bit digital signal, and then outputs an 8-bit control code through the digital coding logic circuit to control the conduction and cutoff of the NMOS tubes in MN1 and MN2. The resistor string R1-R4 is used in the flash analog-to-digital converter FlashADC to generate a stable reference voltage, and a dynamic comparator is used to compare the temperature voltage signal and the reference voltage, thereby avoiding DC power consumption. Usually, the output voltage of the comparator is coupled to the input end through parasitic capacitance, which will cause the voltage fluctuation of the comparator input end, and the kickback noise generated is relatively large, which affects the input voltage size at the time of the comparator judgment. By connecting the ground capacitor to the two input ends of the comparator, the kickback noise of the comparator can be effectively reduced. The comparison result output by the comparator is held by the latch until the next detection cycle, and the comparison result D2-D0 is finally input to the digital coding logic circuit to generate an 8-bit first control code. At high temperatures, the delay of the inverter chain MOS tube itself will increase, so in order to keep the regulating tube in a low delay state, it is necessary to use the first control code of "00000001" for control. At low temperatures, the MOS tube delay is small, and the asynchronous timing comparison cycle will be reduced. In order for the SAR ADC to fully utilize the designed comparison phase time, the number of regulating tube conduction is increased to increase the delay time, that is, the first control code is "11111111". The temperature range in which the chip may work is divided into 4 temperature intervals, and the number of NMOS tubes turned on in the temperature interval and the size of the turned-on NMOS tube are determined according to the simulated delay time of the delay module in each interval. Exemplarily, the temperature range in which the chip may work can be: -40~0℃, 0~50℃, 50~100℃ and 100~130℃. The first control code corresponding to the conversion in the temperature range of -40 to 0°C is: 111111111; the first control code corresponding to the conversion in the temperature range of 0 to 50°C is: 00111111; the first control code corresponding to the conversion in the temperature range of 50 to 100°C is: 00001111; and the first control code corresponding to the conversion in the temperature range of 100 to 130°C is: 00000001.

[0056] like Figure 6As shown, the delay time of the traditional inverter chain delay circuit is positively correlated with temperature, with a deviation of 23.6% and a variance of 0.5. The delay circuit of the present invention is adjusted by a temperature detection encoding circuit, and the delay time decreases with the temperature change, with a maximum deviation of 8.9% and a variance of only 0.23. The delay circuit of the present invention exhibits good low temperature drift performance, and can be used in SAR ADC asynchronous timing to generate a relatively stable conversion frequency under various temperature conditions, making full use of the designed comparison time. At the same time, when other factors affect the delay time, the digital adjustment circuit can perform foreground adjustment and calibration to keep the delay time of the delay circuit within a reasonable range.

[0057] It can be seen from the above structure and specific implementation methods that the effects of the low-temperature drift delay circuit for asynchronous timing of the present invention include: 1. It has good low-temperature drift characteristics, the delay time changes little with temperature, and the maximum deviation is only 8.9%, which is very suitable for controlling the conversion speed in SAR ADC asynchronous timing. 2. The delay circuit is simple and efficient, and the number of MOS tubes used is small. Only a small number of hardware resources are needed to achieve a stable delay time, reducing the adjustment cost. 3. The delay circuit takes power consumption issues into consideration and reduces the temperature detection frequency. At the same time, a reset switch is used to control the current consumption of the FlashADC resistor string. The switch is disconnected when temperature detection is not performed, reducing the power consumption of the temperature detection circuit. 4. An RC circuit is added to the inverter chain delay circuit. The delay time mainly depends on the size of RC, which reduces the degree to which the inverter chain delay circuit is affected by temperature, and further improves the stability of the delay circuit of the present invention.

[0058] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0059] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A low temperature drift delay circuit for asynchronous timing, characterized in that: At least: Temperature detection encoding circuit, inverter chain circuit and regulating tube circuit; The regulating tube circuit is respectively connected to the inverter chain circuit and the temperature detection encoding circuit, and the regulating tube circuit includes a plurality of NMOS tubes connected in parallel; The temperature detection coding circuit at least includes a temperature sensor, a flash memory analog-to-digital converter and a digital coding logic circuit; the temperature sensor is connected to the input end of the flash memory analog-to-digital converter, the output end of the flash memory analog-to-digital converter is connected to the input end of the digital coding logic circuit, and the output end of the digital coding logic circuit is connected to the regulating tube circuit; The flash analog-to-digital converter is used to convert the temperature voltage signal detected by the temperature sensor into a thermometer code; The digital coding logic circuit is used to convert the thermometer code into a first control code; the first control code is used to control the conduction and cutoff of the NMOS tube in the regulating tube circuit; the smaller the number of NMOS tubes that are turned on, the smaller the delay time of the low temperature drift delay circuit.

2. The low temperature drift delay circuit for asynchronous timing according to claim 1, characterized in that: The temperature detection encoding circuit also includes a unit gain buffer, an input end of the unit gain buffer is connected to an output end of the temperature sensor, and an output end of the unit gain buffer is connected to an input end of the flash memory analog-to-digital converter.

3. The low temperature drift delay circuit for asynchronous timing according to claim 2, characterized in that: The flash memory analog-to-digital converter includes multiple dynamic comparators and a reference voltage generating circuit arranged between a power supply and the multiple dynamic comparators, the first input end of each dynamic comparator is connected to the reference voltage generating circuit, the second input end of the dynamic comparator is connected to the output end of the unit gain buffer, the dynamic comparator includes a comparator and a latch, the output end of the comparator is connected to the input end of the latch, the output end of the latch is connected to the input end of the digital coding logic circuit, the clock signal input end of the comparator is connected to the first clock signal, the clock signal input end of the latch is connected to the second clock signal, and the rising edge arrival time of the second clock signal is later than the rising edge arrival time of the first clock signal.

4. The low temperature drift delay circuit for asynchronous timing according to claim 1, characterized in that: The inverter chain circuit includes a plurality of inverters connected in parallel, the inverter chain circuit includes a first inverter and a second inverter, the regulating tube circuit includes a first regulating tube and a second regulating tube; the first regulating tube and the second regulating tube both include a plurality of NMOS tubes connected in parallel; the number of NMOS tubes in the first regulating tube is the same as the number of NMOS tubes in the second regulating tube; the first inverter is composed of a first PMOS tube and a first NMOS tube; the second inverter is composed of a second PMOS tube and a second NMOS tube; the drain of the first regulating tube is connected to the drain of the first PMOS tube, and the source of the first regulating tube is connected to the drain of the first NMOS tube; the gate of the first regulating tube is connected to the temperature detection encoding circuit, the drain of the second regulating tube is connected to the drain of the second PMOS tube, and the source of the second regulating tube is connected to the drain of the second NMOS tube; the gate of the second regulating tube is connected to the temperature detection encoding circuit.

5. The low temperature drift delay circuit for asynchronous timing according to claim 4, characterized in that: The low temperature drift delay circuit also includes a first RC circuit and a second RC circuit, and the inverter chain circuit also includes a third inverter and a fourth inverter; the third inverter is composed of a third PMOS tube and a third NMOS tube, and the fourth inverter is composed of a fourth PMOS tube and a fourth NMOS tube, the first RC circuit is respectively connected to the third PMOS tube and the third NMOS tube, and the second RC circuit is respectively connected to the fourth PMOS tube and the fourth NMOS tube.

6. The low temperature drift delay circuit for asynchronous timing according to claim 4, characterized in that: The low temperature drift delay circuit also includes a digital trimming circuit, and the regulating tube circuit also includes a third regulating tube and a fourth regulating tube; the third regulating tube and the fourth regulating tube each include a plurality of NMOS tubes connected in parallel, and the inverter chain circuit also includes a fifth inverter and a sixth inverter, the fifth inverter includes a fifth PMOS tube and a fifth NMOS tube, and the sixth inverter includes a sixth PMOS tube and a sixth NMOS tube, and the digital trimming circuit is used to configure a second control code according to an output waveform of the low temperature drift delay circuit, and control the number of NMOS tubes that are turned on in the third regulating tube and the fourth regulating tube.

7. The low temperature drift delay circuit for asynchronous timing according to claim 3, characterized in that: The reference voltage generating circuit includes a reset switch, a first resistor, a second resistor, a third resistor and a fourth resistor connected in series in sequence, the reset switch is connected to a power supply, and the fourth resistor is grounded; multiple dynamic comparators include a first dynamic comparator, a second dynamic comparator and a third dynamic comparator, the first input end of the first dynamic comparator is connected to the wire between the first resistor and the second resistor, the first input end of the second dynamic comparator is connected to the wire between the second resistor and the third resistor, the first input end of the third dynamic comparator is connected to the wire between the third resistor and the fourth resistor, the switching frequency of the reset switch is the same as the frequency of the first clock signal, and the reset switch is turned on before the rising edge of the first clock signal arrives.

8. The low temperature drift delay circuit for asynchronous timing according to claim 5, characterized in that: The first RC circuit includes a fifth resistor, a sixth resistor and a first capacitor, and the second RC circuit includes a seventh resistor, an eighth resistor and a second capacitor; one end of the fifth resistor is connected to the drain of the third PMOS tube, the other end of the fifth resistor is respectively connected to one end of the sixth resistor, the gate of the fourth PMOS tube and one end of the first capacitor, the other end of the sixth resistor is connected to the drain of the third NMOS tube, the gate of the third NMOS tube is connected to the gate of the third PMOS tube, the wire between the gate of the third NMOS tube and the gate of the third PMOS tube is connected to the output of the second inverter, and the source of the third NMOS tube is connected to the output of the second inverter. The first capacitor is connected to the ground, the source of the third PMOS tube is connected to the power supply, and the other end of the first capacitor is grounded; one end of the seventh resistor is connected to the drain of the fourth PMOS tube, the other end of the seventh resistor is respectively connected to one end of the eighth resistor and one end of the second capacitor, the other end of the eighth resistor is connected to the drain of the fourth NMOS tube, the gate of the fourth NMOS tube is connected to the gate of the fourth PMOS tube, the wire between the gate of the fourth NMOS tube and the gate of the fourth PMOS tube is connected to the output of the third inverter, the source of the fourth NMOS tube is grounded, the source of the fourth PMOS tube is connected to the power supply, and the other end of the second capacitor is grounded.

9. The low temperature drift delay circuit for asynchronous timing according to claim 3, characterized in that: The temperature sensor is used to generate a temperature voltage signal that varies with temperature according to the characteristic that the voltage between the base and the emitter of the transistor is negatively correlated with the temperature.

10. The low temperature drift delay circuit for asynchronous timing according to claim 3, characterized in that: The two input terminals of each dynamic comparator are connected to capacitors to ground.

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