Open-loop modulator circuit, digital-to-time converter, and system

Abstract

The invention provides an open-loop modulator circuit, a digital-to-time converter and a system. The digital-to-time converter comprises a delay generator and a current acquisition module. The current obtained by the delay generator from the power supply comprises a fixed current component and a variable current component, and the amplitude of the fixed current component is fixed and is not influenced by the amplitude represented by the second code of the specified required delay; the amplitude of the variable current component is determined only by the amplitude represented by the second code. The current acquisition module acquires the correction current from the power supply, and the amplitude of the correction current is only determined by the complement of the second code.

Description

Technical Field

[0001] The present invention relates to the technical field of digital to time converters, and in particular to an open loop modulator (OLM) circuit, a digital to time converter (DTC), and a system. Background Art

[0002] A digital-to-time converter is generally used to generate an output signal whose corresponding edge is delayed from the edge of an input clock signal, and the amount of delay between the two is determined by the input code. As is known to all, digital-to-time converters are widely used in electronic devices, such as fractional-N phase locked loops (PLLs), sampling oscilloscopes, direct digital frequency synthesis, etc.

[0003] The ideal transfer function of a digital-to-time converter is a straight line, which means that the time delay of the output changes linearly with the corresponding change in the input code value. However, in some real-world scenarios, the actual output time delay may deviate from the ideal value, which is called nonlinearity in the operation of the digital-to-time converter.

[0004] It is well known that one of the causes of nonlinearity in digital-to-time converters is that the corresponding delays specified by successive input codes are not equal, for example, when the digital-to-time converter is used in a fractional-frequency phase-locked loop. This nonlinearity may be unacceptable in some environments. Summary of the invention

[0005] In view of this, the present application provides an open-loop modulator circuit, a digital-to-time converter, and a system to reduce the nonlinearity of the digital-to-time converter caused by the unequal corresponding delays specified by consecutive input codes.

[0006] In a first aspect, the present application provides an open-loop modulator circuit for generating a fractional output clock, wherein the frequency of the fractional output clock is an expected fraction of a reference clock, wherein the expected fraction includes an integer part and a decimal part, and the open-loop modulator circuit includes:

[0007] A Delta Sigma Modulator (DSM) for receiving the expected score and generating a corresponding first coding sequence and a second coding sequence; wherein the first coding sequence includes a set of lower values ​​and a set of higher values, and a common average of the set of lower values ​​and the set of higher values ​​is used to represent the expected score;

[0008] a first frequency divider, configured to receive the reference clock and each first code of the first code sequence, and generate a frequency-divided signal according to the reference clock and each first code of the first code sequence; wherein a period of the frequency-divided signal is a multiple of the reference clock period, and the multiple is a value represented by each first code in the first code sequence;

[0009] A digital time converter, used to generate the fractional output clock according to the frequency-divided signal; wherein the digital time converter comprises:

[0010] a delay generator, powered by a power supply, for receiving the frequency-divided signal and delaying an edge of interest of the frequency-divided signal according to a corresponding second code in the second code sequence, so as to generate the fractional output clock; wherein the current obtained by the delay generator from the power supply includes a fixed current component and a variable current component, the amplitude of the fixed current component is not affected by the corresponding second code in the second code sequence, and the amplitude of the variable current component is determined only by the amplitude represented by the corresponding second code in the second code sequence;

[0011] A current acquisition module is used to acquire a correction current from the power supply; wherein the magnitude of the correction current is determined only by the complement of the corresponding second code in the second coding sequence; the current acquisition module is used to ensure that the sum of the correction current and the variable current component is not affected by the corresponding second code in the second coding sequence and remains constant; the total current acquired from the power supply by the delay generator and the current acquisition module is equal to the sum of the sum and the fixed current component.

[0012] In a second aspect, the present application provides a digital time converter, the digital time converter is used to generate a fractional output clock from a frequency-divided signal according to a delayed coding sequence, the digital time converter comprising:

[0013] a delay generator, powered by a power supply, for receiving the divided frequency signal and delaying an edge of interest of the divided frequency signal according to each delay code of the delay code sequence to generate the fractional output clock, wherein the current obtained by the delay generator from the power supply comprises a fixed current component and a variable current component, the amplitude of the fixed current component remains unchanged regardless of the value represented by the corresponding delay code of the delay code sequence; and the amplitude of the variable current component is determined only by the amplitude represented by the corresponding delay code of the delay code sequence;

[0014] A current acquisition module is used to extract a correction current from the power supply, the amplitude of the correction current is determined only by the complement of the corresponding delay code of the delay code sequence; wherein the current acquisition module is used to ensure that the sum of the correction current and the variable current component acquired by the delay generator is not affected by the amplitude represented by the corresponding delay code and remains unchanged; the total current acquired from the power supply by the delay generator and the current acquisition module is equal to the sum of the sum and the fixed current component.

[0015] In a third aspect, the present application provides a system, the system comprising:

[0016] a line card for receiving a data packet, the line card re-timing the data packet with reference to a selected clock, and transmitting the re-timing data packet;

[0017] A first timing card, used to generate a first clock; and

[0018] power supply;

[0019] Wherein, the line card includes:

[0020] a phase-locked loop, configured to receive the first clock, the phase-locked loop generating a reference clock locked to the first clock; and

[0021] an open-loop modulator, configured to receive the reference clock and generate a fractional output clock having a frequency that is a desired fraction of the reference clock, wherein the open-loop modulator comprises:

[0022] A delta-sigma modulator, configured to receive the expected score and generate a corresponding first code sequence and a second code sequence; wherein the first code sequence includes a set of lower values ​​and a set of upper values, and a common average of the set of lower values ​​and the set of upper values ​​is used to represent the expected score;

[0023] a first frequency divider, configured to receive the reference clock and each first code of the first code sequence, and generate a frequency-divided signal according to the reference clock and each first code of the first code sequence; wherein a period of the frequency-divided signal is a multiple of the reference clock period, and the multiple is a value represented by each first code in the first code sequence;

[0024] A digital time converter, used to generate the fractional output clock according to the frequency-divided signal; wherein the digital time converter comprises:

[0025] a delay generator, powered by a power supply, for receiving the frequency-divided signal and delaying an edge of interest of the frequency-divided signal according to a corresponding second code in the second code sequence, so as to generate the fractional output clock; wherein the current obtained by the delay generator from the power supply includes a fixed current component and a variable current component, the amplitude of the fixed current component is not affected by the corresponding second code in the second code sequence, and the amplitude of the variable current component is determined only by the amplitude represented by the corresponding second code in the second code sequence;

[0026] A current acquisition module is used to acquire a correction current from the power supply; wherein the magnitude of the correction current is determined only by the complement of the corresponding second code in the second coding sequence; the current acquisition module is used to ensure that the sum of the correction current and the variable current component is not affected by the corresponding second code in the second coding sequence and remains constant; the total current acquired from the power supply by the delay generator and the current acquisition module is equal to the sum of the sum and the fixed current component. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Example embodiments of the present application will be described with reference to the following drawings.

[0028] Figure 1 A block diagram of a device according to an embodiment of the present application is shown.

[0029] Figure 2 A timing diagram (not to scale) showing the waveforms generated by various nodes of an open-loop modulator.

[0030] Figure 3A A detailed block diagram of a prior art digital-to-time converter is shown.

[0031] Figure 3B A detailed block diagram of a prior art digital-to-time converter is shown.

[0032] Figure 3C Timing diagram (not to scale) showing ripple in the supply voltage in a prior art digital-to-time converter.

[0033] Figure 3D Schematic diagram showing the manner in which ripple is reduced in a prior art digital to time converter.

[0034] Figure 4 FIG. 4 is a block diagram of a digital-to-time converter provided by an embodiment of the present application.

[0035] Figure 5 A circuit schematic diagram of a current acquisition module provided in an embodiment of the present application is shown.

[0036] Figure 6 A timing diagram (not drawn to scale) showing that an embodiment of the present application provides a reduction in power supply voltage ripple.

[0037] Figure 7 A block diagram of a system using the device provided in an embodiment of the present application is shown.

[0038] In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number. DETAILED DESCRIPTION

[0039] 1. Overview

[0040] One aspect of the present application relates to an open-loop modulator circuit, which generates a fractional output clock whose frequency is a desired fraction of a reference clock, wherein the desired fraction includes an integer part and a fractional part. The open-loop modulator circuit includes a delta-sigma modulator, a first frequency divider, and a digital-to-time converter.

[0041] A delta-sigma modulator, configured to receive a desired score and generate a corresponding first coded sequence and a second coded sequence; wherein the first coded sequence includes a set of lower values ​​and a set of upper values, and a common average of the set of lower values ​​and the set of upper values ​​is used to represent the desired score;

[0042] A first frequency divider, used for receiving a reference clock and each first code of a first code sequence, and generating a frequency-divided signal according to the reference clock and each first code of the first code sequence; wherein a period of the frequency-divided signal is a multiple of a period of the reference clock, and the multiple is a value represented by each first code in the first code sequence;

[0043] A digital time converter, used for generating a fractional output clock according to a frequency-divided signal; wherein the digital time converter comprises:

[0044] A delay generator, powered by a power supply, is used to receive the frequency-divided signal and delay the edge of interest of the frequency-divided signal according to the corresponding second code in the second code sequence to generate a fractional output clock; wherein the current obtained by the delay generator from the power supply includes a fixed current component and a variable current component, the amplitude of the fixed current component is not affected by the corresponding second code in the second code sequence, and the amplitude of the variable current component is determined only by the amplitude represented by the corresponding second code in the second code sequence;

[0045] A current acquisition module is used to acquire a correction current from a power supply; wherein the magnitude of the correction current is determined only by the complement of the corresponding second code in the second coding sequence; the current acquisition module is used to ensure that the sum of the correction current and the variable current component is not affected by the corresponding second code in the second coding sequence and remains constant; the total current acquired from the power supply by the delay generator and the current acquisition module is equal to the sum of the sum and the fixed current component.

[0046] Therefore, the total current obtained by the delay generator and the current acquisition module from the power supply remains constant, thereby improving the linearity of the digital-to-time converter. At the same time, since the current acquisition module only supplements the variable current component to ensure the constancy of the total current, the power supply efficiency is also improved.

[0047] In one embodiment, the current acquisition module is implemented by a digital to analog converter (DAC), which takes the complement of the second code as input and obtains the correction current from the power supply to convert the complement into current. On the other hand, in order to further improve area efficiency, the digital to analog converter only uses a part of the complement of the second code as the input of the digital to analog converter.

[0048] The present application will be described below in conjunction with a plurality of embodiments. However, it should be clear to those skilled in the art that the present application may be implemented by omitting one or more specific features or by other methods, components, materials, etc. In other embodiments, known structures, materials, or operations are not described in detail one by one to simplify the features of the present application. In addition, although only some combinations are described here for the sake of brevity, the described features / aspects may be implemented in various combinations.

[0049] 2. Implementation Equipment

[0050] Figure 1 It is a schematic diagram showing the device of the embodiment of the present application. Figure 1 An open loop modulator 100 (also called an open loop fractional frequency divider or fractional frequency divider) is described. The open loop modulator 100 receives a reference clock fref on line 125 and generates an output clock fout on line 165. Figure 1 As shown, the open-loop modulator 100 includes a delta-sigma modulator 130, a multi-modulus divider (MMD) 140, a digital-to-time converter 150, and a duty cycle block (DCB) 160. It should be noted that Figure 1 Only components related to the present application are shown in the figure. It can be understood that the open-loop modulator 100 may include Figure 1 More or fewer modules may be shown.

[0051] The reference clock fref 125 may be generated by a phase-locked loop, an oscillator, etc. In one embodiment, the phase-locked loop 110 uses existing technical means to generate the reference clock fref.

[0052] The delta-sigma modulator 130 receives a desired "fraction" ("frequency division") comprising an integer portion 105 and a fractional portion 107, and generates a series of related code pairs on the output lines of the delta-sigma modulator 130, namely lines 132 and 135, using existing technical means. The first value in the code pair is an integer, and the second value represents the desired delay, which are combined to generate the desired fractional output clock fout on the output line of the duty cycle module 160, namely line 165. For example, the fraction 4.25 includes an integer portion "4" and a fractional portion "0.25", and sends a (repeating) sequence of numbers 4, 4, 4, and 5 (average value 4.25) on line 132, while sending a sequence of delay values ​​1 / 4, 2 / 4, 3 / 4, and 0 on line 135. As described below, the period of the fractional output clock fout (or the fractional output clock f_frac output on the output line of the digital-to-time converter 150, namely line 155) is 4.25 times the period of the reference clock fref125. When the higher value 5 is transmitted on the line 132, the control signal (dsm_carry) of the delta-sigma modulator 130 is 1, otherwise it is 0. In one embodiment, the delta-sigma modulator 130 is a first-order delta-sigma modulator. Although the present embodiment is described by taking the delta-sigma modulator 130 as a first-order delta-sigma modulator as an example, it should be clear to those skilled in the art through this application that the present application is also applicable to higher-order delta-sigma modulators. The delta-sigma modulator 130 can be implemented by existing technical means.

[0053] The multi-mode divider 140 receives the reference clock fref on the output line of the reference clock fref, that is, line 125, and receives the code Ndiv1 132 on line 132, and generates the divided clock f_div on line 145 according to each received code Ndiv1 145. The code Ndiv1 132 includes a set of lower values ​​(4 in the above example) and a set of higher values ​​(5), which causes the corresponding delayed clock signal f_div145 to have a lower time period and a higher time period, so that the average period of the delayed clock signal f_div is equal to the period of the expected fractional output clock. The multi-mode divider 140 can be implemented by existing technical means.

[0054] The digital-to-time converter 150 delays each falling edge (or rising edge) of the divided clock f_div145 received on line 145 according to the amplitude indicated by the corresponding code Ndtc135 received on line 135 to generate a fractional output clock f_frac155 on line 155. In the figure, the digital-to-time converter 150 is shown as delaying the falling edge of the clock signal f_div145. In general, a particular "edge of interest" (whether rising or falling) is delayed according to the corresponding amplitude specified by the code Ndtc135 on line 135, which is well known in the art.

[0055] The duty cycle module 160 generates a fractional output clock fout165 on line 165, and the desired duty cycle of the fractional output clock fout corresponds to the fractional output clock f_frac155 received from line 155. In one embodiment, the duty cycle module 160 works as a frequency division module, and obtains a 50% duty cycle by dividing the frequency of the fractional output clock f_frac155 by an even number, and the integer part 105 and the fractional part 107 are reduced accordingly. The duty cycle module 160 can be implemented by existing technical means.

[0056] Figure 2 is a timing diagram (not to scale), Figure 2 The waveforms generated by the nodes in the open-loop modulator 100 are shown when the fraction is 8.5 and the duty cycle module 160 is divided by 2. Therefore, the code Ndiv1 is the division represented by the codes of the repeating sequence 4, 4, 4 and 5, and therefore, the codes represented by the code Ndtc 135 are 1 / 4, 2 / 4, 3 / 4 and 0. The delayed clock signal f_div 145 represents the corresponding fractional output clock generated by dividing the reference clock signal fref by the code pair received on the line 132, and the time period of the delayed clock signal f_div corresponds to the code Ndiv1, as shown in the time points t251, t254, t257 and t259 in the figure. The expected output signal f_frac 155 describes the falling edge of the delayed clock signal f_div145, which is delayed according to the amplitude represented by the code Ndtc135. The delayed clock signal fout describes the desired output signal with a duty cycle of 50%. The desired fractional output signal fout 165 is obtained by dividing the frequency of the fractional output clock f_frac155 by 2.

[0057] It is understandable that specifying consecutive codes Ndtc 135 with unequal delays may cause nonlinearity in the digital-to-time converter 150. The occurrence of this nonlinearity will be described below with reference to the implementation of the digital-to-time converter in the prior art. Figures 3A-3DAn example of a prior art digital-to-time converter is briefly described.

[0058] 3. Prior Art Digital Time Converter

[0059] Figure 3A is a block diagram of a prior art digital-to-time converter 350 and an associated power supply 320 , which illustrates the linearity phenomenon that occurs with the prior art digital-to-time converter 350 . Figure 3A The illustrated embodiment includes a low dropout voltage regulator (LDO) 320 that provides a stable voltage Vsupply 303 of a required amplitude (hereinafter referred to as “nominal amplitude”) from an input voltage Vin 301 to a prior art digital-to-time converter 350 . Figure 3A Also shown are decoupling capacitors 312 and equivalent series resistors 317 associated with the low dropout linear regulator. Node 399 represents a ground terminal to provide a constant reference potential.

[0060] The digital-to-time converter 350 includes an input buffer 356, a delay generator 360, and an output buffer 370. The delay generator 360 and the output buffer 370 may be considered together as a "delay control module" 380, which is intended to generate a desired fractional output clock.

[0061] Input buffer 356 generates a high intensity clock (full logic level digital signal) on line 357 based on the divided clock f_div345 received from line 345 for use by delay generator 360. Therefore, the output clock of input buffer 356 remains constant relative to the divided clock f_div345.

[0062] Delay generator 360 generates a fractional output clock on line 369, which is a delayed version of the divided clock f_div345 (equivalent to Figure 1 The delay of the edge corresponding to the divided clock f_div 345 is specified by the value represented by the code Ndtc335 received on line 335. The output buffer 370 outputs a high-intensity fractional output clock f_frac355 on line 355 according to the fractional output clock received on line 369. Figure 3B Implementation details of modules 356, 360, and 370 are described.

[0063] Figure 3BThe details of the prior art digital-to-time converter 350 are described. Specifically, the input buffer 356 includes complementary metal-oxide semiconductor (CMOS) inverters 351-1 and 351-2. The output buffer 370 includes CMOS inverters 371-1 and 371-2.

[0064] The delay generator 360 includes an asymmetric inverter 365 (including transistors 361-1, 361-2, a resistor 362, a fixed bias capacitor 364, and a capacitor bank including capacitors 366-1 to 366-N) and a symmetric inverter 368 (including transistors 363-1 and 363-2). Switches 367-1 to 367-N are used to connect or disconnect the corresponding capacitors with the asymmetric inverter 365.

[0065] Capacitors 366-1 to 366-N are collectively referred to as number 366 according to the context, or each of them can be referred to as number 366. Similarly, switches 367-1 to 367-N can be collectively referred to as number 367, or individually referred to as number 367. Throughout the entire content of this application, similar conventions are followed for other modules / components / signals.

[0066] When an all-zero code is received on line 335, the delay provided by asymmetric inverter 365 is not zero, but a fixed offset. This is generally done to avoid non-linearities that may result from delay transitions from an all-zero code to a non-zero code (eg, code Ndtc is '1').

[0067] The difference between the delay when the coded Ndtc is '1' and the delay when the coded Ndtc is all zeros is found to be greater than the difference between the delay when the coded Ndtc is '2' and the coded Ndtc is '1', which in turn is greater than the difference between the delay when the coded Ndtc is '3' and the coded Ndtc is '2', and so on. Therefore, in order to make the delay difference of consecutive coded Ndtc negligible, the above-mentioned fixed offset is added. The fixed offset is achieved by biasing capacitor 364. Therefore, when the coded Ndtc is not all zeros, the biasing capacitor 364 is combined with the selected capacitor 366 to act to achieve the corresponding specified delay. When such non-linearity can be tolerated, the biasing capacitor 364 can be omitted.

[0068] As is well known in the art, one or more capacitors 366 in the capacitor bank are selected according to the code Ndtc, and the RC time constant of the RC circuit composed of the resistor R362 and the selected capacitor 366 determines the slope of the rising edge of the clock signal at the node 359. The switching threshold voltage of the symmetrical inverter is fixed and is designed to be close to the middle voltage between the stable voltage Vsupply 303 and the ground 399.

[0069] Delay generator 360 provides a desired delay to the falling edge of frequency-divided signal f_div 345 , the magnitude of the desired delay being specified by the magnitude represented by code Ndtc.

[0070] The charging current of the selected capacitor 366 may cause the magnitude of the voltage Vsupply 303 at the node 303 to decrease accordingly, thereby causing the voltage Vsupply 303 to fluctuate. As described above, the capacitance value of the selected capacitor 366 is a function of the code Ndtc 335 to achieve the specified delay. Therefore, the charging current (depending on the selected capacitor 366) when the frequency division signal f_div 345 occurs is also a function of the code Ndtc, causing the voltage Vsupply 303 to decrease in magnitude proportional to the magnitude represented by the code Ndtc. This fluctuation in the voltage Vsupply 303 manifests itself as a nonlinearity of the digital-to-time converter 350, as described in detail as follows Figure 3C shown.

[0071] On the other hand, the symmetrical inverter 368 and the inverters 371 - 1 and 371 - 2 make the current drawn from the low dropout linear regulator close to a constant value (substantially fixed amplitude) appear at the edge of the frequency division signal f_div 345 regardless of the amplitude indicated by the code Ndtc.

[0072] Therefore, the current drawn from the LDO can be considered to consist of the following components:

[0073] a fixed current component representing the current drawn by symmetrical inverter 368, offset capacitor 364 (if present), and output buffer 370 (if present); and

[0074] The variable current component represents the current drawn by the components included in the asymmetric inverter 365 (except the bias capacitor 364).

[0075] As mentioned above, the magnitude of the variable current component is determined only by the magnitude of the code Ndtc335.

[0076] Figure 3C3 is a timing diagram (not to scale) illustrating the ripple in the power supply of the prior art digital-to-time converter 350 during steady-state operation (i.e., after the circuit stabilizes within a short period of time after power is applied), and depicts the waveforms / values ​​of the voltage Vsupply 303 and the code Ndtc 335. For ease of understanding, the figure shows the decimal value of the code Ndtc 335. The waveform of the voltage Vsupply 303 is illustrated as the fractional part of 16 / 512. The code Ndtc 335 is illustrated by taking 9 bits as an example.

[0077] It is pointed out here that although Figure 3A A low dropout linear regulator is described as providing a stable voltage for input buffer 356 and delay control module 380, but for simplicity, Figure 3C The waveform of only describes the power supply fluctuation caused by the delay generator 380.

[0078] As is well known in the art, the waveform of the encoded Ndtc 335 follows a sawtooth wave cycle (as shown in time intervals t301-t304, t304-t308, and t308-t310) due to the operation of the accumulator inside the first-order delta-sigma modulator.

[0079] Voltage Vsupply 303 is shown varying between amplitudes V1 and V2 during the sawtooth period of line 335. The largest variations in the amplitude of voltage Vsupply 303 occur at the largest jumps in line 335 (as shown at time instances t304 and t308), ignoring high frequency (but smaller amplitude) fluctuations in voltage Vsupply 303.

[0080] During the time intervals t304-t306 and t308-t309, the magnitude of the voltage Vsupply 303 is restored to about V2 due to the operation of the control loop of the low dropout linear regulator. In other words, since the current drawn from the low dropout linear regulator has an even smaller magnitude for the smaller magnitude of Ndtc 335, the control loop of the low dropout linear regulator is able to restore the voltage Vsupply 303 to the magnitude of V2.

[0081] However, as the amplitude represented by the code Ndtc increases, the amplitude of the voltage Vsupply 303 gradually decreases over time, resulting in an increase in the fluctuation of the voltage Vsupply 303 (as shown in the time intervals t306-t308 and t309-t310). This may be due to the limited bandwidth of the low-dropout linear regulator. For example, at least in some embodiments, the frequency of the frequency-divided signal f_div345 may be much higher than the bandwidth of the low-dropout linear regulator.

[0082] If not corrected, the large fluctuations in voltage Vsupply 303 (approximately V2 minus V1) will cause the voltage Vsupply 303 to have inconsistent amplitudes when the edges of the frequency division signal f_div 345 / 357 occur. Therefore, the code-dependent delay provided by the asymmetric inverter 365 is not an ideal delay, thereby causing nonlinear phenomena in the prior art digital-to-time converter 350 and causing unacceptable jitter in the fractional output clock f_frac 355, which appears on the output clock of the OLM. The variable current component of the current as described above causes all or a large part of the fluctuations (e.g., V2 minus V1).

[0083] The advantages of the present application will become more apparent when compared with prior art solutions for reducing non-linearity of digital-to-time converters. Therefore, the prior art solutions will be briefly described below.

[0084] 4. Existing technical solutions

[0085] Figure 3D is a block diagram illustrating a prior art technique for reducing the nonlinearity of a prior art digital to time converter 350. The digital to time converter 350′ is Figure 3A / 3B corresponds to the prior art digital-to-time converter 350 shown in FIG. 3B and is shown to additionally include a module 360', which is a replica of module 360. As shown in the figure, module 360' includes an asymmetric inverter 365' and a symmetric inverter 368'. Asymmetric inverter 365' includes transistors 361'-1, 361'-2, resistor 362', bias capacitor 364', capacitor group (including capacitors 366'-1 to 366'-N), which is a replica of the capacitor group in asymmetric inverter 365. Symmetric inverter 368' includes transistors 363'-1 and 363'-2 in sequence. Switches 367'-1 to 367'-N are used to connect or disconnect the connection between the respective capacitors and asymmetric inverter 365'. Signal 369' is a virtual signal that may or may not be used further.

[0086] Asymmetric inverter 365' receives the complement 1' of code Ndtc 335 on line 335' (via inverter 373). One or more capacitors 366' in the capacitor bank are selected based on the complement of code Ndtc 335 so that the overall current drawn from the low dropout linear regulator is substantially constant, thereby reducing the nonlinearity of the prior art digital-to-time converter 350'.

[0087] However, in the prior art solution, the total current drawn from the low dropout linear regulator by the delay generator 360 and the module 360' comprises:

[0088] (A) Fixed current components, including:

[0089] (i) The current produced by the symmetrical inverter 368 and the bias capacitor 364 (if present).

[0090] (ii) The current generated by the symmetrical inverter 368' and the bias capacitor 364' (if any).

[0091] (B) Variable current components, including:

[0092] (i) The current consumed by the variable capacitor group (excluding the bias capacitor 364) in the asymmetric inverter 365 is determined by the size of the code Ndtc335.

[0093] (ii) The current consumed by the replica capacitor group (excluding the bias capacitor 364 ′) in the asymmetric inverter 365 ′ is determined by the size of the complement code of the code Ndtc335 .

[0094] Therefore, while the prior art techniques can reduce nonlinearities in the prior art digital-to-time converter 350', the prior art solution results in significant area overhead (primarily due to the need to replicate the capacitor bank) and increased current consumption due to the repetition of the fixed current (the fixed current component (A)(ii) mentioned above).

[0095] Embodiments of the present application overcome the above-mentioned problems, as described below.

[0096] 5. Digital Time Converter

[0097] Figure 4 1 is a block diagram of a digital-to-time converter and related power supply low-dropout linear regulators 420 and 425 implemented according to various aspects of the present application. The digital-to-time converter 150 includes an input buffer 456, a correction controller (CC) 450, a delay control module 480, and a current acquisition module (CDB) 490. The delay control module 480 further includes a delay generator 460 and an output buffer 470. Figure 4 Also shown in FIG. 4 are the decoupling capacitor 412 and the equivalent series resistor 417 associated with the low dropout linear regulator 420. Node 499 represents the ground terminal that provides a constant reference potential. It should be noted that Figure 4 Only components relevant to the understanding of the present application are described. It is understood that the digital-to-time converter 150 and its associated power supply low-dropout linear regulators 420 and 425 may include more than Figure 4 More or fewer modules / components as shown.

[0098] Figure 4 The modules 456, 460, and 470 in FIG. 1 are functionally similar to the modules 456, 460, and 470 in FIG. Figure 3A Modules 356, 360, and 370 in FIG. 1 are functionally identical and are not described in detail here to simplify the description. In addition, signals 457 and 469 are identical to Figure 3A The signals 357 and 369 in FIG. 1 are functionally identical and are not described in detail here to simplify the description. The number of capacitors in the capacitor bank and their amplitudes may be implemented in any suitable manner. For example, the capacitance values ​​may all be the same, or may be related in a unary, binary, or other manner. The generation of the code Ndtc1 135 is consistent with the generation of the corresponding implementation.

[0099] In some embodiments, output buffer 470 may be omitted, in which case signal 469 is converted to fractional clock f_frac 155 .

[0100] LDO regulator 425 provides a regulated supply voltage Vsupply-2 409 from an input voltage Vin received on line 401. LDO regulator 420 operates to provide a regulated supply voltage Vsupply 403 from an input voltage Vin 401. Voltage Vin 401 represents a DC voltage source that provides input voltage to LDO regulators 420,425.

[0101] Although the present embodiment is described exemplarily with a low dropout linear regulator 420 as the power source, various aspects of the present application are also applicable to any linear or switching regulator that provides a regulated voltage on line 403, which will be apparent to technical practitioners after reading the present application.

[0102] The correction controller 450 controls the input of the current acquisition module 490 so that the current acquisition module 490 compensates for the variable current component obtained from the power supply 420 to ensure that a constant current can be obtained even with unequal amplitudes of Ndtc135. The correction controller 450 forwards the code Ndtc135 to the delay generator (460) via line 454. The correction controller 450 extracts some of the most significant bits (MSBs) from the code Ndtc135, which are specified by the input bits_control 445 received from line 445, and provides the above-extracted most significant bits on line 452. The inverter 453 inverts each bit received from the line 452. For simplicity, only one inverter 453 is shown here. Therefore, the code Mcdb456 represents the complement of the corresponding bit on line 452.

[0103] The input bits_control 445 can be configured by the user in a corresponding manner. Alternatively, the amplitude of the input bits_control 445 can also be read from the non-volatile memory of the open-loop modulator 100 in a known manner. In an exemplary embodiment, the Ndtc135 width is 9 bits, and the input bits_control 445 is equal to 4. Therefore, the complement code Mcdb456 has a width of 4 bits.

[0104] Currents 404-1, 404-2, 404-3 represent the currents obtained in the corresponding modules 460, 470, 490 when the corresponding inverter switches state within the module (i.e., when the edge of the delayed clock signal f_div 145 occurs). As described above, the current I-dg 404-1 includes a fixed current component and a variable current component. The current I-ob 404-2 is a fixed amplitude. The current obtained by the correction controller 450 may be insignificant compared to the current obtained by the modules 480 and 490, and therefore is ignored when quantifying the overall current obtained from the low dropout linear regulator 420.

[0105] The current acquisition module 490 operates to acquire (suck) a current 404-3 (hereinafter referred to as the correction current) from the power supply LDO 420, whose amplitude is determined only by the amplitude indicated by the input code Mcdb 456 received on line 456. In other words, the current acquisition module 490 does not acquire any fixed current component other than the amplitude indicated by the code Mcdb 456 on line 456 from the LDO 420, which is contrary to the fixed current component (A)(ii) of the above-mentioned prior art solution. The current acquisition module 490 operates to ensure that the sum of the correction current and the variable current component acquired by the asymmetric inverter in the delay generator 460 is constant regardless of the amplitude indicated by the code Ndtc135. For example, the larger the amplitude of the current 404-1, the smaller the amplitude of the current 404-3, and vice versa.

[0106] It is noted that even if only one low dropout linear regulator is used to provide the regulated voltage for modules 456 and 480, the current acquisition module 490 is different from the conventional method (such as Figure 3A The nonlinearity contributed by the delay control module 480 can also be minimized by comparing the input buffer 456 to the input buffer 456. A separate low dropout linear regulator provides an additional benefit that can further reduce the nonlinearity caused by the additional contribution of the input buffer 456.

[0107] The detailed implementation of the current acquisition module 490 in the embodiment of the present application is described as follows.

[0108] 6. Current acquisition module

[0109] Figure 5 4 shows a specific circuit diagram of a current acquisition module 490 in an embodiment of the present application. The current acquisition module 490 uses a programmable M-bit current digital-to-analog converter to acquire (absorb) current according to the "M"-bit logic value received on the 456 line. The digital-to-analog converter 490 includes transistors 520, 530-1 to 530-M, switches 525-1 to 525-M and a programmable current source 510, which provides a current amplitude of i-ref. Node 499 represents a ground terminal that provides a constant reference potential. It should be noted that Figure 5 Only components relevant to understanding the present application are shown. It is understood that the digital-to-analog converter 490 may include more Figure 5 The voltage Vbias 501 is the bias voltage of the current source 510 and can be generated inside the open-loop modulator 100 by other power sources except the low-dropout linear regulator 420 . The current amplitude i-ref 512 provided by the programmable current source 510 is controlled by the configuration input 511 .

[0110] In this embodiment, the number of transistors M is equal to the value specified by the control bit bits_control on line 445. The present application points out that the sizes (channel width and channel length values) of transistors 530-1 to 530-M can be related to each other in a manner related to the capacitance values ​​of the capacitors in the capacitor bank. For example, if the capacitance values ​​are related to each other in a binary manner, the sizes of transistors 530-1 to 530-M are also binary weighted. At least, the sizes of the transistors may be related so that the current generated by the current acquisition module 490 is inversely proportional to the variable current component generated by the delay generator 460, without considering the exact nature of the ratio.

[0111] Each switch 525 is used to connect (disconnect) the corresponding transistor 530 and the voltage Vsupply403 of the node 403, thereby turning on (off) the corresponding transistor. Each switch is controlled to be turned on or off by the logic level corresponding to the corresponding bit of the code Mcdb456. It can be seen that the opening and closing of the switch 525-1 is controlled by the code Mcdb456[0]. In one embodiment, when the corresponding bit of Mcdb456[0] is logically high, the switch 525 is closed, otherwise it is opened. When the switch 525-1 is closed, the amplitude of the transistor 530-1 is proportional to the current amplitude i-ref512 provided by the programmable current source 510, and the ratio depends on the specific implementation of the digital-to-analog converter 490.

[0112] The amplitude provided by the programmable current source 510 is configured to obtain the desired I-1 to IM current value. The programmable current source 510 can be configured for a specific operating frequency range of the fractional output clock f_frac155 supported by the open-loop modulator 100 .

[0113] It is common knowledge in the art that the open-loop modulator 100 generally needs to be designed to support a specific operating frequency range of the fractional output clock f_frac155. In one embodiment, the current generated by the delay generator 460 is measured by simulating the steady-state operation of the delay generator 460 in each operating frequency range of the fractional output clock f_frac155 supported by the open-loop modulator 100. Considering the process inflection point of the integrated circuit (IC) and the calibration of the digital-to-analog converter 490, the corresponding magnitude of the current amplitude i-ref512 is stored in a look-up table (LUT) for each range of the fractional output clock f_frac155.

[0114] For example, assuming that the configuration input 511 of the control source 510 is 4 bits, the total operating frequency range of the fractional output clock f_frac 155 is subdivided into 16 ranges, and according to the desired operating frequency range of the clock f_frac 155 , one of the 16 possible values ​​of the current amplitude i-ref 512 can be configured to be provided by the current source 510 .

[0115] The lookup table may be stored in a non-volatile memory of the open-loop modulator 100. The configuration input 511 corresponding to the operating frequency range of the fractional output clock f_frac155 may be provided to the current source 510 by existing technical means. For example, when the open-loop modulator 100 is powered on, the first logic circuit of the open-loop modulator 100 may determine an appropriate configuration input value and store the value in a register, which in turn is read by a second logic circuit of the open-loop modulator 100 (e.g., included in the correction controller 450) to configure the current acquisition module 490. Alternatively, the user may determine the value of the configuration input 511 by looking up the lookup table and program the register with the appropriate configuration input value by a corresponding method.

[0116] Although the illustrative embodiment describes the use of 4 MSBs of Ndtc 135 to operate the current acquisition module 490, in general, when an N-bit digital-to-time converter is used, all or only a portion of the “N” MSBs may be used to control the operation of the current acquisition module 490, as will be apparent to a skilled practitioner. In addition, a smaller number of MSBs (e.g., 4 of the 9 bits in the illustrative embodiment) may reduce programming complexity and simplify the implementation of the current acquisition module 490 while fully complementing the variable current component extracted from the low dropout linear regulator 420.

[0117] It will be appreciated that the above described technique using a DAC provides a solution that may be insensitive to small changes in programmed DAC current (e.g., + / - 10% changes), so a rough calibration of the DAC may be sufficient to achieve the target jitter performance.

[0118] Furthermore, while the current acquisition module 490 in the illustrative embodiment is shown as a current digital-to-analog converter implementation, it will be apparent to a skilled practitioner who has read the present application that various aspects of the present application may be equally well applied when alternative techniques (and / or alternative implementations of the present digital-to-analog converter) are employed to sink current from the low dropout linear regulator 420.

[0119] For example, different or more complex current acquisition modules (circuits) may be used to supplement the above variable current components. In addition, although the illustrative embodiments describe a first-order delta-sigma modulator, the present application may also be well applied to a high-order delta-sigma modulator with corresponding changes to the digital-to-time converter and / or the current acquisition module, which should be relatively clear to those skilled in the art through the disclosure of the present application.

[0120] Specifically, when the change in the power supply voltage has a nonlinear relationship with the amplitude change of the encoded Ndtc 135 (e.g., a quadratic or exponential dependence), a lookup table can be used to store the correspondence between such a change and the required digital-to-analog converter response (e.g., based on the current amplitude I-ref 512, the encoded Mcdb456, etc.).

[0121] Although the exemplary embodiment shows a specific technique for determining and configuring the magnitude of the current amplitude i-ref 512, it is apparent that other embodiments may employ different techniques, as will be apparent to a skilled practitioner upon reading the disclosure of this application.

[0122] Next, it will be described how the current acquisition module 490 reduces nonlinearity in the digital-to-time converter 150 according to aspects of the present application.

[0123] 7. Reduce the nonlinearity of digital-to-time converters

[0124] Figure 6 1 is a timing diagram (not to scale), which describes the reduction of the power supply voltage ripple in the steady-state operation of the digital-to-time converter 150 in the embodiment of the present application, and describes the waveforms / values ​​of the voltage Vsupply 403, the code Ndtc135, the amplitude I-cdb 404-3 of the correction current, and the extracted current I-tot 404. Although the embodiment of the present application only describes the digital-to-time converter 150 for delaying the falling edge of the delayed clock signal f_div145, it is clear to those skilled in the art that, according to the content disclosed in the present application, it is also applicable to delaying the rising edge.

[0125] The current I-cdb404-3 drawn from the low-dropout linear regulator 420 by the current acquisition module 490 is shown to be inversely proportional to the code Ndtc. It can be seen that during the time intervals t601-t604 and t604-t608, when the magnitude of Ndtc135 increases, the current I-cdb 404-3 drawn from the current acquisition module 490 shows a decreasing trend. As described above, regardless of the magnitude of Ndtc135, the current I-tot 404 extracted from the low-dropout linear regulator 420 remains substantially unchanged, although high-frequency ripple may still exist.

[0126] Specifically, the magnitude of the total current obtained by the delay generator 460 and the current acquisition module 490 from the low dropout linear regulator 420 is equal to the sum of the following:

[0127] A. The magnitude of the correction current I-cdb 404-3 plus the magnitude of the variable current component consumed by the delay generator 460. And

[0128] B. The magnitude of the fixed current component produced by the symmetrical inverter of the asymmetrical inverter and (if any) the bias capacitor.

[0129] The magnitude of the total current provided from the delay generator 460 and the current acquisition module 490 to the low dropout linear regulator 420 in the form of a fixed current component and a variable current component includes:

[0130] (A) The fixed current component generated by the symmetrical inverter and the bias capacitor of the asymmetrical inverter. And

[0131] (B) Variable current components include:

[0132] (i) the current in the variable capacitor bank of the asymmetric inverter during operation, the magnitude of which is determined solely by the magnitude of the code Ndtc135; and

[0133] (ii) The magnitude consumed by the current acquisition module 490 is determined only by the size of the code Mcdb456.

[0134] It can be appreciated that by adding a fixed current component to the variable current component, ensuring that a fixed amount of current is drawn from the power supply, the generation of ripple can be reduced or avoided. This technique also results in Figure 3D According to various aspects of the present application, the prior art solution (see Figure 3D ) no longer occurs. In addition, the use of a digital-to-analog converter can reduce at least the area overhead associated with the use of a replicated capacitor bank in the prior art digital-to-time converter 350'.

[0135] It should be noted that, although the current I-tot 404 extracted from the low-dropout linear regulator 420 is drawn as a straight line for ease of explanation, it can be understood that, in practice, although there is still a non-zero difference between the extracted currents for unequal codes Ndtc135, this difference has been greatly reduced compared to the prior art. This non-zero difference may depend on factors such as the bandwidth of the low-dropout linear regulator 420, the operating frequency range of the divided output clock f_frac, the fractional number achieved, and the like.

[0136] Since the amplitude of the voltage Vsupply403 at the node 403 hardly changes due to the delay generator 480 processing the edge change of the delayed clock signal f_div145 regardless of the amplitude represented by the encoding Ndtc135, in the digital time converter 150, the delay of the edge of interest of the delayed clock signal f_div145 implemented by the delay generator 480 is basically close to the ideal delay, thereby significantly improving the linearity of the digital time converter 150.

[0137] In addition to using the current acquisition module 490, in one embodiment, the capacitance value of the decoupling capacitor 412 is selected to be as large as possible, that is, within the area constraint of the chip. For example, the capacitance value of the decoupling capacitor 412 can range from 20pF to 40pF to partially reduce the nonlinearity of the open-loop modulator caused by the ripple in the voltage Vsupply403, and the operating clock frequency range of the open-loop modulator is configured to be 200-1400 MHz.

[0138] In this way, various aspects of the present invention reduce digital-to-time converter nonlinearities caused by unequal corresponding delays specified by subsequent input codes. The digital-to-time converter 150 described above may be integrated into a larger device or system, as briefly described below.

[0139] 8. System

[0140] Figure 7 7 is a block diagram of an example system including a phase-locked loop implemented according to various aspects of the present application described in detail above. The illustrated system 700 includes SyncE (Synchronous Ethernet) timing cards 710, 720 and line cards 1 to N, of which only two line cards 730 and 750 are shown for simplicity. Line card 730 includes a jitter attenuation module 740 and a synchronous PHY transmitter 745. Line card 750 includes a jitter attenuation module 760 and a synchronous PHY transmitter 765. Figure 7The components in can operate in accordance with the synchronous Ethernet SyncE network standard. As is well known in the art, SyncE is a physical layer PHY-based technology for achieving synchronization in a packet-based Ethernet network. The synchronization clock signal transmitted through the physical layer should be traceable to an external master clock (for example, from a timing card such as timing card 710 or timing card 720). Therefore, the Ethernet data packet is re-timed relative to the master clock and then transmitted at the physical layer. Therefore, the data packet (for example, on lines 731, 751) is re-timed and transmitted without any timestamp information being recorded in the data packet. These data packets may be generated by corresponding applications, such as Internet Protocol Television (IPTV), Voice over Internet Protocol (VoIP), etc.

[0141] Thus, line card 730 receives a packet on line 731 and forwards the packet on output 746 after the packet is re-clocked (synchronized) with the master clock. Similarly, line card 750 receives a packet on line 751 and forwards the packet on output 766 after the packet is re-clocked (synchronized) with the master clock.

[0142] The master clock (711 / clock 1) is generated by timing card 710. Timing card 720 generates a redundant clock (721 / clock 2) that is used by line cards 730 and 750 when master clock 711 fails. Master clock 711 and redundant clock 721 are provided to each line card 730 and 750 through a backplane (indicated by numeral 770).

[0143] In the line card 730, the jitter attenuation module 740 includes the phase-locked loop 110 and the open-loop modulator 100 described in detail above (such as Figure 1 ), and receives clocks 711 and 721. Phase locked loop 740 generates an output clock 741 that is used to synchronize (re-clock) data packets received on line 731 and forwarded as re-clocked data packets on line 746.

[0144] Similarly, in the line card 750, the jitter attenuation module 760 also includes the phase-locked loop 110 and the open-loop modulator 100 described in detail above (such as Figure 1 ), and receives clocks 711 and 721. Phase locked loop 760 generates an output clock 761 that is used to synchronize (re-clock) data packets received on line 751 and forwarded as re-clocked data packets on line 766.

[0145] 9. Conclusion

[0146] References in this specification to "one embodiment," "an embodiment," or similar expressions mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, appearances of the phrases "in one embodiment," "in an embodiment," and similar expressions throughout this specification may, but do not necessarily, refer to the same embodiment.

[0147] And in Figure 1 , 3A In the examples of 3B, 3D, 4, 5 and 7, although the terminals / nodes are shown as being directly connected (i.e., "connected to") various other terminals, it should be understood that additional components (such as components suitable for a particular environment) may also be present in the line, and the connections can be considered to be "electrically coupled" to the terminals of the same connection accordingly.

[0148] In this application, the power supply and ground terminals are referred to as constant reference potentials.

[0149] Although various embodiments of the present application have been described above, it should be understood that they are only provided by way of example rather than limitation. Therefore, the breadth and scope of the present application should not be limited by any of the above embodiments, but should only be defined according to the following claims and their equivalents.

Claims

1. An open-loop modulator circuit for generating a fractional output clock, wherein the frequency of the fractional output clock is a desired fraction of a reference clock, wherein: The expected fraction includes an integer part and a decimal part, and the open-loop modulator circuit includes: a delta-sigma modulator for receiving the expected score and generating a corresponding first code sequence and a second code sequence; wherein the first code sequence includes a set of lower values ​​and a set of upper values, and a common average of the set of lower values ​​and the set of upper values ​​is used to represent the expected score; a first frequency divider, configured to receive the reference clock and each first code of the first code sequence, and generate a frequency-divided signal according to the reference clock and each first code of the first code sequence; wherein a period of the frequency-divided signal is a multiple of the reference clock period, and the multiple is a value represented by each first code in the first code sequence; A digital time converter, used to generate the fractional output clock according to the frequency-divided signal; wherein the digital time converter comprises: a delay generator, powered by a power supply, for receiving the frequency-divided signal and delaying an edge of interest of the frequency-divided signal according to a corresponding second code in the second code sequence, so as to generate the fractional output clock; wherein the current obtained by the delay generator from the power supply includes a fixed current component and a variable current component, the amplitude of the fixed current component is not affected by the corresponding second code in the second code sequence, and the amplitude of the variable current component is determined only by the amplitude represented by the corresponding second code in the second code sequence; A current acquisition module is used to acquire a correction current from the power supply; wherein the magnitude of the correction current is determined only by the complement of the corresponding second code in the second coding sequence; the current acquisition module is used to ensure that the sum of the correction current and the variable current component is not affected by the corresponding second code in the second coding sequence and remains constant; the total current acquired from the power supply by the delay generator and the current acquisition module is equal to the sum of the sum and the fixed current component.

2. The open-loop modulator circuit according to claim 1, wherein: The current acquisition module is a current digital-to-analog converter, which receives the second code's complement as input and acquires the correction current from the power supply to convert the second code's complement into a current.

3. The open-loop modulator circuit according to claim 2, characterized in that The digital-to-time converter comprises: an input buffer for receiving the frequency-divided signal and generating a buffered signal, the buffered signal being provided to the delay generator; and an output buffer for receiving the fractional output clock and generating a buffered fractional output clock; wherein the delay generator comprises: an asymmetric inverter for obtaining the variable current component from the power supply; and A symmetrical inverter is used to obtain at least a part of the fixed current component from the power supply.

4. The open-loop modulator circuit according to claim 2, wherein: The delta-sigma modulator is a first-order delta-sigma modulator.

5. The open-loop modulator circuit according to claim 4, characterized in that The complement of the second encoding includes a plurality of bits, wherein the magnitude of the correction current is proportional to a value represented by a subset of the plurality of bits; the subset of bits includes a preset number of most significant bits of the plurality of bits.

6. The open-loop modulator circuit according to claim 5, characterized in that The current digital-to-analog converter comprises: A programmable current source, used to obtain a reference current from a bias voltage source, wherein a first terminal of the programmable current source is connected to the bias voltage source; a first transistor, wherein a first current terminal of the first transistor is connected to a control terminal of the first transistor, and a second current terminal of the first transistor is connected to a constant reference potential; wherein a second terminal of the programmable current source is connected to the first current terminal of the first transistor; Multiple switches; and A plurality of transistors, whose control terminals are connected to each other and to the control terminal of the first transistor, wherein the first current terminal of each of the plurality of transistors is connected to the power supply through a corresponding switch in the plurality of switches, and the second current terminal of each transistor is connected to the constant reference potential; each switch connects the corresponding transistor to the power supply when closed, and disconnects the corresponding transistor from the power supply when opened; wherein each switch is closed or opened by a corresponding bit of the bit subset; and the plurality of transistors can be used to obtain the correction current from the power supply.

7. The open-loop modulator circuit according to claim 6, characterized in that The open-loop modulator circuit includes a lookup table, which includes reference currents corresponding to various operating frequency ranges of the fractional output clock; wherein the amplitude of the reference current is configured according to the lookup table.

8. A digital-to-time converter, characterized in that: The digital time converter is used to generate a fractional output clock from a frequency-divided signal according to a delayed code sequence, and the digital time converter comprises: a delay generator, powered by a power supply, for receiving the divided frequency signal and delaying an edge of interest of the divided frequency signal according to each delay code of the delay code sequence to generate the fractional output clock, wherein the current obtained by the delay generator from the power supply comprises a fixed current component and a variable current component, the amplitude of the fixed current component remains unchanged regardless of the value represented by the corresponding delay code of the delay code sequence; and the amplitude of the variable current component is determined only by the amplitude represented by the corresponding delay code of the delay code sequence; A current acquisition module is used to extract a correction current from the power supply, and the amplitude of the correction current is determined only by the complement of the corresponding delay code of the delay code sequence; wherein the current acquisition module is used to ensure that the sum of the correction current and the variable current component obtained by the delay generator remains unchanged without being affected by the amplitude represented by the corresponding delay code; the total current obtained from the power supply by the delay generator and the current acquisition module is equal to the sum of the sum and the fixed current component.

9. The digital-to-time converter according to claim 8, characterized in that The current acquisition module is a current digital-to-analog converter, which receives the complement code and acquires the correction current to convert the complement code into a current.

10. The digital-to-time converter according to claim 9, characterized in that The digital-to-time converter comprises: an input buffer for receiving the divided signal and generating a buffered signal, wherein the buffered signal is provided to the delay generator; and an output buffer for receiving the fractional output clock and generating a buffered fractional output clock; wherein the delay generator comprises: an asymmetric inverter for obtaining the variable current component from the power supply; and A symmetrical inverter is used to obtain at least a part of the fixed current component from the power supply.

11. The digital-to-time converter according to claim 10, characterized in that The delay-encoded complement includes a plurality of bits, wherein the magnitude of the correction current is proportional to a value represented by a subset of the plurality of bits; wherein the subset of bits includes a predetermined number of most significant bits of the plurality of bits.

12. The digital-to-time converter according to claim 11, characterized in that The digital-to-time converter comprises: A programmable current source, used to obtain a reference current from a bias voltage source, wherein a first terminal of the programmable current source is connected to the bias voltage source; a first transistor, wherein a first current terminal of the first transistor is connected to a control terminal of the first transistor, and a second current terminal of the first transistor is connected to a constant reference potential; wherein a second terminal of the programmable current source is connected to the first current terminal of the first transistor; Multiple switches; and A plurality of transistors, whose control terminals are connected to each other and to the control terminal of the first transistor, wherein the first current terminal of each of the plurality of transistors is connected to the power supply through a corresponding switch in the plurality of switches, and the second current terminal of each transistor is connected to the constant reference potential; each switch connects the corresponding transistor to the power supply when closed, and disconnects the corresponding transistor from the power supply when opened; wherein each switch is closed or opened by a corresponding bit of the bit subset; and the plurality of transistors can be used to obtain the correction current from the power supply.

13. The digital-to-time converter according to claim 12, wherein: The digital-to-time converter comprises a lookup table, wherein the lookup table comprises reference currents corresponding to respective operating frequency ranges of the fractional output clock; wherein the amplitude of the reference current is configured according to the lookup table.

14. A system, characterized in that: The system comprises: a line card, configured to receive a data packet, re-time the data packet according to a selected clock, and transmit the re-timed data packet; A first timing card, used to generate a first clock; and power supply; Wherein, the line card includes: a phase-locked loop, configured to receive the first clock and generate a reference clock locked to the first clock; and an open-loop modulator, configured to receive the reference clock and generate a fractional output clock having a frequency that is a desired fraction of the reference clock, wherein the open-loop modulator comprises: a delta-sigma modulator for receiving the expected score and generating a corresponding first code sequence and a second code sequence; wherein the first code sequence includes a set of lower values ​​and a set of upper values, and a common average of the set of lower values ​​and the set of upper values ​​is used to represent the expected score; a first frequency divider, configured to receive the reference clock and each first code of the first code sequence, and generate a frequency-divided signal according to the reference clock and each first code of the first code sequence; wherein a period of the frequency-divided signal is a multiple of the reference clock period, and the multiple is a value represented by each first code in the first code sequence; A digital time converter, used to generate the fractional output clock according to the frequency-divided signal; wherein the digital time converter comprises: a delay generator, powered by a power supply, for receiving the frequency-divided signal and delaying an edge of interest of the frequency-divided signal according to a corresponding second code in the second code sequence, so as to generate the fractional output clock; wherein the current obtained by the delay generator from the power supply includes a fixed current component and a variable current component, the amplitude of the fixed current component is not affected by the corresponding second code in the second code sequence, and the amplitude of the variable current component is determined only by the amplitude represented by the corresponding second code in the second code sequence; A current acquisition module is used to acquire a correction current from the power supply; wherein the magnitude of the correction current is determined only by the complement of the corresponding second code in the second coding sequence; the current acquisition module is used to ensure that the sum of the correction current and the variable current component is not affected by the corresponding second code in the second coding sequence and remains constant; the total current acquired from the power supply by the delay generator and the current acquisition module is equal to the sum of the sum and the fixed current component.

15. The system of claim 14, wherein: The current acquisition module is a current digital-to-analog converter, which receives the second code's complement as input and acquires the correction current from the power supply to convert the second code's complement into a current.

16. The system of claim 15, wherein: The digital-to-time converter comprises: an input buffer for receiving the frequency-divided signal and generating a buffered signal, the buffered signal being provided to the delay generator; and an output buffer for receiving the fractional output clock and generating a buffered fractional output clock; wherein the delay generator comprises: an asymmetric inverter for obtaining the variable current component from the power supply; and A symmetrical inverter is used to obtain at least a part of the fixed current component from the power supply.

17. The system of claim 15, wherein: The delta-sigma modulator is a first-order delta-sigma modulator.

18. The system of claim 17, wherein: The complement of the second encoding includes a plurality of bits, wherein the magnitude of the correction current is proportional to a value represented by a subset of the plurality of bits; the subset of bits includes a preset number of most significant bits of the plurality of bits.

19. The system of claim 18, wherein: The current digital-to-analog converter comprises: A programmable current source, used to obtain a reference current from a bias voltage source, wherein a first terminal of the programmable current source is connected to the bias voltage source; a first transistor, wherein a first current terminal of the first transistor is connected to a control terminal of the first transistor, and a second current terminal of the first transistor is connected to a constant reference potential; wherein a second terminal of the programmable current source is connected to the first current terminal of the first transistor; Multiple switches; and A plurality of transistors, whose control terminals are connected to each other and to the control terminal of the first transistor, wherein the first current terminal of each of the plurality of transistors is connected to the power supply through a corresponding switch in the plurality of switches, and the second current terminal of each transistor is connected to the constant reference potential; each switch connects the corresponding transistor to the power supply when closed, and disconnects the corresponding transistor from the power supply when opened; wherein each switch is closed or opened by a corresponding bit of the bit subset; and the plurality of transistors can be used to obtain the correction current from the power supply.

20. The system of claim 19, wherein: The open-loop modulator circuit includes a lookup table, which includes reference currents corresponding to various operating frequency ranges of the fractional output clock; wherein the amplitude of the reference current is configured according to the lookup table.

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