Semiconductor power device with better FOM value and manufacturing method thereof

Abstract

The invention discloses a semiconductor power device with a better FOM value and a manufacturing method thereof, the semiconductor power device comprises a substrate, an epitaxial layer, a body region, a JFET region, a cut-off gate, a concave source contact region and a source electrode structure, the epitaxial layer grows on the upper surface of the substrate, the body region is arranged in the epitaxial layer, spaced source regions are arranged in the body region, and the JFET region is arranged in the cut-off gate. A base region is arranged between the adjacent source regions, and the base region is connected with the opposite side edges of the source regions; the JFET region is arranged in the epitaxial layer, the JFET region is connected with the opposite side edges of the body region, and the JFET region has set doping concentration; the cut-off gate is provided with openings above the JFET region and above the source region and the base region, the cut-off gate completely covers the upper surface of the body region, and the peripheral side of the cut-off gate is covered with an isolation layer; the concave source contact region is formed above the source region and above the base region of which the upper structure is etched; and the source electrode structure is filled in the concave source contact region and the peripheral side edge of the isolation layer. According to the invention, the conduction loss and the switching loss can be effectively reduced.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a semiconductor power device with a better FOM value and a manufacturing method thereof. Background Art

[0002] As an important semiconductor device, power MOSFET is widely used in power management, motor drive and other fields. With the increasing demand for miniaturization and high efficiency of electronic devices, the development of power MOSFET is also facing higher challenges. In order to meet these needs, researchers are constantly exploring new design concepts and technical means to improve the performance indicators of power MOSFET, such as higher power density, lower specific on-resistance, lower switching loss and better gate oxide protection. These improvements can not only improve the working efficiency of the device, but also extend its service life, so as to play a greater role in practical applications. FOM is a comprehensive indicator used to measure the performance of power devices in specific applications, especially in terms of loss description. The smaller the FOM value, the lower the conduction loss and switching loss of the device, and the better the overall performance of the device in power applications.

[0003] In the existing power MOSFET technology, common design schemes mainly include traditional planar MOSFET and trench MOSFET. For traditional planar MOSFET, a standard planar structure is usually adopted to improve device performance by optimizing material selection and process parameters. For example, by optimizing gate length and width, parasitic capacitance is reduced, thereby reducing switching losses. Another common method is to use an epitaxial layer with a high doping concentration to reduce on-resistance.

[0004] Although the above method improves the performance of power MOSFET to a certain extent, there are still some obvious defects. First, the traditional planar MOSFET has a large gate width, resulting in a high parasitic gate-drain capacitance, which increases the switching loss. Secondly, the large size of the source contact area makes the cell pitch wide and the chip area utilization rate is not high, which in turn limits the further reduction of the on-resistance. Therefore, how to effectively reduce the switching loss and conduction loss while maintaining high power density has become a key issue that needs to be solved urgently. Summary of the invention

[0005] In order to effectively reduce conduction losses and switching losses, the present application provides a semiconductor power device with a better FOM value and a manufacturing method thereof.

[0006] In a first aspect, the present application provides a semiconductor power device with a better FOM value using the following technical solution: A semiconductor power device with a better FOM value, comprising: a substrate having an epitaxial layer grown on its upper surface; A body region, which is separated and arranged in the epitaxial layer, wherein the body region is provided with spaced-apart source regions, and a base region is provided between adjacent source regions, and the base region is connected to opposite sides of the source region; A JFET region, disposed in the epitaxial layer, the JFET region is in contact with opposite sides of the body region, and the JFET region has a set doping concentration; A cut-off gate is formed with openings above the JFET region and above the source region and the base region, the cut-off gate completely covers the upper surface of the body region, and the peripheral side of the cut-off gate is covered with an isolation layer; A recessed source contact region is formed above the source region and above the base region where the upper structure is etched; The source structure is filled in the recessed source contact area and the peripheral side of the isolation layer.

[0007] By adopting the above technical solution, the design of the concave source contact area reduces the area occupied by the source contact, increases the proportion of the chip current flowing through the area, and makes better use of the chip area. The source contact size is reduced, and the cell unit size (Cell Pitch) can be made smaller. For the same chip area, a smaller cell unit size can connect more units in parallel, the cell and channel unit density is higher, and the on-resistance is greatly reduced. At the same time, the split gate design makes the gate width smaller, the parasitic gate-drain capacitance Cgd is greatly reduced, and the switching loss is greatly reduced. The combination of these two designs significantly improves the overall performance of the device, and the Ron,sp*Qgd performance is greatly improved.

[0008] Optionally, the opening above the JFET region is filled with a dielectric material, and polysilicon is backfilled above the dielectric material so that the polysilicon and the cut-off gate form an antenna-shaped gate structure.

[0009] By adopting the above technical solution, the antenna-shaped gate structure can effectively reduce the electric field concentration phenomenon under the gate. This design helps to reduce the electric field strength (EOX) of the gate oxide (Gate Oxide, i.e., the gate oxide layer), reduce the influence of the gate oxide on the reverse large voltage, play a role in protecting the gate oxide, and improve the reliability of the device.

[0010] Optionally, the dielectric material is one of SiO2, SiN, Al2O3, TiO2, HfO2 and MoO2.

[0011] By adopting the above technical solutions, these materials have good insulation and stability, can effectively isolate the gate from other areas, reduce parasitic effects, and further improve the reliability and performance of the device.

[0012] Optionally, a gate oxide layer is provided between the cut-off gate and the upper surface of the epitaxial layer, and the thickness of the dielectric material is greater than the thickness of the gate oxide layer.

[0013] By adopting the above technical solution, the gate oxide layer between the gate and the epitaxial layer can effectively isolate the gate and the epitaxial layer to prevent a short circuit between the gate and the epitaxial layer. At the same time, the thickness of the dielectric material is greater than the thickness of the gate oxide layer, which can further enhance the insulation performance above the JFET region and reduce the influence of the gate electric field on the gate oxide, thereby improving the reliability and stability of the device.

[0014] Optionally, the upper surface of the recessed source contact region is covered with a metal interconnection layer.

[0015] By adopting the above technical solution, the source resistance can be significantly reduced, the conductive performance of the device can be improved, and the heat dissipation capacity of the device can be enhanced, thereby further reducing the operating temperature of the device and improving the reliability and stability of the device.

[0016] Optionally, a passivation layer is provided on the upper surface of the source structure, the thickness of the passivation layer is 0.1 μm-20 μm, a resin layer is provided on the upper surface of the passivation layer, the thickness of the resin layer is 1 μm-50 μm, and a drain structure is provided on the lower surface of the substrate.

[0017] By adopting the above technical solutions, the reliability and packaging performance of the device are improved. The passivation layer effectively prevents the external environment from corroding the inside of the device, while reducing surface defects and improving the electrical performance of the device. The resin layer enhances the mechanical strength of the device and reduces stress damage during the packaging process. The setting of the drain structure ensures good heat dissipation performance of the device and prolongs its service life.

[0018] The second aspect of the present application provides a semiconductor power device with a better FOM value using the following technical solution: A method for manufacturing a semiconductor power device with a better FOM value comprises the following steps: S10, providing a substrate, and growing an epitaxial layer on the upper surface of the substrate.

[0019] S20, doping ions into the epitaxial layer to form a plurality of separated body regions.

[0020] S30, forming spaced-apart source regions in the same body region by ion doping.

[0021] S40, doping ions into the body region to form a base region connected to opposite sides of the source region.

[0022] S50, doping ions into the epitaxial layer to form a JFET region connected to opposite sides of the body region, wherein the JFET region has a set doping concentration.

[0023] S60, depositing polysilicon on the upper surface of the epitaxial layer, removing the polysilicon above the JFET region and above the source region and the base region to form a cut-off gate, wherein the cut-off gate can completely cover the upper surface of the body region.

[0024] S70, forming an isolation layer around the polysilicon.

[0025] S80, etching the upper structure of the base region to form a concave source contact region above the base region and the source region; S90, filling the recessed source contact area and the surrounding side of the isolation layer with metal to form a source structure.

[0026] By adopting the above technical solutions, the design of the concave source contact area reduces the area occupied by the source contact, increases the area of ​​the chip through which the current flows, and makes better use of the chip area, thereby reducing the on-resistance. The cut-off gate design makes the gate width smaller, significantly reducing the parasitic gate-drain capacitance Cgd, that is, the reverse transfer capacitance (Miller capacitance Crss), thereby greatly reducing the switching loss. Combining these two designs, the overall FOM value of the device is greatly improved.

[0027] Optionally, after step S60, the following steps may be further performed: S61, filling the opening of the cut-off gate with a dielectric material; S62, backfilling polysilicon on the dielectric material; S63, etching the polysilicon above the center of the dielectric material to form an antenna-shaped gate structure.

[0028] Optionally, the dielectric material is one of SiO2, SiN, Al2O3, TiO2, HfO2 and MoO2; Before step S60, the method further includes: S59, forming a gate oxide layer on the upper surface of the epitaxial layer; The thickness of the dielectric material is greater than the thickness of the gate oxide layer.

[0029] Optionally, after step S70, the method further includes: S71: forming a mask on the upper surface of the isolation layer, photolithography and etching the isolation layer to expose the upper surface of the base region and a portion of the upper surface of the source region; S72, forming a sidewall structure on the basis of the mask, wherein the sidewall structure covers the upper surface of the base region, part of the upper surface of the source region, and the peripheral sides of the mask and the isolation layer; S73, removing the sidewall structure on the upper surface of the mask and the sidewall structure on the upper surface of the base region.

[0030] By adopting the above technical solution, the exposure degree of the base region and part of the source region can be accurately controlled to ensure good contact between the source and the base region during the subsequent metallization process, thereby effectively reducing the contact resistance and improving the overall conductivity of the device. At the same time, the introduction of the sidewall structure can protect the edges of the source and base regions during the etching process, avoid device damage caused by excessive etching, and improve the reliability and consistency of the device.

[0031] In summary, the present application includes at least one of the following beneficial technical effects: 1. The design of the concave source contact area reduces the area occupied by the source contact, increases the proportion of the chip current flowing through the area, and makes better use of the chip area. The source contact size is reduced, and the cell unit size (Cell Pitch) can be made smaller. For the same chip area, a smaller cell unit size can connect more units in parallel, the cell and channel unit density is higher, and the on-resistance is greatly reduced. At the same time, the split gate design makes the gate width smaller, the parasitic gate-drain capacitance Cgd is greatly reduced, and the switching loss is greatly reduced. The combination of these two designs significantly improves the overall performance of the device, and the Ron,sp*Qgd performance is greatly improved; 2. The antenna-shaped gate structure can effectively reduce the electric field concentration phenomenon under the gate. This design helps to reduce the electric field strength (EOX) of the gate oxide (Gate Oxide, i.e., the gate oxide layer), reduce the influence of the gate oxide on the reverse large voltage, play a role in protecting the gate oxide, and improve the reliability of the device; 3. The thickness of the dielectric material is greater than the thickness of the gate oxide layer, which can further enhance the insulation performance above the JFET region and reduce the influence of the gate electric field on the gate oxide, thereby improving the reliability and stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A partial cross-sectional schematic diagram of a semiconductor power device embodiment 1 of the present application is shown; Figure 2 A partial cross-sectional schematic diagram of a semiconductor power device embodiment 2 of the present application is shown; Figure 3 A schematic diagram illustrating providing a substrate and growing an epitaxial layer on the substrate in the process of manufacturing a semiconductor power device according to some preferred embodiments of the present application; Figure 4 A schematic diagram illustrating the formation of a body region in an epitaxial layer during the process of manufacturing a semiconductor power device in some preferred embodiments of the present application; Figure 5 A schematic diagram illustrating forming a source region in a body region during the process of manufacturing a semiconductor power device according to some preferred embodiments of the present application; Figure 6A schematic diagram illustrating the formation of a base region in a body region during the process of manufacturing a semiconductor power device according to some preferred embodiments of the present application; Figure 7 A schematic diagram illustrating the formation of a JFET region in an epitaxial layer during the process of manufacturing a semiconductor power device in some preferred embodiments of the present application; Figure 8 A schematic diagram illustrating forming a protective layer on the upper surface of an epitaxial layer during the process of manufacturing a semiconductor power device in some preferred embodiments of the present application; Fig. 9 A schematic diagram illustrating the formation of a gate oxide layer on the upper surface of an epitaxial layer during the process of manufacturing a semiconductor power device in some preferred embodiments of the present application; Fig.10 A schematic diagram illustrating the deposition of polysilicon on the upper surface of an epitaxial layer during the process of manufacturing a semiconductor power device in some preferred embodiments of the present application; Fig.11 A schematic diagram illustrating forming a cut-off gate in the process of manufacturing a semiconductor power device according to some preferred embodiments of the present application is shown; Fig.12 A schematic diagram illustrating the formation of an isolation layer on the periphery of polysilicon during the process of manufacturing a semiconductor power device according to some preferred embodiments of the present application; Fig.13 A schematic diagram illustrating forming a protective layer on the upper surface of an epitaxial layer during the process of manufacturing a semiconductor power device in some preferred embodiments of the present application; Fig.14 A schematic diagram illustrating the formation of a sidewall structure in the process of manufacturing a semiconductor power device according to some preferred embodiments of the present application; Fig.15 A schematic diagram illustrating the formation of a recessed source contact region during the process of manufacturing a semiconductor power device according to some preferred embodiments of the present application; Fig.16 A schematic diagram illustrating the formation of a metal interconnection layer in the process of manufacturing a semiconductor power device according to some preferred embodiments of the present application; Fig.17 A schematic diagram illustrating the formation of a source structure in the process of manufacturing a semiconductor power device according to some preferred embodiments of the present application; Fig.18 A schematic diagram illustrating filling a dielectric material in an opening of a cut-off gate during the process of manufacturing a semiconductor power device in some preferred embodiments of the present application; Fig.19 Schematic diagrams showing the formation of antenna-shaped gate structures in the process of manufacturing semiconductor power devices according to some preferred embodiments of the present application.

[0033] Description of reference numerals: 10. Substrate; 20. Epitaxial layer; 21. Gate oxide layer; 22. Protective layer; 30. Body region; 31. Source region; 32. Base region; 40. JFET region; 50. Cut-off gate; 51. Isolation layer; 52. Dielectric material; 53. Antenna-shaped gate structure; 54. Sidewall structure; 60. Concave source contact region; 61. Metal interconnection layer; 70. Source structure; 80. Passivation layer; 81. Resin layer; 90. Drain structure. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments for understanding the inventive concept of the present invention, and cannot represent all the embodiments, nor are they interpreted as the only embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field on the premise of understanding the inventive concept of the present invention are within the scope of protection of the present invention.

[0035] It should be noted that if there are directional indications (such as up, down, left, right, front, back, etc.) involved in the embodiments of the present invention, the directional indications are only used to explain the relative position relationship and movement of the components in a certain posture. If the specific posture changes, the directional indications will also change accordingly. In order to facilitate the understanding of the technical solution of the present invention, the semiconductor power device with a better FOM value and the manufacturing method thereof of the present invention are further described and explained in detail below, but they are not limited to the protection scope of the present invention.

[0036] In the specific application of the variation example, the example source can be used as a drain connection, and the example drain can be used as a source connection. The source to drain represents the relative flow direction of the electron flow. When the source recorded in the specification is connected as a source, the drain recorded in the specification must be connected as a drain; when the drain recorded in the specification is connected as a drain, the drain recorded in the specification must be connected as a source. In order to facilitate the understanding of the technical solution of the present application, the specification and the protection scope still use "source" and "drain", which are actually not limited to the source and the drain, but the first electrode and the second electrode representing two different potential electrodes. Therefore, after understanding the technical solution of the present invention, those skilled in the art can interchange the "source" and "drain" of the semiconductor device, and the protection scope of the present invention naturally also includes such an equivalent interchange.

[0037] The drawings only illustrate the common parts of multiple embodiments, and the parts with differences or distinctions are described in text or presented in comparison with the drawings. Based on the characteristics of the industry and the essence of the technology, those skilled in the art should correctly and reasonably understand and judge whether the individual technical features described below or any combination of them can represent the same embodiment, or whether multiple technical features that are mutually exclusive in essence can only represent different variant embodiments.

[0038] Figure 1 A partial cross-sectional schematic diagram of a semiconductor power device embodiment 1 of the present application is shown; Figure 2 A partial cross-sectional schematic diagram of a semiconductor power device embodiment 2 of the present application is shown; Figures 4 to 17 A partial cross-sectional schematic diagram of corresponding components of the semiconductor power device in the manufacturing process of the third embodiment of the present application is shown (corresponding to steps S10 to S90); Figure 18 to Figure 19 A partial cross-sectional schematic diagram of corresponding components during the manufacturing process of the semiconductor power device of Embodiment 4 of the present application is shown (corresponding to steps S61 to S63 ).

[0039] Example 1 A semiconductor power device with a better FOM value provided in the embodiment of the present application is referred to Figure 1 , including a substrate 10, an epitaxial layer 20, a body region 30, a JFET region 40, a cut-off gate 50, a recessed source contact region 60 and a source structure 70, wherein the epitaxial layer 20 is grown on the upper surface of the substrate 10, the body region 30 is separated and arranged in the epitaxial layer 20, and the body region 30 is provided with spaced-apart source regions 31, and a base region 32 is arranged between adjacent source regions 31, and the base region 32 is connected to the opposite side of the source region 31; the JFET region 40 is arranged in the epitaxial layer 20, and the JFET region 40 is connected to the body On the opposite side of the region 30, the JFET region 40 has a set doping concentration; the cut-off gate 50 is formed with an opening above the JFET region 40 and above the source region 31 and the base region 32, the cut-off gate 50 completely covers the upper surface of the body region 30, and the surrounding side of the cut-off gate 50 is covered with an isolation layer 51; the recessed source contact region 60 is formed above the source region 31 and above the base region 32 where the upper structure is etched; the source structure 70 is filled in the recessed source contact region 60 and the surrounding side of the isolation layer 51.

[0040] Specifically, the substrate 10 may be a semiconductor material such as single crystal silicon, silicon carbide (SiC), gallium nitride (GaN), etc., for supporting the entire device structure. The epitaxial layer 20 may be an N-type or P-type epitaxial layer 20 grown on the substrate 10, for forming subsequent functional regions. In this embodiment, the epitaxial layer 20 is an N-type epitaxial layer.

[0041] Optionally, the body region 30 can be formed into a P BODY or P WELL region by ion implantation or diffusion. The body region 30 is divided into multiple independent regions, and a source region 31 and a base region 32 are formed in each region. The doping types of the source region 31 and the base region 32 are N+ and P+, respectively, to form a PN junction. The depth of the base region 32 in the epitaxial layer 20 is greater than the depth of the source region 31. The JFET region 40 is formed by N-type doping, and its set doping concentration can be adjusted according to actual needs. Optionally, the doping concentration is set to 1e15cm -3 -1e18cm -3 In the range, preferably 1e16cm -3 -1e17cm -3 .

[0042] In the actual manufacturing process, in order to make the cut-off gate 50 completely cover the upper surface of the body region 30, the width of the cut-off gate 50 is greater than the width of the body region 30. In the case of high manufacturing process precision, the width of the cut-off gate 50 can also be equal to the width of the body region 30. The design of the cut-off gate 50 makes the gate width smaller, effectively reducing the parasitic gate-drain capacitance Cgd, thereby reducing the switching loss.

[0043] In addition, a gate oxide layer 21 is provided between the cut-off gate 50 and the upper surface of the epitaxial layer 20. The gate oxide layer 21 may be silicon dioxide (SiO2). The gate material may be polysilicon, metal or metal silicide, or a composite structure composed of these materials.

[0044] Optionally, the isolation layer 51 may be silicon dioxide (SiO 2 ), silicon nitride (SiN) or a combination thereof, and is used to isolate the gate from surrounding structures.

[0045] Among them, the recessed source contact area 60 is formed by etching the upper structure of the base area 32, so that a structure with a low middle and high sides is formed between the base area 32 and the source area 31. This design reduces the area occupied by the source contact, increases the area ratio of the chip through which current flows, improves the chip area utilization, and thus reduces the on-resistance.

[0046] In one embodiment, the upper surface of the recessed source contact region 60 is covered with a metal interconnection layer 61 for achieving connection with an external circuit. The metal interconnection layer 61 may be a metal silicide, wherein the metal includes but is not limited to Ni and Ti.

[0047] The source structure 70 is filled above the metal interconnect layer 61 and around the isolation layer 51. The source structure 70 is formed by metal deposition. The metal includes but is not limited to pure Al / Cu and its alloys (AlSi alloy, AlCu alloy and AlSiCu alloy) or their stacked combinations.

[0048] In one embodiment, a passivation layer 80 is disposed on the upper surface of the source structure 70, and the passivation layer 80 includes but is not limited to SiO2, SiN and a combination thereof, and the thickness of the passivation layer 80 is 0.1 μm-20 μm. A resin layer 81 is disposed on the upper surface of the passivation layer 80, and the resin layer 81 includes but is not limited to polyimide, polyamide and polybenzoxazole, and the thickness of the resin layer 81 is 1 μm-50 μm, and preferably, the thickness of the resin layer 81 is 1 μm-15 μm.

[0049] Optionally, the thickness of the substrate 10 ranges from 80um to 250um, and the preferred thickness range in this embodiment is from 110um to 200um. In addition, a back metal is deposited on the lower surface of the substrate 10 to form a drain structure 90, and the back metal includes but is not limited to Ti / Ni / Ag / Pd / Au and alloys or combinations thereof.

[0050] The implementation principle of this embodiment is: through the design of the recessed source contact area 60 and the cut-off gate 50, the on-resistance and switching loss are significantly reduced, and the FOM value of the device is improved. Specifically, the recessed source contact area 60 reduces the area occupied by the source contact, increases the area ratio of the chip current flowing through, thereby reducing the on-resistance. The design of the cut-off gate 50 reduces the gate width, reduces the parasitic gate-drain capacitance Cgd, and thus reduces the switching loss. In addition, by optimizing the selection and thickness of each layer of material, the reliability and performance of the device are further improved.

[0051] Example 2 The difference between this embodiment and the above-mentioned embodiment 1 is that, referring to Figure 2 The opening above the JFET region 40 is filled with a dielectric material 52 , and polysilicon is backfilled above the dielectric material 52 so that the polysilicon and the cut-off gate 50 form an antenna-shaped gate structure 53 .

[0052] Specifically, the dielectric material 52 filled in the opening above the JFET region 40 may be silicon dioxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), titanium dioxide (TiO2), hafnium oxide (HfO2) or molybdenum oxide (MoO2), etc. Preferably, SiO2 is selected as the dielectric material 52 in this embodiment.

[0053] In a preferred embodiment, the thickness of the dielectric material 52 is greater than the thickness of the gate oxide layer 21 to ensure a good isolation effect. After the backfilled polysilicon is photolithographically and etched, the center of the polysilicon is opened to form an antenna-shaped gate structure 53. The antenna-shaped gate structure 53 can effectively reduce the electric field concentration phenomenon under the gate. This design helps to reduce the electric field strength (EOX) of the gate oxide (GateOxide, i.e., the gate oxide layer 21), reduce the influence of the reverse large voltage on the gate oxide, play a role in protecting the gate oxide, and improve the reliability of the device.

[0054] The implementation principle of this embodiment is: by filling the dielectric material 52 in the opening above the JFET region 40 and forming the antenna-shaped gate structure 53, the influence of the gate oxide on the reverse large voltage is further reduced, and the reliability of the device is improved. Specifically, the introduction of the dielectric material 52 enhances the isolation effect between the gate and the epitaxial layer 20, and the design of the antenna-shaped gate structure 53 makes the gate electric field more uniform, thereby reducing the concentration of the gate oxide electric field and improving the voltage resistance of the device.

[0055] Example 3 Embodiment 3 of the present application further discloses a method for manufacturing a semiconductor power device with a better FOM value, comprising the following steps: Reference Figure 3 , S10, providing a substrate 10, and growing an epitaxial layer 20 on the surface of the substrate 10.

[0056] Specifically, the substrate 10 and the epitaxial layer 20 may be semiconductor materials such as single crystal silicon, silicon carbide (SiC), gallium nitride (GaN), etc., and the epitaxial layer 20 may be an N-type or P-type epitaxial layer 20 grown on the substrate 10, for forming subsequent functional areas. In this embodiment, the epitaxial layer 20 is an N-type epitaxial layer 20. When the epitaxial layer 20 is a P-type, all doping types are changed to opposite types.

[0057] Reference Figure 4 , S20, doping ions into the epitaxial layer 20 to form a plurality of separated body regions 30.

[0058] Specifically, a mask is formed on the upper surface of the epitaxial layer 20 , and an opening is formed on the mask through photolithography and etching. The body region 30 is formed through ion implantation or diffusion process. The body region 30 is a P Body or P WELL region.

[0059] Reference Figure 5 , S30, forming spaced-apart source regions 31 in the same body region 30 by ion doping.

[0060] Specifically, a mask is deposited on the basis of the body region 30 mask; an opening is formed on the mask through photolithography and etching, and separated source regions 31 are formed in the body region 30 through ion implantation or diffusion process. The doping type of the source region 31 is N+ type, and the dopant is usually selected from phosphorus (P) or arsenic (As); the mask is removed after the source region 31 is formed.

[0061] Reference Figure 6 , S40, doping ions into the body region 30 to form a base region 32 connected to the opposite side of the source region 31.

[0062] Specifically, a mask is formed on the upper surface of the epitaxial layer 20, and an opening is formed on the mask through photolithography and etching. A base region 32 connected to the opposite side of the source region 31 is formed in the body region 30 through ion implantation or diffusion process. The doping type of the base region 32 is P+ type, and the dopant is usually boron (B). After the base region 32 is formed, the mask is removed.

[0063] Reference Figure 7 , S50, doping ions into the epitaxial layer 20 to form a JFET region 40 connected to the opposite side of the body region 30, and the JFET region 40 has a set doping concentration.

[0064] Specifically, a mask is formed on the upper surface of the epitaxial layer 20, and an opening is formed on the mask through photolithography and etching. A JFET region 40 is formed in the epitaxial layer 20 to be in contact with the opposite side of the body region 30 through ion implantation or diffusion process. The doping type of the JFET region 40 is N-type, and the dopant is usually selected from phosphorus (P) or arsenic (As); optionally, the doping concentration is set to 1e15cm -3 -1e18cm -3 In the range, preferably 1e16cm -3 -1e17cm -3 ; After the JFET region 40 is formed, the mask is removed.

[0065] Before step S60, the method further includes: Reference Figure 8 S58, using photoresist or sputtering carbon, a protective layer 22 is formed on the upper surface of the epitaxial layer 20, and then the doping process is activated at high temperature; after activation, the protective layer 22 is removed. The protective layer 22 includes but is not limited to PR, C, AlN, etc. The activation temperature range in this embodiment is 1400-2100°C, and the preferred temperature range is 1700-1800°C.

[0066] Reference Fig. 9 S59, oxidizing the upper surface of the epitaxial layer 20 at a high temperature, and then removing the sacrificial oxide layer on the upper surface of the epitaxial layer 20; forming a gate oxide layer 21 on the upper surface of the epitaxial layer 20 by thermal oxidation or CVD.

[0067] Reference Fig.10 and Fig.11 , S60, depositing polysilicon on the upper surface of the epitaxial layer 20, removing the polysilicon above the JFET region 40 and above the source region 31 and the base region 32 to form a cut-off gate 50, and the cut-off gate 50 can completely cover the upper surface of the body region 30.

[0068] Step S60 specifically includes: A mask is formed on the upper surface of the polysilicon, and the polysilicon above the JFET region 40 and above the source region 31 and the base region 32 is removed by photolithography and etching to form a cut-off gate 50. The design of the cut-off gate 50 reduces the gate width, reduces the parasitic gate-drain capacitance Cgd, and thus reduces the switching loss; the mask is removed after the cut-off gate 50 is formed.

[0069] Reference Fig.12 , S70, forming an isolation layer 51 around the polysilicon.

[0070] Specifically, the material of the isolation layer 51 includes but is not limited to SiO 2 , SiN or a combination thereof.

[0071] After step S70, the method further includes: Reference Fig.13 , S71, forming a mask on the upper surface of the isolation layer 51, photolithography and etching the isolation layer 51 to expose the upper surface of the base region 32 and a portion of the upper surface of the source region 31.

[0072] Reference Fig.14 S72, forming a sidewall structure 54 on the basis of the mask, the sidewall structure 54 covers the upper surface of the base region 32, part of the upper surface of the source region 31, and the mask and the peripheral side of the isolation layer 51. Specifically, the material of the sidewall structure 54 includes but is not limited to SiO2, SiN, Poly Si or a combination thereof.

[0073] Reference Fig.15 , S73, removing the sidewall structure 54 on the upper surface of the mask and the sidewall structure 54 on the upper surface of the base region 32.

[0074] S80 , etching the upper structure of the base region 32 to form a recessed source contact region 60 above the base region 32 and the source region 31 .

[0075] Specifically, the upper structure of the base region 32 is etched by using a self-alignment process to form a concave source contact region 60 which is low in the middle and high on both sides; and the sidewall structure 54 and the mask are removed.

[0076] Step S80 also includes: Reference Fig.16 , S81, depositing metal in the recessed source contact area 60, forming a metal interconnection layer 61 at a high temperature, and removing excess metal; the metal includes but is not limited to Ni and Ti.

[0077] Reference Fig.17 , S90, filling metal into the recessed source contact area 60 and the surrounding side of the isolation layer 51 to form a source structure 70.

[0078] Specifically, the metal forming the source structure 70 includes, but is not limited to, pure Al / Cu and alloys thereof (AlSi alloy, AlCu alloy and AlSiCu alloy) or stacked combinations thereof.

[0079] Reference Fig.17 , after step S90, further comprising: S100 , a surface passivation layer 80 is disposed on the upper surface of the source structure 70 . The passivation layer 80 includes but is not limited to SiO 2 , SiN and a combination thereof. The thickness of the passivation layer 80 is 0.1 μm-20 μm.

[0080] S110 , a resin layer 81 is disposed on the upper surface of the passivation layer 80 . The resin layer 81 includes but is not limited to polyimide, polyamide and polybenzoxazole. The thickness of the resin layer 81 is 1 μm-50 μm. Preferably, the thickness of the resin layer 81 is 1 μm-15 μm.

[0081] S120, thinning the substrate 10, the thickness of the substrate 10 after thinning is in the range of 80um-250um, and the preferred thickness range in this embodiment is 110um-200um.

[0082] S130 , depositing a back metal on the lower surface of the substrate 10 to form a drain structure 90 , wherein the back metal includes but is not limited to Ti / Ni / Ag / Pd / Au and alloys or combinations thereof.

[0083] Example 4 The difference between this embodiment and the above-mentioned embodiment 3 is that, referring to Fig.18 and Fig.19 , the following steps are added between process step S60 and process step S70: S61 , filling the opening of the cut-off gate 50 with a dielectric material 52 .

[0084] Specifically, after filling, photolithography and etching are performed to remove excess dielectric material 52 , leaving only dielectric material 52 at the opening.

[0085] Optionally, the dielectric material 52 may be silicon dioxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), titanium dioxide (TiO2), hafnium oxide (HfO2) or molybdenum oxide (MoO2), etc. Preferably, SiO2 is selected as the dielectric material 52 in this embodiment. Preferably, the thickness of the dielectric material 52 is greater than the thickness of the gate oxide layer 21 to ensure a good isolation effect.

[0086] S62 , backfilling polysilicon on the dielectric material 52 .

[0087] S63 , etching the polysilicon above the center of the dielectric material 52 to form an antenna-shaped gate structure 53 .

[0088] Specifically, the backfilled polysilicon is subjected to photolithography and etching to remove excess polysilicon, thereby forming an antenna-shaped gate structure 53. The design of the antenna-shaped gate structure 53 can further reduce the influence of the reverse large voltage on the gate oxide, thereby improving the reliability of the device.

[0089] The implementation principle of this embodiment is: by adding the filling of dielectric material 52 and the backfilling of polysilicon in the process steps, an antenna-shaped gate structure 53 is formed, which further improves the reliability of the device. Specifically, the introduction of dielectric material 52 enhances the isolation effect between the gate and the epitaxial layer 20, and the design of the antenna-shaped gate structure 53 makes the gate electric field more uniform, thereby reducing the concentration of the gate oxide electric field and improving the voltage resistance of the device.

[0090] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereto. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application should be included in the protection scope of the present application.

Claims

1. A semiconductor power device with a better FOM value, characterized in that: include: A substrate (10) having an epitaxial layer (20) grown on its upper surface; A body region (30) is separately arranged in the epitaxial layer (20), wherein the body region (30) is provided with spaced-apart source regions (31), and a base region (32) is provided between adjacent source regions (31), and the base region (32) is connected to opposite sides of the source region (31); A JFET region (40) is arranged in the epitaxial layer (20), the JFET region (40) is connected to opposite sides of the body region (30), and the JFET region (40) has a set doping concentration; A cut-off gate (50) is formed with an opening above the JFET region (40) and above the source region (31) and the base region (32), the cut-off gate (50) completely covers the upper surface of the body region (30), and the peripheral side of the cut-off gate (50) is covered with an isolation layer (51); A recessed source contact region (60) formed above the source region (31) and above the base region (32) where the upper structure is etched; A source electrode structure (70) is filled in the recessed source contact area (60) and the peripheral side of the isolation layer (51).

2. A semiconductor power device with a better FOM value according to claim 1, characterized in that: The opening above the JFET region (40) is filled with a dielectric material (52), and polysilicon is backfilled above the dielectric material (52) so that the polysilicon and the cut-off gate (50) form an antenna-shaped gate structure (53).

3. A semiconductor power device with a better FOM value according to claim 2, characterized in that: The dielectric material (52) is one of SiO2, SiN, Al2O3, TiO2, HfO2 and MoO2.

4. The semiconductor power device with a better FOM value according to claim 2, characterized in that: A gate oxide layer (21) is provided between the cut-off gate (50) and the upper surface of the epitaxial layer (20), and the thickness of the dielectric material (52) is greater than the thickness of the gate oxide layer (21).

5. The semiconductor power device with a better FOM value according to claim 1, characterized in that: The upper surface of the recessed source contact area (60) is covered with a metal interconnection layer (61).

6. The semiconductor power device with a better FOM value according to claim 1, characterized in that: A passivation layer (80) is provided on the upper surface of the source structure (70), the thickness of the passivation layer (80) is 0.1 μm-20 μm, a resin layer (81) is provided on the upper surface of the passivation layer (80), the thickness of the resin layer (81) is 1 μm-50 μm, and a drain structure (90) is provided on the lower surface of the substrate (10).

7. A method for manufacturing a semiconductor power device with a better FOM value, characterized in that: The following steps are involved: S10, providing a substrate (10), and growing an epitaxial layer (20) on a surface of the substrate (10); S20, doping ions into the epitaxial layer (20) to form a plurality of separated body regions (30); S30, forming spaced-apart source regions (31) in the same body region (30) by ion doping; S40, doping ions into the body region (30) to form a base region (32) connected to the opposite side of the source region (31); S50, doping ions into the epitaxial layer (20) to form a JFET region (40) connected to the opposite side of the body region (30), wherein the JFET region (40) has a set doping concentration; S60, depositing polysilicon on the upper surface of the epitaxial layer (20), removing the polysilicon above the JFET region (40) and above the source region (31) and the base region (32), so as to form a cut-off gate (50), wherein the cut-off gate (50) can completely cover the upper surface of the body region (30); S70, forming an isolation layer (51) around the polysilicon; S80, etching the upper structure of the base region (32) to form a recessed source contact region (60) above the base region (32) and the source region (31); S90, filling metal into the recessed source contact area (60) and the peripheral side of the isolation layer (51) to form a source structure (70).

8. The method for manufacturing a semiconductor power device with a better FOM value according to claim 7, characterized in that: After step S60, the following steps are further included: S61, filling the opening of the cut-off gate (50) with a dielectric material (52); S62, backfilling polysilicon on the dielectric material (52); S63, etching the polysilicon above the center of the dielectric material (52) to form an antenna-shaped gate structure (53).

9. The method for manufacturing a semiconductor power device with a better FOM value according to claim 8, characterized in that: The dielectric material (52) is one of SiO2, SiN, Al2O3, TiO2, HfO2 and MoO2; Before step S60, the method further includes: S59, forming a gate oxide layer (21) on the upper surface of the epitaxial layer (20); The thickness of the dielectric material (52) is greater than the thickness of the gate oxide layer (21).

10. The method for manufacturing a semiconductor power device with a better FOM value according to claim 7, characterized in that: After step S70, the method further includes: S71, forming a mask on the upper surface of the isolation layer (51), photolithography and etching the isolation layer (51) to expose the upper surface of the base region (32) and a portion of the upper surface of the source region (31); S72, forming a sidewall structure (54) on the basis of the mask, wherein the sidewall structure (54) covers the upper surface of the base region (32), part of the upper surface of the source region (31), and the peripheral sides of the mask and the isolation layer (51); S73, removing the sidewall structure (54) on the upper surface of the mask and the sidewall structure (54) on the upper surface of the base region (32).

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