Semiconductor substrate and processing method thereof
By setting a silicon oxide layer in the middle layer of the semiconductor substrate, the thermal expansion coefficient is close to that of the film, the problem of warping and deformation of the semiconductor substrate is solved, and more efficient thermal stress management and warping resistance are achieved.
Patent Information
- Application Number
- CN202411716610.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-27
- Publication Date
- 2025-03-14
AI Technical Summary
With the development of semiconductor stacking technology, existing silicon substrates cannot effectively solve the problem of warping and deformation caused by the increase in the number of thin film layers.
A semiconductor substrate is designed, by providing a silicon oxide layer in the middle layer of the substrate so that its thermal expansion coefficient is close to the thermal expansion coefficient of the film, thereby reducing thermal stress and reducing warping deformation.
By reducing the thermal stress generated by thin film stacking, the warping deformation of semiconductor substrates is significantly reduced, and the anti-warping ability of the substrate is improved, which is suitable for the future development of semiconductor technology.
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Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor substrate and a processing method thereof. Background Art
[0002] With the development of the semiconductor industry, stacking technology has become the main development technology for storage semiconductors. Stacking technology mainly involves stacking thin films on semiconductor substrates. With the development of technology, the number of stacked thin film layers is increasing. As the number of stacked layers increases, the warping deformation of the semiconductor structure caused by film stress becomes more and more serious. During semiconductor processing, the existing silicon substrate has a large warping deformation and is not competent for the development of future semiconductor technology. A semiconductor substrate that resists warping deformation is needed. Summary of the invention
[0003] In view of this, the present application provides a semiconductor substrate and a processing method thereof, which can reduce the thermal stress generated by the thin film stack and thereby reduce the warping deformation of the semiconductor substrate.
[0004] In order to achieve the above objectives, this application provides the following technical solutions:
[0005] A semiconductor substrate comprises a first single crystal silicon layer, a silicon oxide layer and a second single crystal silicon layer which are stacked, wherein the first single crystal silicon layer is used to carry a thin film, and the silicon oxide layer is located between the first single crystal silicon layer and the second single crystal silicon layer so that the thermal expansion coefficient of the semiconductor substrate is close to the thermal expansion coefficient of the thin film.
[0006] Optionally, the thickness of the silicon oxide layer accounts for at least one quarter of the total thickness of the semiconductor substrate.
[0007] Optionally, the total thickness of the semiconductor substrate is set to 775 microns, and the minimum thickness of the silicon oxide layer is set to 200 microns.
[0008] Optionally, the minimum thickness of the first single crystal silicon layer is set to 30 microns, and the minimum thickness of the second single crystal silicon layer is set to 50 microns.
[0009] Optionally, the thickness of the silicon oxide layer is set to 500-700 microns, the minimum thickness of the first single crystal silicon layer is set to 37-137 microns, and the minimum thickness of the second single crystal silicon layer is set to 57-117 microns.
[0010] Optionally, the thickness of the silicon oxide layer is set to 600 microns, the minimum thickness of the first single crystal silicon layer is set to 87.5 microns, and the minimum thickness of the second single crystal silicon layer is set to 87.5 microns.
[0011] A method for processing a semiconductor substrate, based on the semiconductor substrate as described in any one of the above items, comprising:
[0012] preparing a silicon oxide wafer and two single crystal silicon wafers in a polished state;
[0013] Using a direct bonding process, two single crystal silicon slices are bonded to two sides of the silicon oxide slice to form a substrate body;
[0014] The substrate body is polished and cleaned.
[0015] Optionally, the direct bonding process includes:
[0016] Using N atmosphere plasma to perform surface modification on the silicon oxide slice and the two single crystal silicon slices;
[0017] Directly bonding the silicon oxide thin slice and the two single crystal silicon thin slices at room temperature to form a substrate body;
[0018] The substrate body is annealed and strengthened at a temperature of 270-330 degrees Celsius.
[0019] Optionally, before the direct bonding process is adopted, the two single crystal silicon slices are subjected to wire cutting, grinding and double-sided polishing to make their GBIR value less than 500 nanometers.
[0020] Optionally, the polishing cleaning includes:
[0021] Performing side polishing and initial cleaning on the substrate body;
[0022] The substrate body is subjected to edge polishing, final polishing and final cleaning.
[0023] Optionally, when the side surfaces of the substrate body are polished, the removal amount on both sides of the substrate body is 8 microns.
[0024] Optionally, the thickness of the silicon oxide thin slice is 600 microns, and the thickness of the two single crystal silicon thin slices is 104 microns.
[0025] Optionally, the diameters of the silicon oxide slice and the two single crystal silicon slices are both 300.4 mm.
[0026] The semiconductor substrate and processing method provided by the present application provide a silicon oxide layer in the middle layer of the semiconductor substrate so that the thermal expansion coefficient of the semiconductor substrate is close to the thermal expansion coefficient of the film, which can greatly reduce the thermal stress generated by the film stacking in the stacking process, thereby reducing the warping deformation of the semiconductor substrate. Moreover, both sides of the single crystal silicon layer are provided with single crystal silicon layers, which can ensure the versatility and adaptability in the stacking process. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.
[0028] Figure 1 A schematic cross-sectional view of a semiconductor substrate according to some embodiments is shown.
[0029] In the figure: 1. first single crystal silicon layer; 2. second single crystal silicon layer; 3. silicon oxide layer. DETAILED DESCRIPTION
[0030] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0031] like Figure 1 As shown, an embodiment of the present application provides a semiconductor substrate for playing the role of basic support and providing an initial surface in semiconductor stacking technology, so that thin films are stacked layer by layer on the surface of the semiconductor substrate.
[0032] The semiconductor substrate is arranged as a stacked structure, comprising a first single crystal silicon layer 1, a silicon oxide layer 3 and a second single crystal silicon layer 2 which are stacked, the silicon oxide layer 3 being located between the first single crystal silicon layer 1 and the second single crystal silicon layer 2, that is, the first single crystal silicon layer 1 and the second single crystal silicon layer 2 are stacked on two sides of the silicon oxide layer 3, respectively, to respectively constitute the upper surface and the lower surface of the semiconductor substrate; during the stacking process, the first single crystal silicon layer 1 is located on the upper layer of the silicon oxide layer 3, so that the thin film is stacked layer by layer on the surface of the first single crystal silicon layer 1; the second single crystal silicon layer 2 is located on the lower layer of the silicon oxide layer 3; the support seat and the heat dissipation component are connected via the second single crystal silicon layer 2 to achieve support and heat dissipation of the semiconductor substrate.
[0033] It should be noted that the sources of film stress include internal stress and thermal stress, wherein the internal stress is caused by the process itself, while the thermal stress is generated when two materials with different thermal expansion coefficients are combined or precipitated with each other. In the prior art, the film is made of silicon oxide and the substrate is made of silicon. The thermal expansion rates between the film and the substrate are different due to temperature changes, which in turn generates thermal stress at the interface. Therefore, the film stress mainly comes from the difference in thermal expansion coefficients between the substrate and the film.
[0034] The semiconductor substrate provided in the present solution has a silicon oxide layer 3 in the middle layer of the semiconductor substrate, so that the thermal expansion coefficient of the semiconductor substrate is close to that of the thin film, which can greatly reduce the thermal stress generated by the thin film stacking in the stacking process, thereby reducing the warping deformation of the semiconductor substrate. Moreover, both sides of the single crystal silicon layer are set as single crystal silicon layers, which can ensure the versatility and adaptability in the stacking process.
[0035] The thickness of the silicon oxide layer 3 is at least one quarter of the total thickness of the semiconductor substrate. For example, the standard thickness of the semiconductor substrate is 775 microns, and the minimum thickness of the silicon oxide layer 3 is set to 200 microns. In this way, by limiting the thickness ratio of silicon oxide relative to the semiconductor substrate, it is possible to avoid a large difference between the thermal expansion coefficient of the semiconductor substrate and the thermal expansion coefficient of the film, thereby reducing the warping deformation of the semiconductor substrate during the thin film deposition process to a certain extent.
[0036] In addition, the minimum thickness of the first single crystal silicon layer 1 is set to 30 microns. Since the first single crystal silicon layer 1 is located above the silicon oxide layer 3, a thin film needs to be stacked on the upper surface of the first single crystal silicon layer 1 to deposit and form a circuit. By limiting the minimum thickness of the first single crystal silicon layer 1, the reliability and stability of the preparation process can be improved. For example, during the process, ion implantation will implant a certain depth of heavily doped wells on the surface of the first single crystal silicon layer 1. If the first single crystal silicon layer 1 is too thin, the well depth will be insufficient and cannot meet the requirements.
[0037] Moreover, the minimum thickness of the second single crystal silicon layer 2 is set to 50 microns. During the manufacturing process, there will be multiple etching steps on the surface of the second single crystal silicon layer 2. These etching processes will have a strong etching effect on silicon oxide. By limiting the thickness of the second single crystal silicon layer 2, the intermediate silicon oxide layer 3 can be protected.
[0038] In some embodiments, the thickness of the silicon oxide layer 3 is set to 500-700 microns, the minimum thickness of the first single crystal silicon layer 1 is set to 37-137 microns, and the minimum thickness of the second single crystal silicon layer 2 is set to 57-117 microns. In this way, the thickness of the silicon oxide layer 3 is larger than the thickness of the first single crystal silicon layer 1 and the second single crystal silicon layer 2, so that the thermal expansion coefficient of the semiconductor substrate is closer to the thermal expansion coefficient of the film (silicon oxide), which can greatly reduce the film stress, thereby reducing the warping deformation of the semiconductor substrate.
[0039] In a specific solution, the thickness of the silicon oxide layer 3 is set to 600 microns, the minimum thickness of the first single crystal silicon layer 1 is set to 87.5 microns, and the minimum thickness of the second single crystal silicon layer 2 is set to 87.5 microns.
[0040] The embodiment of the present application provides a method for processing a semiconductor substrate, based on the semiconductor substrate in the above embodiment, comprising:
[0041] preparing a silicon oxide wafer and two single crystal silicon wafers in a polished state;
[0042] Using a direct bonding process, two single crystal silicon slices are bonded to both sides of a silicon oxide slice to form a substrate body;
[0043] The substrate body is polished and cleaned.
[0044] The thickness of the two single-crystal silicon slices can be consistent or inconsistent. For example, the thickness of the two single-crystal silicon slices is 104 microns. Since the surface of the single-crystal silicon slices needs to be polished and cleaned later, a certain thickness will be removed, so the thickness of the single-crystal silicon slice needs to be slightly larger than the thickness of the single-crystal silicon layer. Since the direct bonding process is used to attach the two single-crystal silicon slices to the two sides of the silicon oxide slice, there is no need to thicken the silicon oxide slice, that is, the thickness of the silicon oxide slice is 600 microns.
[0045] In this way, the silicon oxide slice and the two single crystal silicon slices are bonded together by direct bonding, and the formed substrate body is repaired by polishing and cleaning, which is conducive to simplifying the process and improving processing efficiency and product quality.
[0046] In some embodiments, the direct bonding process includes:
[0047] The surface of silicon oxide wafer and two single crystal silicon wafers were modified by plasma in N atmosphere;
[0048] Directly bonding a silicon oxide thin slice and two single crystal silicon thin slices at room temperature to form a substrate body;
[0049] The substrate body is annealed and strengthened at a temperature of 270-330 degrees Celsius.
[0050] In this way, the silicon oxide sheet and the two single crystal silicon sheets are first surface modified and then directly bonded, and finally high temperature annealing and strengthening, which is conducive to the rapid bonding of the interface and can improve the bonding strength, thereby improving the product quality. Specifically, the substrate body can be annealed and strengthened at a temperature of 300 degrees Celsius.
[0051] Before using the above-mentioned direct bonding process, the two single-crystal silicon wafers need to be wire-cut, ground and double-sided polished to make their GBIR (wafer flatness) value less than 500 nanometers, thereby ensuring that the surface wafer flatness of the two single-crystal silicon wafers is good, which is beneficial to improving the quality of the stacking process.
[0052] In some embodiments, the polishing and cleaning of the substrate body includes side polishing, initial cleaning, edge polishing, final polishing and final cleaning. Specifically, after the direct bonding process is completed, the formed substrate body is side polished, such as CMP (Chemical Mechanical Planarization) to remove 8 microns from both sides of the substrate body. After CMP is completed, the substrate body is initially cleaned. The substrate body is edge polished (EP) to remove possible damage. The substrate body is finally polished (FP) to further repair the surface morphology. Finally, the substrate body is finally cleaned to remove possible contamination on the surface.
[0053] Since the formed substrate body needs to be edge polished, the diameter of the silicon oxide slice and the two single crystal silicon slices needs to be larger than the diameter of the semiconductor substrate. For example, the diameter is set to 300.4 mm, and 0.4 mm is removed during edge polishing.
[0054] The diameter of the silicon oxide wafer and the two single crystal silicon wafers are both 300.4 mm.
[0055]
[0056] In order to demonstrate the effectiveness of the semiconductor substrate in this scheme, a control test of thin film deposition was carried out. As shown in the table above, the experimental group is a semiconductor substrate provided by this scheme, with a diameter of 300 mm and a thickness of 775 microns. The total thickness of the semiconductor substrate in each experimental group is 775 microns, and the thickness of the silicon oxide layer 3 in different experimental groups is different, namely 700 microns, 600 microns, 500 microns, 300 microns, and 200 microns, that is, the proportion of the silicon oxide layer 3 in different experimental groups is different. The control group is a single crystal silicon substrate with a diameter of 300 mm and a thickness of 775 microns, that is, the thickness of the silicon oxide layer in the single crystal silicon substrate is zero. At a temperature of 500 degrees Celsius, APCVD (Atmospheric Pressure Chemical Vapor Deposition) was used to deposit silicon oxide on a single crystal silicon substrate and a semiconductor substrate, respectively. (405 nanometers) of silicon oxide film. Ten pieces were deposited in the experimental group and the control group, and the film stress of the two substrates was tested about four hours after the deposition. The test results are shown in the table above. The film stress of the single crystal silicon substrate is about 75MPa. The film stress of the semiconductor substrate in this scheme is less than 75MPa. The minimum value in the experimental group is about 21MPa, which shows the effectiveness of the semiconductor substrate designed in this scheme.
[0057] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.
[0058] The block diagrams of the devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagram. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open words, referring to "including but not limited to", and can be used interchangeably with them. The words "or" and "and" used here refer to the words "and / or" and can be used interchangeably with them, unless the context clearly indicates otherwise. The words "such as" used here refer to the phrase "such as but not limited to", and can be used interchangeably with them.
[0059] It should also be noted that in the apparatus, device and method of the present application, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present application.
[0060] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.
[0061] It should be understood that the qualifiers "first", "second", "third", "fourth", "fifth" and "sixth" used in the description of the embodiments of the present application are only used to more clearly explain the technical solutions and cannot be used to limit the scope of protection of the present application.
[0062] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present application to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.
Claims
1. A semiconductor substrate, characterized in that: The invention comprises a first single crystal silicon layer, a silicon oxide layer and a second single crystal silicon layer which are stacked, wherein the first single crystal silicon layer is used to carry a thin film, and the silicon oxide layer is located between the first single crystal silicon layer and the second single crystal silicon layer, so that the thermal expansion coefficient of the semiconductor substrate is close to the thermal expansion coefficient of the thin film.
2. The semiconductor substrate according to claim 1, characterized in that The thickness of the silicon oxide layer accounts for at least one quarter of the total thickness of the semiconductor substrate.
3. The semiconductor substrate according to claim 2, characterized in that The total thickness of the semiconductor substrate is set to 775 micrometers, and the minimum thickness of the silicon oxide layer is set to 200 micrometers.
4. The semiconductor substrate according to any one of claims 1 to 3, characterized in that: The minimum thickness of the first single crystal silicon layer is set to 30 micrometers, and the minimum thickness of the second single crystal silicon layer is set to 50 micrometers.
5. The semiconductor substrate according to claim 1, wherein The thickness of the silicon oxide layer is set to 500-700 microns, the minimum thickness of the first single crystal silicon layer is set to 37-137 microns, and the minimum thickness of the second single crystal silicon layer is set to 57-117 microns.
6. The semiconductor substrate according to claim 5, characterized in that The thickness of the silicon oxide layer is set to 600 micrometers, the minimum thickness of the first single crystal silicon layer is set to 87.5 micrometers, and the minimum thickness of the second single crystal silicon layer is set to 87.5 micrometers.
7. A method for processing a semiconductor substrate, characterized in that: The semiconductor substrate according to any one of claims 1 to 6, comprising: preparing a silicon oxide wafer and two single crystal silicon wafers in a polished state; Using a direct bonding process, two single crystal silicon slices are bonded to two sides of the silicon oxide slice to form a substrate body; The substrate body is polished and cleaned.
8. The processing method according to claim 7, characterized in that: The direct bonding process includes: Using N atmosphere plasma to perform surface modification on the silicon oxide slice and the two single crystal silicon slices; Directly bonding the silicon oxide thin slice and the two single crystal silicon thin slices at room temperature to form a substrate body; The substrate body is annealed and strengthened at a temperature of 270-330 degrees Celsius.
9. The processing method according to claim 7, characterized in that: Before the direct bonding process is adopted, the two single crystal silicon slices are subjected to wire cutting, grinding and double-sided polishing to make their GBIR values less than 500 nanometers.
10. The processing method according to claim 7, characterized in that: The polishing cleaning comprises: Performing side polishing and initial cleaning on the substrate body; The substrate body is subjected to edge polishing, final polishing and final cleaning.
11. The processing method according to claim 10, characterized in that: When the side surface of the substrate body is polished, the removal amount on both sides of the substrate body is 8 microns.
12. The processing method according to claim 7, characterized in that: The thickness of the silicon oxide slice is 600 microns, and the thickness of the two single crystal silicon slices is 104 microns.
13. The processing method according to claim 7, characterized in that: The diameters of the silicon oxide slice and the two single crystal silicon slices are both 300.4 mm.