Flat panel detector substrate, preparation method thereof and flat panel detector

Abstract

The invention discloses a flat panel detector substrate, a preparation method thereof and a flat panel detector. The flat panel detector substrate comprises: a substrate; the thin film transistor is formed on the substrate; the photodiode is formed on one side, far away from the substrate, of the thin film transistor; the first interlayer insulating layer is formed on one side, far away from the substrate, of the second electrode, and at least one first via hole for exposing the second electrode is formed in the first interlayer insulating layer; the barrier layer covers at least one first via hole and is electrically connected with the second electrode at the bottom of the first via hole; and the transmission line is formed on one side, far away from the second electrode, of the barrier layer and is electrically connected with the barrier layer. According to the technical scheme provided by the invention, the problem that in the preparation process of the flat panel detector substrate, the product is easy to be bad when the via hole is formed is solved.

Description

Technical Field

[0001] The present application belongs to the field of sensor manufacturing technology, and in particular, relates to a flat panel detector substrate and a preparation method thereof, and a flat panel detector. Background Art

[0002] Flat panel detectors can detect X-rays and other objects, and are widely used in medical imaging, industrial nondestructive testing, security inspection and protection, etc. The flat panel detector substrate structure includes a photodiode film layer, and an upper electrode layer is formed on the upper side of the photodiode film layer. The upper electrode layer is also covered with an interlayer insulating layer for protection and insulation. In order to achieve conduction between the transmission line and the upper electrode layer, a via hole is formed on the interlayer insulating layer to electrically connect the transmission line and the electrode layer. However, the inventor found in the process of implementing the present invention that the process of forming the via hole on the interlayer insulating layer is likely to cause product defects. Summary of the invention

[0003] The present application provides a flat panel detector substrate and a preparation method thereof, and a flat panel detector, aiming to solve the problem that during the preparation process of the flat panel detector substrate, forming via holes easily leads to defective products.

[0004] In a first aspect, an embodiment of the present application provides a flat panel detector substrate, comprising:

[0005] substrate substrate;

[0006] A thin film transistor formed on the base substrate;

[0007] A photodiode formed on a side of the thin film transistor away from the base substrate, the photodiode comprising a first electrode close to the base substrate, a photodiode film layer and a second electrode away from the base substrate, the first electrode being electrically connected to the first electrode of the thin film transistor;

[0008] A first interlayer insulating layer is formed on a side of the second electrode away from the base substrate, wherein at least one first via hole exposing the second electrode is formed on the first interlayer insulating layer;

[0009] a barrier layer covering the at least one first via hole, the barrier layer being electrically connected to the second electrode at the bottom of the first via hole;

[0010] A transmission line is formed on a side of the barrier layer away from the second electrode, and the transmission line is electrically connected to the barrier layer.

[0011] In some embodiments, the number of the first via holes is at least two.

[0012] In some embodiments, at least one second via hole is further formed on the first interlayer insulating layer, the barrier layer covers the second via hole, and the barrier layer is a transparent conductive material.

[0013] In some embodiments, the first via hole and / or the second via hole is a structure that is wide at the top and narrow at the bottom.

[0014] In some embodiments, the second via hole exposes the second electrode, and the barrier layer is directly connected to the second electrode at the bottom of the second via hole.

[0015] In some embodiments, a rough structure is formed on the surface of the barrier layer.

[0016] In some embodiments, the first interlayer insulating layer includes a buffer layer and a first planar layer, and the first via hole and the second via hole both penetrate the buffer layer and the first planar layer.

[0017] In some embodiments, it also includes:

[0018] a second interlayer insulating layer covering the first planar layer and the barrier layer, wherein the transmission line is formed on a side of the second interlayer insulating layer away from the base substrate;

[0019] Furthermore, a third via hole is formed on the second interlayer insulating layer, and the third via hole is formed inside the first via hole and exposes the barrier layer.

[0020] In some embodiments, the third via hole is also formed inside the second via hole.

[0021] In some embodiments, the first via hole and the second via hole are square holes, and the third via hole is a square hole or a circular hole.

[0022] In some embodiments, a projection of the barrier layer on the base substrate is located within a projection range of the first electrode on the base substrate.

[0023] In a second aspect, an embodiment of the present application further provides a flat panel detector, comprising the flat panel detector substrate described in any of the above embodiments.

[0024] In a third aspect, the present application also provides a method for preparing a flat panel detector substrate, comprising:

[0025] providing a substrate base plate;

[0026] forming a thin film transistor on a substrate;

[0027] A photodiode is formed on a side of the thin film transistor away from the substrate, wherein the photodiode comprises a first electrode close to the substrate, a photodiode film layer and a second electrode of the substrate;

[0028] Forming a first interlayer insulating layer on a side of the second electrode away from the substrate, wherein at least one first via hole exposing the second electrode is formed on the first interlayer insulating layer;

[0029] forming a barrier layer covering at least one first via hole, wherein the barrier layer is electrically connected to the second electrode at the bottom of the first via hole;

[0030] A transmission line is formed on a side of the barrier layer away from the second electrode, and the transmission line is electrically connected to the barrier layer.

[0031] In some embodiments, the number of the first via holes is at least two.

[0032] In some embodiments, the following also include:

[0033] At least one second via hole is formed on the first interlayer insulating layer, the barrier layer covers the second via hole, and the barrier layer is a transparent conductive material.

[0034] The technical solution provided in the embodiment of the present application is that after the thin film transistor and the photodiode are manufactured and the first via hole is manufactured on the first interlayer insulating layer, a barrier layer covering the above-mentioned first via hole is formed, so that after the transmission line electrically connected to the barrier layer is formed, during the process of electrically connecting the transmission line to the second electrode, due to the blocking effect of the barrier layer, even if etching is performed again, the photodiode film layer will not be etched, thereby avoiding over-etching to the photodiode film layer to cause direct electrical connection between the transmission line and the first electrode of the photodiode, avoiding T-type defects, and further avoiding the phenomenon of abnormal bias loading, thereby improving product yield.

[0035] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0037] Figure 1 A cross-sectional schematic diagram of a flat panel detector substrate provided for related technology;

[0038] Figure 2 A schematic cross-sectional view of a flat panel detector substrate provided in an embodiment of the present application;

[0039] Figure 3 A schematic top view of a flat panel detector substrate provided in an embodiment of the present application;

[0040] Figure 4is a cross-sectional schematic diagram of forming a second via hole in an embodiment of the present application;

[0041] Figure 5 This is a schematic diagram of the effect of the change in the optical path when the light is incident in the embodiment of the present application;

[0042] Figure 6 This is a schematic diagram of providing a rough structure on the surface of the barrier layer in an embodiment of the present application;

[0043] Figure 7 This is a schematic diagram of the structure of a flat panel detector in an embodiment of the present application;

[0044] Figure 8 A schematic flow chart of a method for preparing a flat panel detector substrate provided in an embodiment of the present application;

[0045] Fig. 9 A schematic diagram of a specific process of a method for preparing a flat panel detector substrate provided in an embodiment of the present application;

[0046] Figure 10 to Figure 13 for Fig. 9 Schematic diagram of the structures corresponding to each step in the preparation method shown. DETAILED DESCRIPTION

[0047] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0048] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0049] In the description of the present application, “plurality” means two or more.

[0050] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0051] When describing some embodiments, the expression "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "electrically connected" indicates, for example, that two or more components are in direct physical or electrical contact, and may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0052] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0053] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0054] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0055] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and should not be construed as limiting the present application.

[0056] The manufacturing process of the Flat Panel X-Ray Detector (FPXD) substrate is relatively complex and usually requires 12 mask processes to complete. Figure 1 A cross-sectional schematic diagram of a flat panel detector substrate provided for related technology, such as Figure 1 As shown, the flat panel detector substrate includes a base substrate 100, and a thin film transistor 101 formed on the base substrate 100, wherein the thin film transistor 101 may include a gate 1012, a gate insulating layer 1013, an active layer 1014 and a source-drain electrode layer 1015, wherein the source-drain electrode layer may include a first electrode and a second electrode of the thin film transistor 101, wherein the first electrode may be a source electrode, and the second electrode may be a drain electrode, or vice versa. The gate insulating layer 1013 may be made of an inorganic insulating material such as SiNx, SiOx, SiNxOy, or an organic insulating material such as an organic resin or other suitable insulating material; the active layer 1014 may be made of an oxide semiconductor, an organic semiconductor, amorphous silicon or polycrystalline silicon, etc., without limitation herein.

[0057] The flat panel detector substrate may further include: a first passivation layer 102 covering the thin film transistor 101, a via hole exposing the first electrode of the thin film transistor is formed on the first passivation layer 102, and a photodiode is formed on the first passivation layer 102, the photodiode includes a first electrode 103, a photodiode film layer 104, and a second electrode 105. The first electrode 103 is electrically connected to the first electrode of the thin film transistor 101 through the via hole on the first passivation layer 102; optionally, the photodiode film layer 104 may include an N-type semiconductor layer, an intrinsic semiconductor layer, and a P-type semiconductor layer in order from bottom to top.

[0058] An interlayer insulating layer 107 may be formed above the photodiode, which may play an insulating role on the one hand and a flattening role on the other hand. The interlayer insulating layer 107 may be set according to the specific situation, for example, it may include a buffer layer 1071, a first flattening layer 1072, and a second passivation layer 1073, or a part of the layers thereof. Furthermore, a via hole needs to be formed in the interlayer insulating layer 107, and the via hole needs to penetrate the interlayer insulating layer 107 and expose the second electrode 105, so that the transmission line (Transfer Mode, which can be referred to as TM line) above the interlayer insulating layer 107 is connected to the second electrode 105 through the via hole. In the manufacturing process of the second electrode 105, it is disconnected (Open) due to the influence of foreign matter in the process. In some cases, the disconnection (Open) position is exactly located at the position where the via hole is formed in the interlayer insulating layer 107, which will expose the photodiode film layer 104 below. When etching the interlayer insulating layer 107 to form a via, the first flat layer 1072 can generally be achieved by wet etching, while the second passivation layer 1073 usually needs to be removed by dry etching. Dry etching will make it easy to directly etch the photodiode film layer 104 when the second electrode 105 is disconnected, thereby directly exposing the first electrode 103. In the subsequent TM line manufacturing process, the TM line will be directly overlapped with the first electrode 103, which will cause the photodiode film layer 104 to fail and form a T-type defect.

[0059] In addition, in some cases, e.g. Figure 1 When the interlayer insulating layer 107 includes a buffer layer 1071, a first planarization layer 1072 and a second passivation layer 1073, in the process of forming the via hole, a via hole A is usually formed in the first planarization layer 1072 first, and then a second passivation layer 1073 is formed above the first planarization layer 1072, and then a via hole B is formed in the second passivation layer 1073. The via hole A and the via hole B belong to a sleeve hole structure. At this time, if the via hole B is tangent to the via hole A, that is, the first planarization layer 1072 is exposed, then the detection unevenness (Mura) phenomenon will occur. Therefore, in the manufacturing process of the flat panel detector substrate, it is necessary to ensure that the via hole B cannot be tangent to the via hole A during the formation process. This undoubtedly increases the difficulty of process control in forming the above-mentioned via hole in the interlayer insulating layer 107.

[0060] In view of the above problems existing in the flat panel detector substrate in the related art, the embodiment of the present application provides a flat panel detector substrate. Figure 2 A schematic cross-sectional view of a flat panel detector substrate provided in an embodiment of the present application.

[0061] like Figure 2As shown, the flat panel detector substrate 10 provided in the embodiment of the present application may include:

[0062] Base substrate 200; wherein, the base substrate 200 can be a glass substrate, or other insulating layer substrate;

[0063] The thin film transistor 201 is used to control the switch of each pixel unit in the flat panel detector substrate. The specific type of the thin film transistor 201 is not limited. For example, a bottom gate type or a top gate type thin film transistor can be selected. Figure 2 The thin film transistor shown in is a bottom gate type, and generally the thin film transistor may further include a first electrode and a second electrode, the first electrode may be a source electrode, the second electrode may be a drain electrode, or vice versa;

[0064] A photodiode is formed on the side of the thin film transistor 201 away from the base substrate 200. The photodiode includes a first electrode 203 close to the base substrate 200, a photodiode film layer 204 and a second electrode 205 away from the base substrate 200. The photodiode film layer 204 may include an N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer from bottom to top. It is mainly used to form detection electron-hole pairs after detecting the target signal, thereby forming a detection current. The specific structure and materials used in the photodiode film layer 204 can refer to the solutions of related technologies and are not limited in the embodiments of the present application. In addition, the first electrode 203 of the above-mentioned photodiode will also be electrically connected to the first electrode of the thin film transistor 201. Specifically, it can be as follows Figure 2 As described in the illustrated embodiment, a first passivation layer 202 may be provided between the thin film transistor 201 and the photodiode, and a via may be provided in the first passivation layer 202 . The first electrode of the thin film transistor 201 may be electrically connected to the first electrode 203 of the photodiode through the via. The first electrode of the thin film transistor 201 may be the drain of the thin film transistor 201 .

[0065] A first interlayer insulating layer 206 is formed on the side of the second electrode 205 away from the base substrate 200, and at least one first via hole 207 exposing the second electrode 205 is formed on the first interlayer insulating layer; the first interlayer insulating layer 206 mainly plays the role of insulation and planarization, and can insulate and separate the second electrode 205 of the photodiode from other structures. The material of the first interlayer insulating layer 206 can usually be selected from a material with high insulation performance and stability, such as resin, and its thickness is relatively large, so as to play a role in planarizing the flat panel detector substrate, so that components such as the transmission line 209 can be manufactured on a relatively flat surface later, and the circuit inside the flat panel detector substrate can be protected from interference and damage from the external environment, such as humidity, dust, chemicals, etc.

[0066] A barrier layer 208 covers the at least one first via hole 207, and the barrier layer 208 is electrically connected to the second electrode 205 exposed at the bottom of the first via hole 207; the barrier layer 208 may be made of a conductive material, so as to be electrically connected to the second electrode 205. In the embodiment of the present application, the barrier layer 208 includes a metal oxide, and specifically may include at least one of indium tin oxide (ITO) and indium gallium zinc oxide (IGZO).

[0067] A transmission line 209 is formed on the side of the blocking layer 208 away from the second electrode 205, and the transmission line 209 is electrically connected to the blocking layer 208. The transmission line 209 can extract the detection current when the detection current is formed in the photodiode film layer 204, and a bias voltage can be applied according to actual needs. The transmission line 209 can be a conductive material layer, and the material can be a metal or a metal alloy, such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium or copper and other conductive materials, which can transmit the detection current in the flat panel detector substrate to the readout circuit.

[0068] The technical solution provided in the embodiment of the present application is as follows: after the thin film transistor 201 and the photodiode are manufactured and the first via hole 207 is formed on the first interlayer insulating layer 206, a blocking layer 208 covering the first via hole 207 is formed, so that after the transmission line 209 electrically connected to the blocking layer 208 is formed, during the process of electrically connecting the transmission line 209 to the second electrode 205, due to the blocking effect of the blocking layer 208, even if dry etching is performed again, the photodiode film layer 204 will not be etched, thereby avoiding over-etching of the photodiode film layer 204 and causing the transmission line 209 to be directly electrically connected to the first electrode 203 of the photodiode, avoiding T-type defects, and further avoiding the phenomenon of abnormal bias loading, thereby improving product yield.

[0069] Figure 3 A schematic top view of a flat panel detector substrate provided in an embodiment of the present application is shown in FIG. Figure 3As shown, the number of the first via holes 207 can be at least two. Specifically, the first via holes 207 can expose the second electrode 205, thereby realizing the electrical connection between the transmission line 209 and the second electrode 205. By setting a plurality of first via holes 207 in the first interlayer insulating layer 206, during the manufacturing process of the transmission line 209, even if there are poor processes or environmental foreign matter that cause the transmission line 209 to fail to overlap with the second electrode 205 in some of the first via holes 207, resulting in poor contact, the transmission line 209 can still be electrically connected to the second electrode 205 through other first via holes 207, thereby ensuring the success rate of the electrical connection between the transmission line 209 and the second electrode 205, thereby improving the product yield.

[0070] In some embodiments, Figure 4 Schematic diagram of a cross section of forming a second via hole in an embodiment of the present application. Figure 3 and Figure 4 As shown, the first interlayer insulating layer 206 may include at least one second via hole 210 in addition to the first via hole 207 , and the barrier layer 208 also covers the second via hole 210 , and the barrier layer 208 is a transparent conductive material.

[0071] The blocking layer 208 in this embodiment is a transparent conductive material, which can, on the one hand, enable the blocking layer 208 to be electrically connected to the second electrode 205 in the first via hole 207, and on the other hand, avoid blocking the light signal detected by the photodiode, so that the incident light from the outside can still be incident on the photodiode film layer 204, and the presence of the blocking layer 208 in the first via hole 207 and the second via hole 210 can refract and / or reflect the incident light, so that the incident light from the outside will no longer be incident nearly vertically into the photodiode film layer 204, but will be incident into the photodiode film layer 204 at a certain inclination angle, which can increase the optical path of the light in the photodiode film layer 204, thereby improving the photoelectric conversion efficiency of the photodiode film layer 204.

[0072] Especially when the first via hole 207 and / or the first via hole 210 is a structure that is wide at the top and narrow at the bottom, the surface of the blocking layer 208 is an inclined surface, which can better reflect the light at a certain inclined angle into the photodiode film layer 204, thereby increasing the optical path and obtaining a better improvement in photoelectric conversion efficiency.

[0073] It can be understood that when the flat panel detector substrate in the embodiment of the present application can be applied to X-ray detection, the above-mentioned light can be obtained by converting X-rays through cesium iodide or the like.

[0074] In some embodiments, the barrier layer 208 may be an indium tin oxide layer to fully utilize the conductive property and light transmittance of indium tin oxide.

[0075] Figure 5 Schematic diagram of the effect of the change of the optical path when the light is incident in the embodiment of the present application. Figure 5 As shown, there are two cases of light incidence, vertical incidence and non-vertical incidence. For the non-vertical incidence, that is, when the light is incident on the photodiode film layer 204 at a certain angle, the optical path of the light in the photodiode film layer 204 will be increased compared to the optical path of the vertically incident light. Increasing the optical path can increase the absorption rate of the light in the photodiode film layer 204, thereby effectively improving the photoelectric conversion efficiency of the photodiode film layer 204.

[0076] In some embodiments, the above Figure 4 As shown, the second via hole 210 also exposes the second electrode 205, and the barrier layer 208 is directly connected to the second electrode 205 at the bottom of the second via hole 210. This is mainly because the function of the barrier layer 208 is different from that of the first via hole 210, and the barrier layer 208 does not have to be directly connected to the second electrode 205 to achieve the conductive function. Therefore, the second via hole 210 in the embodiment of the present application may not expose the second electrode 205, but the second via hole 210 exposes the second electrode 205 and makes the barrier layer directly connected to the second electrode 205, so that the barrier layer 208 can better play the effect of increasing the optical path.

[0077] In some embodiments, the second via 210, like the first via 207, also exposes the second electrode 205, so that the first via 208 and the second via 210 can be manufactured in the same manufacturing process. At this time, the process parameters and dimensions of the two can be unified to obtain two types of vias with the same structure and size. The two can be manufactured simultaneously, thereby reducing the manufacturing process.

[0078] In some embodiments, as described above Figure 3 As shown, the second via holes 210 may be evenly arranged in multiple rows and columns.

[0079] In some embodiments, the surface of the barrier layer 208 may be further configured to have a rough structure. Figure 6 FIG. 2 is a schematic diagram of providing a rough structure on the surface of the barrier layer 208 in an embodiment of the present application. In some cases, the rough structure here may be a porous structure, which may be as follows: Figure 6At this time, the external incident vertical light can be reflected, refracted or diffusely reflected after passing through the above-mentioned rough structure, thereby better changing the propagation direction of the light, so that it changes from vertical incidence to incidence at a certain inclined angle, thereby increasing the optical path of the light in the photodiode film layer 204, increasing the light absorption rate, and thus improving the photoelectric conversion efficiency of the photodiode film layer 204.

[0080] In some embodiments, still referring to the above Figure 2 As shown, the first interlayer insulating layer 206 may specifically include a buffer layer 2061 and a first planarization layer 2062, and the first via hole 207 and the second via hole 210 both penetrate the buffer layer 2061 and the first planarization layer 2062. The material of the buffer layer 2061 may be aluminum oxide, silicon oxide, etc., which mainly improves the interface characteristics between different materials, reduces defects, and can improve the stability and performance of the overall structure; the first planarization layer 2062 can remove irregular shapes and surface defects.

[0081] In addition, in some embodiments, as described above Figure 2 As shown, the flat panel detector substrate may further include a second interlayer insulating layer 211, which covers the first planarization layer 2062 and the blocking layer 208, and the transmission line 209 is formed on the side of the second interlayer insulating layer 211 away from the base substrate 200; and a third via hole 212 is formed on the second interlayer insulating layer 211, and the third via hole 212 can be formed inside the first via hole 207 and expose the blocking layer 208 below, so that the transmission line 209 can be electrically connected to the blocking layer 208 through the third via hole 212, and further electrically connected to the second electrode 205 of the photodiode.

[0082] In the embodiment of the present application, although the third via hole 212 and the first via hole 207 also form a sleeve hole structure, the presence of the barrier layer 208 can prevent the two from being tangent to each other, thereby effectively preventing the first planarization layer 2062 from being exposed and causing the phenomenon of uneven detection (Mura), that is, the phenomenon of uneven grayscale will appear on the detection image.

[0083] In some cases, the third via hole 212 is also formed inside the second via hole 210 and exposes the barrier layer 208 .

[0084] In the embodiment of the present application, for the shapes of the first via hole 207, the second via hole 210 and the third via hole 212, any one of a square hole and a circular hole can be selected. For example, in some embodiments, the first via hole 207 and the second via hole 210 can be set as a square hole, and the third via hole 212 can be set as a square hole and a circular hole, wherein the combination of the square hole and the circular hole can improve the reflection and refraction effect of light. Figure 3 In the illustrated embodiment, each of the above-mentioned via holes is a square hole.

[0085] In addition, for the coverage range of the barrier layer 208 in the embodiment of the present application, its minimum range is to be able to cover the first via hole and the second via hole mentioned above, so as to achieve the technical effects recorded in the above embodiments; for its maximum coverage feedback, it can be as follows Figure 3 As shown, its projection on the base substrate 200 is located within the projection range of the first electrode 203 on the base substrate 200, so as to limit the formation of the blocking layer 208 in different pixel units of the flat panel detector substrate.

[0086] In some embodiments, a third passivation layer 213 , a top electrode 214 , and a second planarization layer 215 are sequentially formed on a side away from the base substrate 200 , wherein the top electrode 214 may be made of ITO material.

[0087] The present application also provides a flat panel detector, Figure 7 is a schematic diagram of the structure of a flat panel detector in an embodiment of the present application, such as Figure 7 As shown, the flat panel detector 30 includes a flat panel detector substrate 20, and the flat panel detector substrate 20 may include the above-mentioned Figure 2-Figure 6 Any of the flat panel detector substrates shown. The flat panel detector provided in the embodiments of the present application also has the technical effects described in the embodiments of the flat panel detector substrates described in the above embodiments.

[0088] The present application also provides a method for preparing a flat panel detector substrate, by which the above-mentioned Figure 2 The flat panel detector substrate 20 in the illustrated embodiment. Figure 8 A schematic diagram of a process for preparing a flat panel detector substrate provided in an embodiment of the present application, wherein the specific structure can be referred to Figure 2 As shown, Figure 8 As shown, the preparation method comprises the following steps:

[0089] Step 21: providing a base substrate 200;

[0090] Step 22: forming a thin film transistor 201 on the base substrate 200;

[0091] Step 23: forming a photodiode on a side of the thin film transistor 201 away from the base substrate 200, the photodiode comprising a first electrode 203 close to the base substrate 200, a photodiode film layer 204 and a second electrode 205 away from the base substrate 200, wherein the first electrode 203 is electrically connected to the first electrode of the thin film transistor 201;

[0092] In some embodiments, the photodiode film layer 404 may include an N-type semiconductor layer, an intrinsic semiconductor layer, and a P-type semiconductor layer in order from bottom to top. During the manufacturing process, the corresponding film layer material may be deposited first, and then a patterned mask may be formed and then etched to form a patterned photodiode film layer 104, such as Fig.10 After the photodiode film layer 204 is formed, a second electrode 105 may be formed by deposition on the side of the photodiode film layer 104 away from the base substrate 1011 . The second electrode 105 may be formed of indium tin oxide (ITO).

[0093] Step 24: forming a first interlayer insulating layer 206 on a side of the second electrode 205 away from the base substrate 200 , wherein at least one first via hole 207 exposing the second electrode 205 is formed on the first interlayer insulating layer 206 ;

[0094] Exemplarily, the material of the first interlayer insulating layer 207 may include materials such as resin, and its thickness is relatively large, so as to planarize the flat panel detector substrate. The first interlayer insulating layer 206 may be formed by deposition using plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition, and at least one first via hole 207 exposing the second electrode 205 is formed on the first interlayer insulating layer 206 through a patterning process such as masking and etching.

[0095] Step 25: forming a barrier layer 208 covering at least one first via hole 207 , wherein the barrier layer 208 is electrically connected to the second electrode 205 at the bottom of the first via hole 207 ;

[0096] For example, the blocking layer 208 may be deposited by any one of sputtering, thermal evaporation, plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, or electron cyclotron resonance chemical vapor deposition.

[0097] Step 26: forming a transmission line 209 on a side of the barrier layer 208 away from the first electrode 205, and the transmission line 209 is electrically connected to the barrier layer 206;

[0098] Exemplarily, the transmission line 209 can be formed by depositing on the side of the blocking layer 208 away from the second electrode 205 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, electron cyclotron resonance chemical vapor deposition or sputtering, wherein the material of the transmission line 209 can be metal, metal alloy, such as molybdenum, molybdenum-niobium alloy, aluminum, aluminum-neodymium alloy, titanium or copper and other conductive materials.

[0099] The technical solution provided in the embodiment of the present application is as follows: after the thin film transistor 201 and the photodiode are manufactured and the first via 207 is formed on the first interlayer insulating layer 206, a blocking layer 208 covering the first via 207 is formed, so that after the transmission line 209 electrically connected to the blocking layer 208 is formed, during the process of electrically connecting the transmission line 209 to the second electrode 205, due to the blocking effect of the blocking layer 208, even if dry etching is performed again, the photodiode film layer 204 will not be etched, thereby avoiding over-etching of the photodiode film layer 204, causing the transmission line 209 to be directly electrically connected to the first electrode 203 of the photodiode, and avoiding T-type defects.

[0100] Fig. 9 A specific flow chart of a method for preparing a flat panel detector substrate provided in an embodiment of the present application, which can be combined with Figure 10-13 The schematic diagram of the preparation process shown in the figure can be used to understand the preparation method of the flat panel detector substrate in the embodiment of the present application. Fig. 9 As shown, and also refer to Figure 10-13 The method for preparing the flat panel detector substrate provided in the embodiment of the present application may include the following steps:

[0101] Step 31: Complete the production of the first interlayer insulating layer 206 and the front film layer, which can be specifically as follows: Fig.10 As shown, this step is divided into five parts:

[0102] 1) The gate 2012 of the thin film transistor 201, the gate insulating layer 2013, the active layer 2014, the source-drain electrode layer 2015, the first passivation layer 202 and the first electrode 203 of the photodiode are sequentially formed on the base substrate 200 by a patterning process.

[0103] 2) The photodiode film layer 204 can be formed by deposition using a plasma enhanced chemical vapor deposition method or the like. The photodiode film layer 204 includes an N-type semiconductor layer, an intrinsic semiconductor layer and a P-type semiconductor layer. Specifically, the film materials of the N-type semiconductor layer, the intrinsic semiconductor layer and the P-type semiconductor layer can be sequentially deposited on the side of the first electrode 203 away from the substrate 200, and then patterned masking is performed and then etching is performed to form a patterned photodiode film layer 204.

[0104] 3) Forming a first interlayer insulating layer 206, the first interlayer insulating layer 206 includes a buffer layer 2061 and a first planarization layer 2062. The material of the first planarization layer 2062 is generally resin, and its thickness is relatively large, which can play a role in planarizing the flat panel detector substrate; the buffer layer 2061 can include an oxidized material, such as aluminum oxide, silicon oxide, etc., which can improve the interface characteristics between different materials and reduce defects. The first interlayer insulating layer 206 can be formed by plasma enhanced chemical vapor deposition and other methods.

[0105] 4) The second electrode 205 is deposited on the side of the photodiode film layer 204 away from the base substrate 200 by plasma enhanced chemical vapor deposition or sputtering, wherein the material of the second electrode 205 is a conductive material, and indium tin oxide ITO can be used in the embodiment of the present application.

[0106] 5) A first via hole 207 and a second via hole 210 are formed on the first interlayer insulating layer 206 through masking, etching and other patterning processes. The shapes and sizes of the first via hole 207 and the second via hole 210 may include various shapes such as square and circle, and are not limited to the examples shown in the drawings in this embodiment. In the embodiment of the present application, the number of the first via hole 207 and the second via hole 210 may be at least two, and both may be a structure with a wide top and a narrow bottom. The specific technical effects may refer to the description in the above embodiment.

[0107] Step 32: forming a barrier layer 208, which may be specifically as follows: Fig.11 shown.

[0108] Exemplarily, the barrier layer 208 can be deposited by sputtering, thermal evaporation or plasma enhanced chemical vapor deposition. The projection of the barrier layer 208 on the substrate 200 needs to be within the projection range of the first electrode 203 on the substrate 200 at most, and at least needs to cover the first via 207 and the second via 210. The material of the barrier layer 208 is mainly transparent conductive material, such as indium tin oxide ITO. In addition, the surface of the barrier layer 206 can be further designed as a surface roughness structure, for example, a porous structure. At this time, the vertical light incident from the outside can be reflected, refracted or diffusely reflected after passing through the above roughness structure, thereby better changing the propagation direction of the light, so that it changes from vertical incidence to incidence at a certain tilt angle, thereby increasing the optical path of the light in the photodiode film layer 204, increasing the light absorption rate, and thus improving the photoelectric conversion efficiency of the photodiode film layer 204.

[0109] Step 33: Fig.12 As shown, a second interlayer insulating layer 211 and a transmission line 209 are formed, and the second interlayer insulating layer 211 may be a second passivation layer;

[0110] For example, the second passivation layer may be formed by thermal evaporation or plasma enhanced chemical vapor deposition, which covers the planarization layer 1062 and the barrier layer 208 and may penetrate into the first via hole 207 and the second via hole 210 .

[0111] Furthermore, a third via 212 can be formed on the second passivation layer by using masking, etching and other composition processes to expose the blocking layer 208, and then a transmission line 209 can be formed by plasma enhanced chemical vapor deposition or sputtering, and the transmission line 209 can be electrically connected to the blocking layer 208 through the third via 212.

[0112] Step 34: Fig.13 As shown, a third passivation layer 213, a top electrode 214 and a second planarization layer 215 are formed;

[0113] Exemplarily, a third passivation layer 213 , a top electrode 214 and a second planarization layer 215 may be formed in sequence on a side away from the base substrate 200 , wherein the top electrode 214 may be made of ITO material.

[0114] The technical solution provided by the embodiment of the present application, in which the blocking layer 208 is provided, can avoid T-shaped defects on the one hand, and further avoid the phenomenon of abnormal bias loading, thereby improving product quality; on the other hand, it can also avoid the tangent phenomenon when the sleeve hole structure appears, and thus can effectively avoid the first planarization layer 2062 being exposed and causing the phenomenon of detection unevenness (Mura); further, when the blocking layer 208 is a transparent photoelectric material, the first via hole 207 and the second via hole 208 formed in the first interlayer insulating layer 206 are used to make the blocking layer 208 have the functions of reflection, scattering and diffuse reflection, so as to change the incident angle of light to the photodiode film layer 204, increase the optical path of light in the photodiode film layer 204, and improve the absorption rate of the photodiode film layer 204 to light, and finally improve the photoelectric conversion efficiency, and the effect is better when the first via hole 207 and the second via hole are wide at the top and narrow at the bottom; further, if the number of the above-mentioned first via holes 207 is multiple, the overlap success rate between the transmission line 209 and the second electrode 205 of the photodiode can be guaranteed.

[0115] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A flat panel detector substrate, characterized in that: include: substrate substrate; A thin film transistor formed on the substrate; A photodiode is formed on a side of the thin film transistor away from the base substrate, the photodiode comprises a first electrode close to the base substrate, a photodiode film layer and a second electrode away from the base substrate, the first electrode is electrically connected to a first electrode of the thin film transistor; A first interlayer insulating layer is formed on a side of the second electrode away from the base substrate, wherein at least one first via hole exposing the second electrode is formed on the first interlayer insulating layer; a barrier layer covering the at least one first via hole, the barrier layer being electrically connected to the second electrode at the bottom of the first via hole; A transmission line is formed on a side of the barrier layer away from the second electrode, and the transmission line is electrically connected to the barrier layer.

2. The substrate according to claim 1, characterized in that The number of the first via holes is at least two.

3. The substrate according to claim 1, characterized in that At least one second via hole is also formed on the first interlayer insulating layer, the barrier layer covers the second via hole, and the barrier layer is made of a transparent conductive material.

4. The substrate according to claim 3, characterized in that The first via hole and / or the second via hole has a structure that is wide at the top and narrow at the bottom.

5. The substrate according to claim 3, characterized in that The second via hole exposes the second electrode, and the barrier layer is directly connected to the second electrode at the bottom of the second via hole.

6. The substrate according to claim 3, characterized in that A rough structure is formed on the surface of the barrier layer.

7. The substrate according to claim 3, characterized in that The first interlayer insulating layer includes a buffer layer and a first planarization layer, and the first via hole and the second via hole both penetrate the buffer layer and the first planarization layer.

8. The substrate according to claim 7, characterized in that Also includes: a second interlayer insulating layer covering the first planar layer and the barrier layer, wherein the transmission line is formed on a side of the second interlayer insulating layer away from the base substrate; A third via hole is formed on the second interlayer insulating layer, wherein the third via hole is formed inside the first via hole and exposes the barrier layer.

9. The substrate according to claim 8, characterized in that The third via hole is also formed inside the second via hole and exposes the barrier layer.

10. The substrate according to claim 8, characterized in that The first via hole and the second via hole are square holes, and the third via hole is a square hole or a circular hole.

11. The substrate according to any one of claims 1 to 10, characterized in that: The projection of the barrier layer on the base substrate is located within the projection range of the first electrode on the base substrate.

12. A flat panel detector, characterized in that: The invention comprises the flat panel detector substrate as described in any one of claims 1 to 11.

13. A method for preparing a flat panel detector substrate, characterized in that: include: providing a substrate base plate; forming a thin film transistor on the base substrate; A photodiode is formed on a side of the thin film transistor away from the base substrate, wherein the photodiode comprises a first electrode close to the base substrate, a photodiode film layer and a second electrode away from the base substrate, wherein the second electrode is electrically connected to the first electrode of the thin film transistor; Forming a first interlayer insulating layer on a side of the second electrode away from the substrate, wherein at least one first via hole exposing the second electrode is formed on the first interlayer insulating layer; forming a barrier layer covering the at least one first via hole, wherein the barrier layer is electrically connected to the second electrode at the bottom of the first via hole; A transmission line is formed on a side of the barrier layer away from the second electrode, and the transmission line is electrically connected to the barrier layer.

14. The preparation method according to claim 13, characterized in that: The number of the first via holes is at least two.

15. The preparation method according to claim 13, characterized in that: Also includes: At least one second via hole is formed on the first interlayer insulating layer, the barrier layer covers the second via hole, and the barrier layer is a transparent conductive material.

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