Array substrate, manufacturing method and display panel

Abstract

The invention provides an array substrate, a manufacturing method and a display panel. The array substrate comprises a substrate, a planarization layer is arranged on the substrate, a groove is formed in the side, away from the substrate, of the planarization layer, a metal layer is arranged on the side, away from the substrate, of the planarization layer and comprises a first metal wire and a second metal wire, the first metal wire is located in the groove, and the second metal wire is located in the groove. In the thickness direction of the planarization layer, the first metal wiring and the second metal wiring are at different heights. Through the design, the metal wiring is configured at different heights of the organic glue. The risk of wiring short circuit caused by foreign matters or metal residues on the same layer can be reduced, so that the product yield is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to an array substrate, a manufacturing method and a display panel. Background Art

[0002] The driving circuit of OLED is usually configured on a substrate. During the setting, there is a layer where metal wirings of different types / purposes are configured at the same time (for example, Vdata line and Vdd signal line are configured on a planarization layer of a certain layer). During the process stage of this layer, due to fluctuations in array process equipment parameters or the influence of foreign matter in the chamber, more foreign matter or residue increases, and there are defects caused by short circuits and foreign matter between different metal wirings, which in turn affects the yield of the product. Summary of the invention

[0003] The object of the present invention is to provide an array substrate, a manufacturing method and a display panel to solve the existing problem of arranging different metal wirings on the same layer and improve the yield.

[0004] To achieve the above object, the present invention provides an array substrate, comprising:

[0005] Substrate,

[0006] A planarization layer is disposed on the substrate, and a groove is disposed on a side of the planarization layer away from the substrate.

[0007] A metal layer is disposed on the side of the planarization layer away from the substrate, the metal layer includes a first metal wiring and a second metal wiring, and the first metal wiring is located in the groove.

[0008] In the thickness direction of the planarization layer, the first metal wiring and the second metal wiring are at different distances from the substrate. With such a design, the metal wiring is arranged at different heights of the organic glue. The risk of wiring short circuit caused by foreign matter or metal residue in the same layer can be reduced, thereby improving product yield.

[0009] Preferably, the first metal wiring and the second metal wiring are arranged at a projection interval on the planarization layer side;

[0010] Preferably, a surface of the first metal wiring facing away from the substrate is lower than or flush with a surface of the planarization layer facing away from the substrate;

[0011] Preferably, the first metal wiring and the second metal wiring extend in the same direction;

[0012] Preferably, a plurality of the first metal wirings and a plurality of the second metal wirings are alternately arranged on a side of the planarization layer facing away from the substrate.

[0013] Preferably, in the array substrate,

[0014] The depth of the groove in the thickness direction of the planarization layer is the same as or substantially the same as the thickness of the second metal wiring.

[0015] Preferably, the thickness of the planarization layer is between 1.6 μm and 2.0 μm.

[0016] Preferably, the cross section of the groove is in the shape of a rectangular parallelepiped;

[0017] Preferably, the groove is prepared by a semi-transparent mask plate;

[0018] Preferably, the semi-transparent mask plate has a first light-transmitting portion and a second light-transmitting portion, the light transmittance of the first light-transmitting portion is greater than that of the second light-transmitting portion, and the first light-transmitting portion is used to form the groove.

[0019] Preferably, a light-emitting layer and an encapsulation layer are further provided on the side of the metal layer away from the substrate, and the light-emitting layer includes a plurality of light-emitting units;

[0020] A driving array layer is further provided on a side of the planarization layer close to the substrate, and the driving array layer includes a plurality of driving circuits corresponding to the light-emitting units;

[0021] In the extending direction of the first metal wiring, the plurality of driving circuits are connected to one of the first metal wiring and one of the second metal wiring;

[0022] Preferably, the first metal wiring and the second metal wiring are used to transmit a power supply voltage signal and a data voltage signal to the driving circuit respectively.

[0023] The present invention provides a method for preparing an array substrate, which comprises the following steps:

[0024] coating a planarization layer on the substrate;

[0025] Performing patterning on the planarization layer using a semi-transparent mask plate to form grooves on the planarization layer;

[0026] Preparing a metal layer on the planarization layer, and depositing a portion of the metal layer into the groove;

[0027] The metal layer is patterned to obtain a first metal wiring and a second metal wiring at different heights along the thickness direction of the planarization layer by etching, and the first metal wiring is located in the groove.

[0028] Preferably, before the step of preparing a metal layer on a planarization layer, the step further includes:

[0029] Ashing process to remove foreign matter or residual glue on the planarization layer.

[0030] Preferably, the ashing process takes between 20s and 45s.

[0031] Preferably, the planarization layer is stacked on the substrate or on the passivation layer.

[0032] Preferably, the mask plate is configured to have a first light-transmitting portion and a second light-transmitting portion, and the light transmittance of the first light-transmitting portion is greater than that of the second light-transmitting portion, the first light-transmitting portion is used to form a groove, and the transparency of the first light-transmitting portion is between 40%→60%.

[0033] Preferably, the depth of the groove in the thickness direction of the planarization layer is the same as or slightly deeper than the thickness of the metal layer.

[0034] Preferably, the upper photoresist covering the metal layer in the groove and the upper photoresist covering the metal layer outside the groove do not contact each other in their projections on the planarization layer side.

[0035] Preferably, the metal layer is prepared on a planarization layer, and part of the metal is deposited into the groove, including preparing the metal layer by physical vapor deposition or sputtering, and part of the metal layer is deposited into the groove,

[0036] Preferably, the metal deposited into the groove does not protrude from the planarization layer.

[0037] Preferably, (the top of) the metal deposited into the groove does not protrude beyond (the plane of) the planarization layer.

[0038] An embodiment of the present application provides a display panel, which includes the above-mentioned array substrate or the array substrate prepared by the above-mentioned preparation method.

[0039] The array substrate proposed in the present application optimizes the layout of the metal layer on the planarization layer (also called the organic glue layer), and the metal layer includes a first metal wiring and a second metal wiring. The first metal wiring and the second metal wiring are at different heights in the thickness direction of the planarization layer (i.e., they are at different distances from the substrate), and their projections on the side of the planarization layer are spaced apart (i.e., not in contact), which can reduce the risk of wiring short circuits between the first metal wiring and the second metal wiring due to foreign matter or metal residues, thereby improving product yield. The preparation method of the array substrate proposed in the present application makes the planarization layer (organic glue) of different thicknesses by cleverly using the characteristics of the Halftone yellow light process, and the first metal wiring (located in the groove) and the second metal wiring are arranged on film layers of different heights, thereby reducing the probability of defects. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 is a schematic top view of an array substrate;

[0042] Figure 1a A schematic diagram of a structure in which different metals are arranged on the same planarization layer in an existing array substrate;

[0043] Figure 2 It is a cross-sectional schematic diagram of depositing a planarization layer according to an embodiment of the present application;

[0044] Figure 3 To use the mask Figure 2 Schematic diagram of preparing grooves in a planarization layer;

[0045] Figure 4 For Figure 3 Schematic diagram of preparing a metal layer on the planarization layer shown;

[0046] Figure 5 For Figure 4 Schematic diagram of coating photoresist on the metal layer shown;

[0047] Figure 6 For Figure 5 Schematic diagram of the metal layer after etching shown;

[0048] Figure 7 For Figure 6 The cross-sectional diagram shown is of the etched metal layer after the photoresist is stripped off. DETAILED DESCRIPTION

[0049] The preferred embodiments of the present invention are described below with reference to the drawings in the specification to prove that the present invention can be implemented. The embodiments of the invention can fully introduce the present invention to those skilled in the art, making its technical content clearer and easier to understand. The present invention can be embodied through many different forms of embodiments of the invention, and the protection scope of the present invention is not limited to the embodiments mentioned in the text.

[0050] In the drawings, components with the same structure are indicated by the same numerical reference numerals, and components with similar structures or functions are indicated by similar numerical reference numerals. The size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thickness of the components is appropriately exaggerated in some places in the drawings.

[0051] In addition, the following descriptions of the various embodiments of the invention are made with reference to the attached diagrams to illustrate specific embodiments of the invention that the present invention can be implemented with. The directional terms mentioned in the present invention, such as "upper", "lower", "front", "back", "left", "right", "inner", "outer", "side", etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are for better and clearer description and understanding of the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", "third", etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0052] When some components are described as being "on" another component, the component may be directly placed on the other component; there may also be an intermediate component on which the component is placed, and the intermediate component is placed on the other component. When a component is described as being "mounted to" or "connected to" another component, the two may be understood to be directly "mounted" or "connected", or one component may be indirectly "mounted to" or "connected to" another component through an intermediate component. Mask plates are sometimes referred to as masks.

[0053] In related display technologies, a 7T1C (7 thin film transistors and 1 capacitor) type pixel driving circuit is usually used to drive the display panel, that is, a single light-emitting unit has a driving circuit driven by 7 thin film transistors and 1 capacitor to emit light. Figure 1 As shown, it includes a substrate 40, a display area 41 is provided on one side of the substrate 40, and a plurality of light-emitting units 411 are provided in the display area 41. The light-emitting unit 411 is matched with a corresponding pixel driving circuit (not shown), and the pixel driving circuit is electrically connected to the matching Vdata line and Vdd signal line (such as the Vdata line and Vdd signal line located at the side where the pixel driving circuit is electrically connected away from the substrate). When this type of driving circuit is configured on the array substrate, a 4-layer metal routing design is usually used. There is a layer where different metal wirings (such as Vdata line and Vdd signal line) are configured at the same time. In the process stage of this layer, due to the fluctuation of array process equipment parameters or the influence of foreign matter in the chamber, foreign matter or residue increases, resulting in poor current lines and burn-in (such defects can be found in the subsequent lighting or aging process). The applicant analyzed the process of configuring different metal wirings on a certain layer. In the current process, after the organic glue (PLN2) planarization layer 10 is set on the substrate 40, a metal layer (M4 metal layer) is made on it by physical vapor deposition, and then different metal wirings 31 / 32 (metal M4 routing) are made by yellow light, etching, and stripping, that is, Vdd and Vdata routing are made, and then the organic glue (PLN3) planarization layer 20 is made. The cross-sectional effect is as follows. Figure 1aWhen making Vdd and Vdata routing in the M4 metal layer, due to the parameter fluctuation of the equipment or the influence of foreign matter in the chamber, the M4 layer has more foreign matter or residue, which shows poor performance (such as line shortage or display abnormality) when powered on. In other types of different metal wiring drive circuits configured at the same time in a certain layer (such as 7T2C, 8T2C, 9T2C), the applicant has also found similar problems.

[0054] Based on the above research findings of the applicant, the existing driving circuit is improved. Without changing the existing driving circuit topology or significantly changing the process flow, the configuration of different (type / purpose) metal wirings (such as arranging wiring for passing voltage Vdd and wiring for transmitting write voltage Vdata) on the same planarization layer (i.e., organic glue layer) is optimized to reduce or even eliminate the risk of wiring short circuits between different metal wirings due to foreign matter or metal residues when different metal wirings / routings are configured on the same planarization layer, thereby improving the yield of the product.

[0055] To this end, the present application proposes an array substrate, a manufacturing method and a display panel.

[0056] See also Figure 7 The array substrate includes a substrate 110, a planarization layer 120 is disposed on the substrate 110, a groove 121 is disposed on the side of the planarization layer 120 away from the substrate, a metal layer is disposed on the planarization layer, the metal layer includes a first metal wiring 131 and a second metal wiring 132, and the first metal wiring is located in the groove 131, and the first metal wiring 131 and the second metal wiring 132 are at different distances from the substrate 110 in the thickness direction of the planarization layer (y direction). Through such a design, the first metal wiring and the second metal wiring are disposed on the planarization layer, and the first metal wiring and the second metal wiring are at different heights in the thickness direction of the planarization layer. The projection interval between the first metal wiring 131 and the second metal wiring 132 on the side of the planarization layer 120 is arranged (that is, the first metal wiring 131 and the second metal wiring 132 are not in contact), so that the risk of wiring short circuit between the first metal wiring 131 and the second metal wiring 132 on the same planarization layer 120 due to foreign matter or metal residue can be reduced, so as to improve the product yield. In this embodiment, the thickness (in the y direction) of the planarization layer 120 is between 1.6 μm and 2.0 μm, and its cross section is in the shape of a rectangular parallelepiped. Preferably, the surface of the first metal wiring 131 on the side facing away from the substrate 110 is lower than or flush with the side of the planarization layer 120 facing away from the substrate 110. Preferably, the first metal wiring 131 and the second metal wiring 132 extend in the same direction. Preferably, a plurality of first metal wirings and a plurality of second metal wirings are alternately arranged on the side of the planarization layer facing away from the substrate.

[0057] The substrate may be a flexible substrate such as PI (polyimide), or a rigid substrate such as glass, which is not limited here. In one embodiment, a passivation layer is disposed on the substrate, and the planarization layer is stacked on the passivation layer.

[0058] In one embodiment, the depth of the groove is the same or substantially the same as the thickness of the second metal wiring in the thickness direction of the planarization layer. During preparation, the groove can be prepared by a semi-transparent mask. Preferably, the semi-transparent mask has a first light-transmitting portion and a second light-transmitting portion, and the light transmittance of the first light-transmitting portion is greater than that of the second light-transmitting portion, and the first light-transmitting portion is used to form the groove.

[0059] In an embodiment of the present invention, an array substrate is also provided, on which a light-emitting layer, an encapsulation layer, etc. are also provided. The light-emitting layer, the encapsulation layer, etc. can adopt existing implementations and are not limited here. The light-emitting layer includes a plurality of light-emitting units, and a driving array layer is also provided on the side of the planarization layer close to the substrate, and the driving array layer includes a plurality of driving circuits arranged corresponding to the light-emitting units; in the extension direction of the first metal wiring, the plurality of driving circuits are connected to a first metal wiring and a second metal wiring. Preferably, the first metal wiring and the second metal wiring are used to transmit a power supply voltage signal and a data voltage signal to the driving circuit respectively.

[0060] In an embodiment of the present invention, a method for preparing an array substrate is also provided. Figure 2-Figure 7 , the preparation method comprises:

[0061] A groove is made on the planarization layer (also called the organic glue layer). In this step, a semi-transparent mask plate can be used to make the groove. Figure 3 The mask plate 200 includes a semi-transparent area 210, which matches the groove prepared subsequently, and changes the transparency of the patterned position (i.e., the groove) of the mask plate. The mask plate has a first light-transmitting portion and a second light-transmitting portion, and the transmittance of the first light-transmitting portion is greater than that of the second light-transmitting portion. The first light-transmitting portion is used to form the groove.

[0062] The transparency is between 40% → 60% (for example, the transparency is 50%), and the transparency of the mask can be 0% → 50% → 0%. A groove is prepared at the position corresponding to the semi-transparent match (i.e., the position of the data routing). During the production, yellow light is used to pass through the mask 200. After the yellow light process is completed, a pattern (i.e., a groove) appears on the planarization layer. The depth of the groove in the thickness direction of the planarization layer is related to the thickness h of the subsequent metal layer (see Figure 4) or configured to be slightly deeper than the thickness of the metal layer. In this way, in the subsequent metal layer preparation process, part of the metal is deposited into the groove (preferably the metal deposited into the groove does not protrude from the planarization layer), and physical isolation can be achieved through etching. In other embodiments, the groove can be made on the planarization layer by photolithography.

[0063] A metal layer is prepared on a planarization layer, and part of the metal of the metal layer is deposited into the groove. In this step, see Figure 4 , deposit a metal layer (such as an M4 metal layer, which can be made of molybdenum, aluminum, or titanium-aluminum-titanium) on the planarization layer 120, and part of the metal is deposited into the groove (preferably, the metal deposited into the groove does not protrude from the planarization layer), and the thickness of the metal layer deposited into the groove is the same or substantially the same as the thickness of the metal layer outside the groove. For example, the metal layer is prepared on the planarization layer on the groove side by sputtering.

[0064] Coating photoresist solvent on metal layer Figure 5 , and use the yellow light and the mask plate to cooperate to obtain a photoresist of a preset pattern, the photoresist 140 partially covers the metal layer deposited in the groove, and partially covers the metal layer outside the groove (the photoresist covering the metal layer deposited in the groove and the photoresist covering the metal layer outside the groove do not touch the projection on the flattening layer side, so that the metal in the groove is physically separated / not in contact with the metal outside the groove after etching, avoiding the risk of short circuit between the metal in the groove and the metal outside the groove due to foreign matter or metal residue). In this step, a yellow light mask can be used to make two layers of metal routing (a yellow light mask can only make a conventional understanding of one layer of metal routing). Through this design adjustment, the risk of short circuit between different routings due to foreign matter or metal residue on the same flattening layer can be reduced, and the yield can be improved. The photoresist contains photosensitive materials, and the material properties will change after being exposed to specific light. The light can be passed through the mask plate with a designed circuit pattern and shine on the photoresist, and the photoresist exposed will change to obtain a preset pattern. Photoresist is mainly composed of four parts: film-forming resin, photosensitive agent, solvent and additives. In a typical photoresist composition, 50% to 90% is solvent, 10% to 40% is film-forming resin, photosensitive agent accounts for 1% to 6%, and surfactants, leveling agents and other additives account for less than 1%.

[0065] Different metal wirings are obtained on a planarization layer by etching and stripping (the first metal wiring and the second metal wiring are obtained at different heights along the thickness direction, and the first metal wiring is located in the groove). Figure 6 and Figure 7, different metal wirings 131 / 132 are obtained on a planarization layer through etching (etching away the metal layer not covered by the photoresist) and stripping processes. The metal wirings 131 / 132 are at different heights in the thickness direction (y direction) of the planarization layer 120. The projections of the metal wirings 131 / 132 on the side of the planarization layer 120 are not in contact (i.e., they are not in contact in the x direction of the planarization layer 120), which reduces the risk of short circuits caused by foreign matter or metal residues between the metal wirings 131 / 132, thereby improving the yield. In this embodiment, the etching and stripping processes are existing processes that can meet the requirements of etching the metal layer, such as using ECCP (i.e., enhanced capacitively coupled plasma etching) and ICP (i.e., inductively coupled plasma etching) to etch a preset pattern (metal wiring), and then stripping the photoresist above the metal wiring, which is not limited here. In addition, the preparation method of other layers of the array substrate in this embodiment can refer to the prior art and is not elaborated in detail here.

[0066] In one embodiment, the method includes depositing a planarization layer, in which step, see Figure 2 A planarization layer 120 is deposited on the substrate 110 (or other film layer), and the cross section of the deposited planarization layer is a rectangular parallelepiped, or the cross section of the deposited planarization layer is a rectangular parallelepiped after the morphology is adjusted.

[0067] In one embodiment, before the step of preparing a metal layer on a planarization layer, an ashing process is also included to remove foreign matter on the planarization layer. The residual glue or uneven state in the groove is cleaned by the ashing process. In this embodiment, the ashing (Asher) time is between 20s-45s, which is higher than the conventional time (usually Asher time is 16s). The thickness of the planarization layer (also called organic glue) (PLN2 film thickness) is greater than 1.6μm and less than 2.0μm (such as the film thickness is 1.7um).

[0068] Preferably, a shaping process is further included after the ashing process, and the thickness and morphology of the planarization layer are adjusted through the shaping process.

[0069] In one embodiment, a metal layer is prepared on a planarization layer, and the metal layer is deposited into the groove, including preparing a metal layer (such as an M4 metal layer) by physical vapor deposition, depositing part of the M4 metal layer into the groove, applying photoresist on the metal layer, and then performing a yellow light process, setting an optical glue (first optical glue) in the depression above the portion of the M4 metal layer deposited into the groove, and setting an optical glue (second optical glue) of a preset pattern in the non-groove portion of the M4 metal layer. After a subsequent etching process, a metal wiring of a preset pattern is etched out, and the metal routing in the groove (such as forming a subsequent Data line / Vdata line) and the metal routing outside the groove (such as forming a subsequent Vdd line) are physically cut off and are at different heights of the planarization layer, thereby avoiding the risk caused by foreign matter or metal residue between the two metal routings. Compared with the current method in which a yellow light mask can only make one layer of metal routing / wiring, this method can use a yellow light mask to make two layers of metal (at different heights) routing / wiring, which can reduce the risk of routing short circuits caused by foreign matter or metal residues on the same layer, and achieve improved yield.

[0070] In one embodiment, after obtaining different metal wirings 131 / 132, a planarization layer 1 is deposited on the metal wirings 131 / 132. In this step, the planarization layer 1 is deposited on the metal wirings 131 / 132, which facilitates subsequent processes (such as the production of M1 metal layer / M2 metal layer) to obtain an array substrate.

[0071] In an embodiment of the present invention, a display panel is also provided, which may be an OLED (Organic Light-Emitting Diode) display panel, which includes the above-mentioned array substrate and a light-emitting layer, an encapsulation layer, a polarizing layer, a touch layer and a cover plate arranged on the array substrate. The display panel can be arranged on any terminal device with a display function, such as a mobile phone, a laptop computer, a tablet computer, a car display, etc.

[0072] In the array substrate and display panel provided in the embodiments of the present invention, by optimizing the layout of metal wiring, when two or more metal wirings / routings are set on a planarization layer, they are configured at different heights (in the thickness direction of the planarization layer). This can reduce the risk of arranging metal wirings with different purposes / functions on the same planarization layer (also called an organic glue layer), such as the risk of foreign matter or metal residues between the routing for transmitting the voltage Vdd and the routing for transmitting the write voltage Vdata, thereby improving the yield of the display panel.

[0073] Although the present invention is described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the present invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that the various dependent claims and features described herein may be combined in a manner different from that described in the original claims. It should also be understood that features described in conjunction with individual embodiments may be used in other described embodiments.

Claims

1. An array substrate, characterized in that: include: Substrate, A planarization layer is disposed on the substrate, and a groove is disposed on a side of the planarization layer away from the substrate. A metal layer is disposed on the side of the planarization layer away from the substrate, the metal layer includes a first metal wiring and a second metal wiring, and the first metal wiring is located in the groove. In a thickness direction of the planarization layer, the first metal wiring and the second metal wiring are at different distances from the substrate.

2. The array substrate according to claim 1, characterized in that: The projections of the first metal wiring and the second metal wiring on the planarization layer side are arranged at intervals; Preferably, a surface of the first metal wiring facing away from the substrate is lower than or flush with a surface of the planarization layer facing away from the substrate; Preferably, the first metal wiring and the second metal wiring extend in the same direction; Preferably, a plurality of the first metal wirings and a plurality of the second metal wirings are alternately arranged on a side of the planarization layer facing away from the substrate.

3. The array substrate according to claim 1, characterized in that: In the thickness direction of the planarization layer, the depth of the groove is the same or substantially the same as the thickness of the second metal wiring. Preferably, the thickness of the planarization layer is between 1.6 μm and 2.0 μm.

4. The array substrate according to claim 1, wherein: The cross section of the groove is in the shape of a rectangular parallelepiped; Preferably, the groove is prepared by a semi-transparent mask plate; Preferably, the semi-transparent mask plate has a first light-transmitting portion and a second light-transmitting portion, the light transmittance of the first light-transmitting portion is greater than that of the second light-transmitting portion, and the first light-transmitting portion is used to form the groove.

5. The array substrate according to claim 1, wherein: A light-emitting layer and an encapsulation layer are further provided on the side of the metal layer away from the substrate, and the light-emitting layer includes a plurality of light-emitting units; A driving array layer is further provided on a side of the planarization layer close to the substrate, and the driving array layer includes a plurality of driving circuits corresponding to the light-emitting units; In the extending direction of the first metal wiring, the plurality of driving circuits are connected to one of the first metal wiring and one of the second metal wiring; Preferably, the first metal wiring and the second metal wiring are used to transmit a power supply voltage signal and a data voltage signal to the driving circuit respectively.

6. A method for preparing an array substrate, characterized in that: The preparation method comprises the following steps: Coating a planarization layer on a substrate, patterning the planarization layer using a mask plate, and making grooves on the planarization layer; A metal layer is prepared on the planarization layer, and a portion of the metal layer is deposited into the groove. The metal layer is patterned, and a first metal wiring and a second metal wiring are obtained on the planarization layer at different heights along the thickness direction thereof by etching, wherein the first metal wiring is located in the groove.

7. The method for preparing an array substrate according to claim 6, wherein: Before the step of preparing a metal layer on a planarization layer, the step further includes: Ashing process to remove foreign matter or residual glue on the planarization layer. Preferably, the ashing process takes between 20s and 45s. Preferably, the planarization layer is stacked on the substrate or on the passivation layer.

8. The method for preparing an array substrate according to claim 6, wherein: The mask plate is configured to have a first light-transmitting portion and a second light-transmitting portion, and the light transmittance of the first light-transmitting portion is greater than that of the second light-transmitting portion, the first light-transmitting portion is used to form a groove, and the transparency of the first light-transmitting portion is between 40%→60%, Preferably, the depth of the groove in the thickness direction of the planarization layer is the same as or slightly deeper than the thickness of the metal layer. Preferably, the upper photoresist covering the metal layer in the groove and the upper photoresist covering the metal layer outside the groove do not contact each other in their projections on the planarization layer side.

9. The method for preparing an array substrate according to claim 6, wherein: The step of preparing a metal layer on a planarization layer and depositing part of the metal into the groove comprises preparing the metal layer by physical vapor deposition or sputtering, and depositing part of the metal layer into the groove. Preferably, the metal deposited into the groove does not protrude from the planarization layer.

10. A display panel, characterized in that: The invention comprises an array substrate as claimed in any one of claims 1 to 5 or an array substrate prepared by the preparation method as claimed in any one of claims 6 to 9.

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