Wafer warping detection structure and detection method
By setting non-parallel plate capacitance measurement board components on both sides of the wafer to detect the difference in capacitance value, the problem that the prior art cannot detect the intermediate frequency wrigility warpage of the wafer is solved, and accurate detection of the degree of warpage of the wafer is achieved and process improvement is achieved.
Patent Information
- Application Number
- CN202411856303.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-16
- Publication Date
- 2025-03-18
AI Technical Summary
The prior art cannot detect the intermediate frequency wrigility warpage of wafers, resulting in the inability of manufacturers to improve the process and improve the processing quality of wafers.
By setting non-parallel plate capacitance measurement board components on both sides of the wafer to be tested, and using the capacitance measurement equipment to detect the difference in capacitance values on both sides, accurate detection of the degree of warping of the wafer's intermediate frequency wrigation is achieved.
This method can effectively detect the degree of warping of the intermediate frequency wrigormity of the wafer, helping manufacturers improve processes and improve the processing quality of the wafer.
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Figure CN119642693A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of wafer detection technology, and in particular to a wafer warpage detection structure and a detection method. Background Art
[0002] In semiconductor manufacturing and wafer processing, there are usually three types of wafer deformation: Bow, Roughness, and Waviness. Bow refers to the overall deformation of the wafer, the bending of the center of the wafer relative to the edge, and the overall bow-shaped bending. Roughness is the microscopic roughness of the wafer surface, usually referring to the surface unevenness with wavelengths from nanometers to micrometers. Waviness is the medium-frequency waviness of the wafer surface, usually referring to the surface unevenness with a longer wavelength, usually hundreds of microns to millimeters in length, showing a wave-like warp. At present, only Bow and Roughness can be detected by detection equipment, and there is a lack of structures and methods for testing Waviness. Waviness can reflect the macroscopic unevenness of the wafer surface, which is usually related to the grinding and polishing process of the wafer. The existing technology cannot detect Waviness, resulting in manufacturers being unable to further improve the process, improve the processing quality of wafers, and produce high-quality and high-performance products. Summary of the invention
[0003] The purpose of the present application is to provide a wafer warpage detection structure and detection method, which can accurately detect the degree of mid-frequency corrugation warpage of the wafer through the difference in capacitance values on both sides of the wafer to be tested.
[0004] The embodiment of the present application is implemented as follows:
[0005] In a first aspect, an embodiment of the present application provides a wafer warpage detection structure, comprising a first measuring plate assembly, a second measuring plate assembly and a capacitance measuring device; the first measuring plate assembly is used to connect to the first surface of a wafer to be measured, and the second measuring plate assembly is used to connect to the second surface of the wafer to be measured; the first surface of the wafer to be measured is divided into a first detection area, and the second surface of the wafer to be measured is divided into a second detection area, and the projections of the first detection area and the second detection area on the wafer to be measured coincide; the first measuring plate assembly and the second measuring plate assembly are both perpendicular to the wafer to be measured, the first measuring plate assembly is inserted in the first detection area, and the second measuring plate assembly is inserted in the second detection area; the capacitance measuring device is used to detect the capacitance values of the first measuring plate assembly and the second measuring plate assembly; wherein the first measuring plate assembly and the second measuring plate assembly are both non-parallel plate capacitors.
[0006] As an optional implementation, a first surface of the wafer to be tested is provided with a first bearing layer for forming a first detection area, and the first measurement board assembly is inserted in the first bearing layer.
[0007] As an optional implementation, a second surface of the wafer to be tested is provided with a second bearing layer for forming a second detection area, and the second measurement board assembly is inserted in the second bearing layer.
[0008] As an optional implementation, there are multiple first measurement board assemblies, which are arranged at intervals on the first surface of the wafer to be measured; there are multiple second measurement board assemblies, which are located on the second surface of the wafer to be measured, and the positions of the second measurement board assemblies and the first measurement board assemblies correspond one-to-one.
[0009] As an optional implementation, a distance is preset between the first measurement plate assembly and the second measurement plate assembly.
[0010] As an optional implementation, the first measurement plate assembly and / or the second measurement plate assembly includes at least two capacitance measurement plates arranged at intervals.
[0011] As an optional implementation, an electrical connection port connected to a capacitance measuring device is provided at the end of each capacitance measuring plate away from the wafer to be measured.
[0012] As an optional implementation, the spacing between adjacent capacitance measurement plates is 3-10 μm.
[0013] As an optional implementation, the capacitance measurement plate has a length of 3-10 μm, a width of 3-10 μm, and a thickness of 0.8-2 μm.
[0014] In a second aspect, an embodiment of the present application provides a wafer warpage detection method, which is applied to the above-mentioned wafer warpage detection structure, including:
[0015] electrically connecting a capacitance measuring device to the first measurement board assembly;
[0016] Detecting the capacitance of the first measuring plate assembly by a capacitance measuring device to obtain a first capacitance value;
[0017] electrically connecting a capacitance measuring device to the second measurement board assembly;
[0018] Detecting the capacitance of the second measuring plate assembly by a capacitance measuring device to obtain a second capacitance value;
[0019] The first capacitance value is compared with the second capacitance value. When the first capacitance value is greater than the second capacitance value, it indicates that the wafer to be tested is warped toward the surface where the first measurement board assembly is located; when the second capacitance value is greater than the first capacitance value, it indicates that the wafer to be tested is warped toward the surface where the second measurement board assembly is located.
[0020] The beneficial effects of the embodiments of the present application include:
[0021] In the first aspect, the wafer warpage detection structure provided by the embodiment of the present application includes a first measurement board assembly, a second measurement board assembly and a capacitance measurement device; the first measurement board assembly of the embodiment of the present application is used to connect with the first surface of the wafer to be tested, and the second measurement board assembly of the embodiment of the present application is used to connect with the second surface of the wafer to be tested. The embodiment of the present application divides a first detection area on the first surface of the wafer to be tested, and divides a second detection area on the second surface of the wafer to be tested, and the projections of the first detection area and the second detection area on the wafer to be tested coincide. The first measurement board assembly and the second measurement board assembly are both perpendicular to the wafer to be tested, the first measurement board assembly is inserted in the first detection area, and the second measurement board assembly is inserted in the second detection area; the capacitance measurement device is used to detect the capacitance values of the first measurement board assembly and the second measurement board assembly, and compare the first capacitance value with the second capacitance value. When the first capacitance value is greater than the second capacitance value, it indicates that the wafer to be tested is warped toward the surface where the first measurement board assembly is located; when the second capacitance value is greater than the first capacitance value, it indicates that the wafer to be tested is warped toward the surface where the second measurement board assembly is located. The embodiment of the present application can detect the degree of mid-frequency corrugation warping of the wafer through the difference in capacitance values on both sides of the wafer to be tested, which is beneficial for manufacturers to improve the process and improve the processing quality of the wafer.
[0022] In the second aspect, the wafer warpage detection method provided in the embodiment of the present application is applied to the above-mentioned wafer warpage detection structure, including: electrically connecting the capacitance measuring device to the first measuring board assembly; detecting the capacitance of the first measuring board assembly by the capacitance measuring device to obtain a first capacitance value. Electrically connecting the capacitance measuring device to the second measuring board assembly; detecting the capacitance of the second measuring board assembly by the capacitance measuring device to obtain a second capacitance value. Comparing the first capacitance value with the second capacitance value, when the first capacitance value is greater than the second capacitance value, it indicates that the wafer to be tested is warped toward the surface where the first measuring board assembly is located; when the second capacitance value is greater than the first capacitance value, it indicates that the wafer to be tested is warped toward the surface where the second measuring board assembly is located. The embodiment of the present application can detect the degree of warpage of the intermediate frequency corrugation of the wafer through the difference in capacitance values on both sides of the wafer to be tested, which is beneficial for manufacturers to improve the process and improve the processing quality of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0024] Figure 1 This is one of the structural schematic diagrams of the wafer warpage detection structure according to an embodiment of the present application;
[0025] Figure 2 This is the second structural schematic diagram of the wafer warpage detection structure according to an embodiment of the present application;
[0026] Figure 3 This is the third structural schematic diagram of the wafer warpage detection structure according to the embodiment of the present application.
[0027] Icons: 100 - first measurement board assembly; 101 - second measurement board assembly; 102 - capacitance measurement device; 103 - wafer to be measured; 104 - first bearing layer; 105 - second bearing layer; 106 - capacitance measurement board. DETAILED DESCRIPTION
[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.
[0029] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0030] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.
[0031] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0032] In semiconductor manufacturing and wafer processing, there are usually three types of wafer deformation: Bow, Roughness, and Waviness. Bow refers to the overall deformation of the wafer, the bending of the center of the wafer relative to the edge, and the overall bow-shaped bending. Roughness is the microscopic roughness of the wafer surface, usually referring to the surface unevenness of the wavelength from nanometers to micrometers. Waviness is the medium-frequency waviness of the wafer surface, usually referring to the surface unevenness with a longer wavelength, usually hundreds of microns to millimeters in length, showing a wave-like warp. At present, only Bow and Roughness can be detected by detection equipment, and there is a lack of structures and methods for testing Waviness. Waviness can reflect the macroscopic unevenness of the wafer surface, which is usually related to the grinding and polishing process of the wafer. The existing technology cannot detect Waviness, resulting in manufacturers being unable to further improve the process, improve the processing quality of wafers, and produce high-quality and high-performance products.
[0033] In order to solve the above technical problems, the embodiments of the present application provide a wafer warpage detection structure and a detection method.
[0034] Reference Figure 1 As shown, an embodiment of the present application provides a wafer warpage detection structure, including a first measurement plate assembly 100, a second measurement plate assembly 101 and a capacitance measuring device 102; the first measurement plate assembly 100 is used to connect to the first surface of the wafer 103 to be measured, and the second measurement plate assembly 101 is used to connect to the second surface of the wafer 103 to be measured; the first surface of the wafer 103 to be measured is divided into a first detection area, and the second surface of the wafer 103 to be measured is divided into a second detection area, and the projections of the first detection area and the second detection area on the wafer 103 to be measured coincide; the first measurement plate assembly 100 and the second measurement plate assembly 101 are both perpendicular to the wafer 103 to be measured, the first measurement plate assembly 100 is inserted in the first detection area, and the second measurement plate assembly 101 is inserted in the second detection area; the capacitance measuring device 102 is used to detect the capacitance values of the first measurement plate assembly 100 and the second measurement plate assembly 101; wherein the first measurement plate assembly 100 and the second measurement plate assembly 101 are both non-parallel plate capacitors.
[0035] The wafer warpage detection structure provided in the embodiment of the present application includes a first measurement plate assembly 100 , a second measurement plate assembly 101 and a capacitance measurement device 102 .
[0036] It should be noted that the capacitance measuring device 102 of the embodiment of the present application is connected to a signal detection structure. The signal detection structure may be a signal connection line, one end of which is connected to the capacitance measuring device 102, and the other end of which is in contact with the electrical connection ports on the first measurement board assembly 100 and the second measurement board assembly 101 to achieve conductive connection.
[0037] The first measurement board assembly 100 of the embodiment of the present application is used to connect with the first surface of the wafer 103 to be measured, and the second measurement board assembly 101 of the embodiment of the present application is used to connect with the second surface of the wafer 103 to be measured.
[0038] It should be noted that the first measurement board assembly 100 of the embodiment of the present application is provided with a first surface of the wafer 103 to be tested, and the second measurement board assembly 101 is provided with a second surface of the wafer 103 to be tested. The first surface and the second surface are parallel to each other and are corresponding two side planes of the wafer 103 to be tested.
[0039] Exemplarily, the first surface may be the upper surface of the wafer 103 to be tested, and the second measurement board assembly 101 may be the lower surface of the wafer 103 to be tested. At this time, the wafer 103 to be tested is placed horizontally.
[0040] If the wafer 103 to be tested needs to be placed vertically in a certain scenario, the first surface is the left surface of the wafer 103 to be tested, and the second surface is the right surface of the wafer 103 to be tested. Those skilled in the art can make settings as needed.
[0041] In the embodiment of the present application, a first detection area is divided on the first surface of the wafer 103 to be tested, and a second detection area is divided on the second surface of the wafer 103 to be tested. The projections of the first detection area and the second detection area on the wafer 103 to be tested overlap.
[0042] It should be noted that the first detection area divided on the first surface of the wafer 103 to be tested not only includes a certain plane space, but also includes a space in the depth direction. Similarly, the first detection area divided on the second surface of the wafer 103 to be tested not only includes a certain plane space, but also includes a space in the depth direction.
[0043] Therefore, the first detection area and the second detection area are not just defined as plane areas, and the first detection area and the second detection area are symmetrically arranged with respect to the wafer 103 to be tested.
[0044] Furthermore, the first measurement board assembly 100 and the second measurement board assembly 101 of the embodiment of the present application are both perpendicular to the wafer 103 to be measured, the first measurement board assembly 100 is inserted in the first detection area, and the second measurement board assembly 101 is inserted in the second detection area.
[0045] It should be noted that the first measurement board assembly 100 is perpendicular to the wafer 103 to be tested, and the second measurement board assembly 101 is perpendicular to the wafer 103 to be tested. The first measurement board assembly 100 and the second measurement board assembly 101 can be directly inserted into the wafer 103 to be tested, or can be on other hierarchical structures on the surface of the wafer 103 to be tested.
[0046] Therefore, the wafer to be tested 103 in the embodiment of the present application should be understood broadly, and it can be a wafer to be tested 103 to be processed, or a wafer with other hierarchical structures on its surface.
[0047] Reference Figure 2 As shown, illustratively, the first surface of the wafer 103 to be tested is provided with a first carrier layer 104 for forming a first detection area, and the first measurement board assembly 100 is inserted into the first carrier layer 104. The second measurement board assembly 101 can be directly inserted from the second side surface of the wafer 103 to be tested.
[0048] Reference Figure 2 As shown, illustratively, the second surface of the wafer 103 to be tested is provided with a second carrier layer 105 for forming a second detection area, and the second measurement board assembly 101 is inserted into the second carrier layer 105. The first measurement board assembly 100 can be directly inserted from the first side of the wafer 103 to be tested.
[0049] Exemplarily, a first surface of the wafer 103 to be tested is provided with a first carrier layer 104 for forming a first detection area, and the first measurement board assembly 100 is inserted in the first carrier layer 104. A second surface of the wafer 103 to be tested is provided with a second carrier layer 105 for forming a second detection area, and the second measurement board assembly 101 is inserted in the second carrier layer 105.
[0050] It should be noted that the first carrier layer 104 and the second carrier layer 105 may be a layered structure deposited on the surface of the wafer.
[0051] It should be noted that the first measurement board assembly 100 and the second measurement board assembly 101 may be inserted on the wafer 103 to be measured in a hierarchical structure that vertically penetrates the surface of the wafer 103 to be measured.
[0052] The first measurement board assembly 100 and the second measurement board assembly 101 can be disposed in the first detection area and the second detection area by etching and deposition processes.
[0053] Among them, the capacitance measuring device 102 is used to detect the capacitance values of the first measurement board assembly 100 and the second measurement board assembly 101, and compare the first capacitance value with the second capacitance value. When the first capacitance value is greater than the second capacitance value, it indicates that the wafer 103 to be measured is warped toward the surface where the first measurement board assembly 100 is located; when the second capacitance value is greater than the first capacitance value, it indicates that the wafer 103 to be measured is warped toward the surface where the second measurement board assembly 101 is located. The embodiment of the present application can detect the degree of warpage of the intermediate frequency waviness of the wafer through the difference in capacitance values on both sides of the wafer 103 to be measured, which is beneficial for manufacturers to improve the process and improve the processing quality of the wafer.
[0054] Reference Figure 2 As shown, as an optional embodiment, there are multiple first measurement board assemblies 100, and the multiple first measurement board assemblies 100 are arranged at intervals on the first surface of the wafer 103 to be measured; there are multiple second measurement board assemblies 101, and the second measurement board assemblies 101 are located on the second surface of the wafer 103 to be measured, and the positions of the second measurement board assemblies 101 and the first measurement board assemblies 100 correspond one to one.
[0055] It should be noted that, in the embodiment of the present application, multiple first detection areas can be set on the first surface, and each first detection area is correspondingly inserted with a first measurement board assembly 100. Similarly, multiple second detection areas can be set on the second surface, and each second detection area is correspondingly inserted with a second measurement board assembly 101.
[0056] The above configuration enables warpage detection to be performed at multiple locations of the wafer 103 to be tested, which is beneficial to improving the accuracy of the detection. The number of the first measurement board assembly 100 and the second measurement board assembly 101 can be selected by those skilled in the art as needed.
[0057] There is a preset distance between the first measurement board assembly 100 and the second measurement board assembly 101 .
[0058] Reference Figure 3 As shown, as an optional implementation, the first measurement board assembly 100 and / or the second measurement board assembly 101 includes at least two capacitance measurement boards 106 arranged at intervals.
[0059] Furthermore, the first measurement board assembly 100 and the second measurement board assembly 101 of the embodiment of the present application include at least two capacitance measurement boards 106 arranged at intervals.
[0060] Exemplarily, a single first measurement board assembly 100 includes four capacitance measurement boards 106 arranged at intervals, and a spacing between adjacent capacitance measurement boards 106 is 3-10 μm.
[0061] It should be noted that the capacitance measuring plate 106 is disposed on the wafer to be tested 103 through etching, deposition and other processes. At this time, the wafer to be tested 103 is perpendicular to the capacitance measuring plate 106. When the wafer to be tested 103 is subjected to various processes such as grinding and polishing later, warping occurs, and two adjacent capacitance measuring plates 106 change from parallel to non-parallel.
[0062] As an optional implementation, the capacitance measuring plate 106 has a length of 3-10 μm, a width of 3-10 μm, and a thickness of 0.8-2 μm. Each capacitance measuring plate 106 has an electrical connection port connected to the capacitance measuring device 102 at the end away from the wafer 103 to be tested.
[0063] The wafer warpage detection method provided in the embodiment of the present application is applied to the above-mentioned wafer warpage detection structure, including:
[0064] The capacitance measuring device 102 is electrically connected to the first measuring board assembly 100 ; the capacitance measuring device 102 detects the capacitance of the first measuring board assembly 100 to obtain a first capacitance value.
[0065] The capacitance measuring device 102 is electrically connected to the second measuring board assembly 101 ; the capacitance measuring device 102 detects the capacitance of the second measuring board assembly 101 to obtain a second capacitance value.
[0066] The first capacitance value is compared with the second capacitance value. When the first capacitance value is greater than the second capacitance value, it indicates that the wafer 103 to be tested is warped toward the surface where the first measurement board assembly 100 is located; when the second capacitance value is greater than the first capacitance value, it indicates that the wafer 103 to be tested is warped toward the surface where the second measurement board assembly 101 is located.
[0067] The embodiment of the present application can detect the degree of intermediate frequency waviness warping of the wafer by measuring the difference in capacitance values on both sides of the wafer 103 to be tested, which is beneficial for manufacturers to improve the process and improve the processing quality of the wafer.
[0068] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A wafer warpage detection structure, characterized in that: The invention comprises a first measuring board component (100), a second measuring board component (101) and a capacitance measuring device (102); the first measuring board component (100) is used to connect to a first surface of a wafer (103) to be tested, and the second measuring board component (101) is used to connect to a second surface of the wafer (103) to be tested; the first surface of the wafer (103) to be tested is divided into a first detection area, the second surface of the wafer (103) to be tested is divided into a second detection area, and the projections of the first detection area and the second detection area on the wafer (103) to be tested are The first measuring plate assembly (100) and the second measuring plate assembly (101) are both perpendicular to the wafer (103) to be measured, the first measuring plate assembly (100) is inserted in the first detection area, and the second measuring plate assembly (101) is inserted in the second detection area; the capacitance measuring device (102) is used to detect the capacitance values of the first measuring plate assembly (100) and the second measuring plate assembly (101); wherein the first measuring plate assembly (100) and the second measuring plate assembly (101) are both non-parallel plate capacitors.
2. The wafer warpage detection structure according to claim 1, characterized in that: A first bearing layer (104) for forming a first detection area is provided on the first surface of the wafer (103) to be tested, and the first measurement board assembly (100) is inserted in the first bearing layer (104).
3. The wafer warpage detection structure according to claim 1, characterized in that: A second bearing layer (105) for forming a second detection area is provided on the second surface of the wafer (103) to be tested, and the second measurement board assembly (101) is inserted into the second bearing layer (105).
4. The wafer warpage detection structure according to any one of claims 1 to 3, characterized in that: There are a plurality of first measurement board assemblies (100), and the plurality of first measurement board assemblies (100) are arranged at intervals on the first surface of the wafer (103) to be measured; there are a plurality of second measurement board assemblies (101), and the second measurement board assemblies (101) are located on the second surface of the wafer (103) to be measured, and the positions of the second measurement board assemblies (101) and the first measurement board assemblies (100) correspond one to one.
5. The wafer warpage detection structure according to any one of claims 1 to 3, characterized in that: A preset distance is provided between the first measurement plate assembly (100) and the second measurement plate assembly (101).
6. The wafer warpage detection structure according to any one of claims 1 to 3, characterized in that: The first measurement plate assembly (100) and / or the second measurement plate assembly (101) comprises at least two capacitance measurement plates (106) arranged at intervals.
7. The wafer warpage detection structure according to claim 6, characterized in that: An electrical connection port connected to a capacitance measuring device (102) is provided at the end of each capacitance measuring plate (106) away from the wafer (103) to be measured.
8. The wafer warpage detection structure according to claim 6, characterized in that: The spacing between adjacent capacitance measurement plates (106) is 3-10 μm.
9. The wafer warpage detection structure according to claim 6, characterized in that: The capacitance measurement plate (106) has a length of 3-10 μm, a width of 3-10 μm, and a thickness of 0.8-2 μm.
10. A wafer warpage detection method, applied to the wafer warpage detection structure according to any one of claims 1 to 9, characterized in that: include: electrically connecting a capacitance measuring device (102) to the first measurement board assembly (100); Detecting the capacitance of the first measurement board assembly (100) by means of a capacitance measuring device (102) to obtain a first capacitance value; electrically connecting a capacitance measuring device (102) to a second measurement board assembly (101); Detecting the capacitance of the second measurement board assembly (101) by means of a capacitance measuring device (102) to obtain a second capacitance value; The first capacitance value is compared with the second capacitance value. When the first capacitance value is greater than the second capacitance value, it indicates that the wafer to be measured (103) is warped toward the surface where the first measurement board assembly (100) is located; when the second capacitance value is greater than the first capacitance value, it indicates that the wafer to be measured (103) is warped toward the surface where the second measurement board assembly (101) is located.