Chip internal signal observation circuit and system

Abstract

The invention discloses a chip internal signal observation circuit and system, and the observation circuit comprises a signal selection module which is connected with a plurality of to-be-tested modules disposed in a target chip, and is used for selecting signals of to-be-observed modules in the plurality of to-be-tested modules, and synthesizing and outputting the signals; the sampling module is connected with the signal selection module and is used for sampling the signal synthesized and output by the signal selection module and writing the signal into an FIFO cache module; the FIFO cache module is used for caching the signals sampled by the sampling module; and the main equipment module is connected with the FIFO cache module, is connected with each memory through a bus, and is used for reading the sampled signals from the FIFO cache module and writing the sampled signals into the corresponding memories for signal observation.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a chip internal signal observation circuit and system. Background Art

[0002] Complex system-on-chip (SoC) chips contain numerous internal circuit modules. During chip testing and actual use, abnormalities that arise require debugging, necessitating monitoring of internal chip signals. However, direct monitoring of internal chip signals is not possible with a physical chip. A common approach involves monitoring internal chip signals by pulling them onto the chip pins. While the number of signals required to be monitored within a chip can be numerous, potentially exceeding several thousand, the limited number of chip pins far outstrips the number of internal signals required. Consequently, the number of signals that can be observed simultaneously is limited, reducing debugging efficiency.

[0003] Furthermore, the original functions of the chip pins selected for observation will not work. If the problem analysis happens to require the circuit modules corresponding to these chip pins to work, the debugging scope will be limited. Summary of the Invention

[0004] The purpose of the embodiments of the present application is to provide a chip internal signal observation circuit and system to solve the problem of limited debugging functions caused by using existing chip internal signal observation methods.

[0005] In order to solve the above technical problems, this specification is implemented as follows: In a first aspect, a chip internal signal observation circuit is provided, comprising: A signal selection module is connected to a plurality of modules to be tested provided inside the target chip, and is used to select the signal of the module to be observed from the plurality of modules to be tested and synthesize and output the signal; A sampling module, connected to the signal selection module, for sampling the signal synthesized and output by the signal selection module and writing it into the FIFO buffer module; The FIFO buffer module is used to buffer the signal sampled by the sampling module; The main device module is connected to the FIFO buffer module and connected to each memory through a bus, and is used to read the sampled signal from the FIFO buffer module and write it to the corresponding memory for signal observation.

[0006] In a second aspect, a chip internal signal observation system is provided, comprising: A signal selection module is connected to a plurality of modules to be tested provided inside the target chip, and is used to select the signal of the module to be observed from the plurality of modules to be tested and synthesize and output the signal; A sampling module, connected to the signal selection module, for sampling the signal synthesized and output by the signal selection module and writing it into the FIFO buffer module; The FIFO buffer module is used to buffer the signal sampled by the sampling module; A main device module is connected to the FIFO buffer module and is connected to each memory through a bus, and is used to read the sampled signal from the FIFO buffer module and write it to the corresponding memory; The waveform reconstruction module is connected to each memory and is used to read the sampled data from the memory after sampling is completed, arrange and reconstruct the waveform for signal observation.

[0007] In an embodiment of the present application, a chip internal signal observation circuit includes: a signal selection module, connected to a plurality of modules to be tested arranged inside a target chip, for selecting the signals of the modules to be observed among the plurality of modules to be tested and synthesizing and outputting them; a sampling module, connected to the signal selection module, for sampling the signals synthesized and outputted by the signal selection module and writing them into a FIFO cache module; the FIFO cache module, for caching the signals sampled by the sampling module; a main device module, connected to the FIFO cache module and connected to each memory through a bus, for reading the sampled signals from the FIFO cache module and writing them into corresponding memories for signal observation, thereby not being restricted by the number of chip pins, the number of internal signals to be observed can be set as needed, and the original chip pins can be free from being occupied, which has little impact on the original circuit, expands the debugging range, and improves the debugging efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 It is a schematic diagram of the overall architecture of the chip internal signal observation circuit of an embodiment of the present application.

[0009] Figure 2 It is a structural diagram of the signal selection module of an embodiment of the present application.

[0010] Figure 3 Schematic diagram of the structure of the multiplexer according to an embodiment of the present application.

[0011] Figure 4 This is a schematic diagram of the working principle of the main device module of an embodiment of the present application.

[0012] Figure 5 This is one of the workflow diagrams of the main device module in an embodiment of the present application.

[0013] Figure 6 This is the second workflow diagram of the main equipment module of the embodiment of the present application. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. The figure numbers in this application are only used to distinguish the various steps in the scheme and are not used to limit the execution order of the various steps. The specific execution order is subject to the description in the specification.

[0015] In order to solve the problems existing in the prior art, the embodiment of the present application provides a chip internal signal observation circuit, such as Figure 1 As shown, it includes a signal selection module 20, which is connected to a plurality of modules to be tested 10 arranged inside the target chip, and is used to select the signals of the modules to be observed in the plurality of modules to be tested 10 and synthesize and output them; a sampling module 30, which is connected to the signal selection module 20, and is used to sample the signals synthesized and output by the signal selection module 20 and write them into a FIFO cache module 40; the FIFO cache module 40 is used to cache the signals sampled by the sampling module 30; a main device module 50, which is connected to the FIFO cache module 40 and is connected to each memory 70 through a bus 60, and is used to read the sampled signals from the FIFO cache module 40 and write them into the corresponding memory 70 for signal observation.

[0016] The module under test 10 is a circuit module within a chip. When anomalies occur within the module under test 10, debugging is required. Monitoring the signals within the module under test 10, in other words, monitoring the internal signals of the chip, is crucial. The number of module signals that require monitoring within a chip can be numerous, potentially reaching thousands. Signal selection module 20 can be used to select the desired module signals from among the multiple modules under test 10 within the connected target chip.

[0017] There is no limit to the number of signals of the modules to be tested in the embodiment of the present application. The number of signals used for observation at the same time can be set according to the observation needs, that is, the signal width of the synthesized output of the signals to be observed at the same time. In addition, during observation, it may be necessary to observe only the signal of a single module to be tested, or it may be necessary to observe the signals of multiple modules to be tested at the same time. The signal selection module 20 can flexibly combine the signals of different modules to be tested 10 as needed. Because the signals between different modules to be tested 10 are related, sometimes debugging requires simultaneous observation of the signal combination of the modules to be tested at the front and back stages. For example, if a total of 32 bits of signal are observed at the same time, the signal selection module 20 can select 8 bits, 8 bits, and 16 bits from three different modules to be tested 10 in a one-to-one correspondence, or it can select 8 bits, 4 bits, 20 bits, etc. from three different modules to be tested 10 in a one-to-one correspondence.

[0018] Assume that the target module under test 10 is allocated to be able to observe 4-bit signals. The 4-bit signals can be selected internally by the target module under test 10. For example, if there are a total of 128-bit signals to be observed in the target module under test 10, the target module under test 10 can provide different combinations of 4-bit signals.

[0019] Signals from multiple modules under test (DUT) 10 within the target chip are fed into a signal selection module 20, which selects a group of signals to be observed simultaneously and synthesizes them for output. Each DUT 10 may contain a single or multiple DUT signals. Some signals may be single-bit, while others may be multi-bit.

[0020] In this way, the number of signals observed inside the target chip is not limited by the number of pins or the application environment.

[0021] like Figure 1 As shown, the signal output by the module to be tested includes 32 bits, 24 bits or 64 bits, etc. After being selected and combined by the signal selection module 20, a 32-bit composite signal is output.

[0022] Combine Figure 2 and Figure 3 The signal selection module 20 includes multiple multiplexers 22 and a synthesis unit 24. The input end of each multiplexer 22 is connected to the multiple modules to be tested 10 and is used to receive all signals of the multiple modules to be tested 10; the output end of each multiplexer 22 is used to output the signal of the selected module to be observed; the synthesis unit 24 is connected to the output end of each multiplexer 22 and is used to synthesize the signals output by the output end of each multiplexer 22 and output them to the sampling module 30.

[0023] For example, if the total number of signals to be observed for all modules under test 10 within the target chip is 512 bits, and all signals are listed in groups of 4 bits, there are a total of 128 groups. If the signal width of the synthesized output of the signals used for simultaneous observation is set to 32 bits, eight "128 groups to 1 group" multiplexers 22 can be used, with each multiplexer 22 selecting a 4-bit signal from the total 512-bit signal. The 4-bit signals selected by the eight multiplexers 22 are then provided to the synthesis unit 24, which synthesizes them to obtain a 32-bit signal for output.

[0024] The signal synthesized and output by the signal selection module 20 is a signal that can be observed simultaneously. The width or number of the synthesized output signal is related to the width of the bus. For example, if the width of the bus is usually 32 bits, 64 bits or 128 bits, then 32 bits, 64 bits or 128 bits of signal can be observed simultaneously.

[0025] The sampling module 30 is used to sample the synthesized signal output by the signal selection module 20 and write the sampled signal into the subsequent FIFO buffer module 40. Because the sampled signal is usually read by the waveform reconstruction module for waveform reconstruction, if sampling is continuous, the amount of sampled signal data may become too large, causing the memory 70 to be full or overwritten. Secondly, too many reconstructed waveforms may prevent the waveform for the target time period from being found.

[0026] Therefore, the sampling module 30 starts sampling after a preset trigger condition is met based on a preset configuration, and stops sampling after the storage space allocated by each memory is full of sampled data. For example, the sampling module can stop sampling by enabling a switch.

[0027] In this way, a trigger condition can be set for the synthetic signal output by the signal selection module 20, and the sampling module 30 starts sampling after the condition is triggered.

[0028] Furthermore, the higher the sampling clock frequency of sampling module 30, the closer the waveform reconstructed from the sampled signal is to reality. Therefore, it is best to use the highest sampling clock frequency possible. However, the higher the sampling clock frequency, the greater the amount of sampled signal data. This increases the bandwidth required by master module 50 to read the sampled signal from FIFO buffer module 40 and write it to memory 70. If writing to memory is not possible in time, the subsequent FIFO buffer module 40 may overflow, resulting in a reconstructed waveform that is not realistic.

[0029] Therefore, in one embodiment, the sampling bandwidth of the sampling module 30 is less than or equal to the sum of the write bandwidths of the memories 70. That is, the sum of the write bandwidths of all memories 70 used to write sampled signals is required to be greater than or equal to the sampling bandwidth of the sampling module 30. The sampling bandwidth is the product of the sampling clock frequency of the sampling module and the sampled signal width. The write bandwidth is the product of the access clock frequency of the memory and the write data width. The sampled signal width is the signal width of the synthesized output, that is, the width of the synthesized signal output by the signal selection module 20, for example Figure 2 In the embodiment, it is 32 bits.

[0030] Optionally, each memory is a different type of memory arranged inside the target chip, and the different types of memories have different storage space sizes, access clock frequencies, and write data widths.

[0031] For example, the memory 70 includes a random access memory with low-latency access characteristics in the CPU system of the target chip, a tightly coupled memory, an on-chip static random access memory connected to the bus, an off-chip double-rate synchronous dynamic random access memory, or a cache of each data processing module inside the target chip.

[0032] Combine Figure 1 The memory 70 may include a low-latency random access memory 72 (LLRAM) in the CPU system 80, a tightly coupled memory 74 (TCM), an on-chip static random access memory 76 (SRAM) on the high-speed bus 60, an off-chip double data rate synchronous dynamic random access memory 78 (DDR) controlled by a DDR controller 90, and a buffer that may exist in each internal data processing module 100.

[0033] By reusing existing on-chip memories, we avoid adding additional memory to store sampled signals, which would increase chip costs. Furthermore, by reusing existing on-chip memories, we can store a large number of sampled signals, achieving high signal depth observation and increasing the time span of observed signals, facilitating on-chip debugging and analysis. Furthermore, in chips with multiple memories, the sampling module's sampling clock frequency can be much higher, facilitating waveform reconstruction.

[0034] Different types of memories have different storage space sizes, access clock frequencies, and write data widths. The write bandwidth of each memory is the product of the access clock frequency of the corresponding memory and the write data width. The sampling bandwidth of the sampling module 30 is the product of the sampling clock frequency of the sampling module 30 and the sampled signal width.

[0035] If the signal width sampled by the sampling module 30 is consistent with the data write width of each memory, it is sufficient to ensure that the sampling clock frequency of the sampling module 30 matches the access clock frequency of each memory.

[0036] The sampling clock frequency of sampling module 30 needs to be determined based on the number of memories available in the actual target chip for storing sampled signals, as well as the storage space and access clock frequency of each memory. For example, if there are four memories available for storing sampled signals, each with the same storage space, a write data width equal to the sampled signal width, and the access clock frequency of all four memories is the same, at 200 MHz, and the four memories can be considered to be written in parallel, then the sampling clock frequency of sampling module 30 can be four times 200 MHz, that is, 800 MHz. However, the actual sampling clock frequency may be less than 800 MHz due to some bandwidth loss in the path from sampling module 30 to memory 70, and this needs to be calculated based on the actual implementation.

[0037] The sampled signal output by the sampling module 30 is first written into the FIFO buffer module 40. The FIFO buffer module 40 is only an intermediate buffer with a relatively small storage capacity, so the impact on the chip area is relatively small and the increased chip cost can be ignored.

[0038] The master device module 50 is used to read the sampled signal from the FIFO buffer module 40 and write it into the corresponding connected memory 70 through the bus 60 .

[0039] Combine Figure 4 Optionally, the master device module 50 includes a read control unit 52, a write address control unit 54, and a write control unit 56. The read control unit 52 initiates a read operation to read the sampled signal from the FIFO cache module 40 when the number of sampled signals cached in the FIFO cache module 40 is higher than a preset number threshold; the write address control unit 54 responds to the read operation and sends the write address of the corresponding memory in each memory 70 to the write control unit 56 based on a preset configuration; the write control unit 56 responds to the read operation and reads the sampled signal of the sampled signal width from the FIFO cache module 40 and writes it to the write address through the bus 60.

[0040] Specifically, the master module 50 is configured to access various memories 70 inside the target chip via the bus 60. The function of the master module 50 is to write the sampled signals into the various memories 70 of the target chip.

[0041] In the embodiment of the present application, the master device module 50 uses a read control unit 52 to control the read FIFO buffer module 40. As long as the FIFO buffer module 40 is not empty or the valid data depth in the FIFO buffer module 40, that is, the number of sampled signals buffered in the FIFO buffer module 40 exceeds a preset number threshold, the read control unit 52 initiates a read operation, that is, sends a read enable signal to the FIFO buffer module 40. The read enable is initiated first, and at the same time, the write address control unit 54 is notified to prepare the write address. The goal is to achieve that the write address control unit 54 writes the address and the write control unit 56 writes the data simultaneously.

[0042] In response to the read operation, the write address control unit 54 sends the write address of the corresponding memory in the multiple memories to the write control unit 56 based on the preset configuration. The write address here can be the address of any memory or the addresses of multiple memories. In response to the read operation, the write control unit 56 reads the sampled signal of the sampled signal width from the FIFO buffer module 40 and writes it to the write address provided by the write address control unit 54 via the bus 60, thereby sequentially writing the sampled signal to the corresponding memory.

[0043] As mentioned above, the higher the sampling clock frequency of the sampling module 30, the better. However, the write bandwidths of different memories 70 are not the same. If the sampling bandwidth of the sampling module 30 exceeds the sum of the write bandwidths of each memory 70, data overflow will occur in the FIFO cache module.

[0044] In addition, the write bandwidth of the main device module 50 is usually set to be greater than the write bandwidth of each memory 70 (single memory). When the write bandwidth of the main device module 50 exceeds the write bandwidth of the memory 70 (single memory), the bus 60 will automatically insert a waiting process, thereby lowering the write bandwidth of the main device module 50. As a result, the sampled signals cached in the FIFO cache module 40 will not be read out in time. As time accumulates, the FIFO cache module 40 will overflow.

[0045] In one embodiment, the preset configuration includes: configuring the starting address of each memory for storing sampled signals; configuring the first storage space within each memory's storage space for storing sampled signals; and configuring the number of advance transmission transactions for each memory and the write burst length for each memory, configuring the alternate writing of sampled signals to each memory, and the number of sampled signals written to each alternate memory each time. The above configuration can be implemented by configuring registers. The write address control unit 54 can flexibly allocate the storage space and size of each memory for storing sampled signals, as well as the starting address of the storage space, by configuring the registers. The first sampled signal will be written starting from the starting address and sequentially downwards.

[0046] Furthermore, the address control unit 54 can be configured to write the write addresses of multiple memories in turn, and the write control unit 56 can be controlled to write the sampled signals into multiple memories in turn. Figure 4 The sampled signals can be configured to be written into the three memories, storage A, storage B, and storage C, in turn.

[0047] The write address control unit 54 can configure registers to set the outstanding number of transactions for each memory and the write burst length, thereby controlling the number of sampled signals written to each memory each time. In the Advanced Extensible Interface (AXI) protocol, "outstanding" refers to the AXI outbound transmission feature, indicating that a transaction has not yet completed and that other transactions can be initiated first.

[0048] The number of sampled signals continuously written to each memory each time is the product of the outstanding number of transmission transactions of each memory (outstanding num) and the write burst length. For example, the number of sampled signals written to each of the three memory configurations described above is: i data for writing to memory A, j data for writing to memory B, and k data for writing to memory C. That is, the number of sampled signals written to each memory each time is i, j, and k, respectively.

[0049] Figure 4 The dotted box is a schematic state machine. The write address control unit 54 writes the sampled signals cached in the FIFO cache module 40 to multiple memories in turn according to the configuration, and by matching the outstanding num and write burst length of each memory, the bandwidth of each memory is fully utilized in a time-sharing manner, thereby solving the contradiction of inconsistent bandwidth between the main device module 50 and each memory.

[0050] Assuming that the write rate of the master device module 50 is 900Mb / s, and the write rates of the three memories, namely storage A, storage B and storage C, are 200Mb / s, 300Mb / s and 400Mb / s respectively, then by controlling i:j:k = 2:3:4, the master device module 50 writes to the three memories in turn, and the write rates are exactly matched.

[0051] Specifically, suppose 20 bytes are written to storage A, 30 bytes are written to storage B, and 40 bytes are written to storage C, and the above cycle is repeated. From the perspective of master module 50, 90 bytes are written at a rate of 900 Mb / s. For storage A, only 20 bytes are written, and the average rate is 200 Mb / s, which exactly matches the rate of storage A. Correspondingly, for storage B, only 30 bytes are written, and the average rate is 300 Mb / s, which exactly matches the rate of storage B. Storage C is similar and will not be described in detail here.

[0052] This can avoid the problem of data overflow in the FIFO buffer module 40 caused by reducing the write bandwidth of the master device module 50 when the write bandwidth of the master device module 50 exceeds the write bandwidth of each memory.

[0053] Optionally, the read control unit 52 counts up by 1 each time the read operation is initiated; the write address control unit 54, when determining that the number of sampled signals read by the read control unit 52 from the FIFO cache module 40 satisfies the requirement for writing into the largest first storage space in each memory 70, determines the target memory in turn based on the current count and sends the write address of the first storage space of the target memory to the write control unit 56; the write control unit 56 writes the sampled signal of the sampled signal width read from the FIFO cache module 40 into the write address of the first storage space of the target memory.

[0054] The number of sampled signals satisfies the requirement to be written into the largest first storage space in each memory, that is, the maximum number of sampled signals that can be written per write in each memory configuration is reached. For example, if the number of sampled signals per write in each memory configuration for memory A, memory B, and memory C is i, j, and k, respectively, then the maximum number of sampled signals among i, j, and k is reached.

[0055] Alternatively, after knowing the target memory of the current rotation, the write address control unit 54 determines whether the number of sampled signals read by the read control unit 52 from the FIFO buffer module 40 satisfies the first storage space of each write of the sampled signals configured for the memory of the rotation. For example, if the current write is to memory A, when the number of sampled signals reaches i, the write address of the first storage space of memory A is sent to the write control unit 56.

[0056] Furthermore, the write address control unit calculates the total amount of the rotated sampling signals of each memory based on the number of sampled signals written to each configured rotated memory each time; calculates the remainder result of the current count to the total amount of the rotated sampling signals; and determines the target memory in rotation based on the remainder result, the total amount of the rotated sampling signals and the preset rotated sampling signal interval of each memory, wherein the preset rotated sampling signal interval is configured according to the number of sampled signals written to each rotated memory each time and the order of writing.

[0057] The total number of rotated sampling signals is the sum of the number of sampled signals written continuously to the rotating memories each time. For example, if there are three memories, and the number of sampled signals written to memory A, memory B, and memory C is I, J, and K respectively, then the total number of rotated sampling signals is X = I + J + K. The order of writing to the three memories is memory A, memory B, and memory C. The rotated sampling signal interval of memory A can be configured as [0, I), the rotated sampling signal interval of memory B as [I, I+J), and the rotated sampling signal interval of memory C as [I+J, I+J+K), that is, [I+J, X).

[0058] Assume that Y represents the remainder of the current count counter to the total amount X of the alternately sampled signal. Assume that I = 10, J = 20, and K = 30, then X = 10 + 20 + 30 = 60.

[0059] When counter < 60: Y = counter When 60<=counter<120: Y = Counter – 60 When 120<=counter<180: Y = Counter – 120.

[0060] Similarly, the value of Y can be calculated each time it is written.

[0061] Compare the Y value with the preset rotation sampling signal number interval of each memory to determine the rotation sampling signal interval where the Y value is located, and determine the memory corresponding to the rotation sampling signal interval where the Y value is located as the memory for the current rotationally written sampled signal.

[0062] Next, combine Figure 5 and Figure 6 , the workflow of the main equipment module 50 is described.

[0063] like Figure 5 As shown, the following steps are included: Step 102, the read control unit triggers sampling enable; Step 104 , determining whether the data depth of the FIFO buffer module is greater than a preset threshold value, if yes (Y), proceeding to step 106 , if no (N), returning to step 104 ; Step 106: The read control unit reads the FIFO buffer module, reading one sampled signal at a time; Step 108: The read control unit adds 1 to the current count Counter; In step 110, the read control unit determines whether the write address control unit is ready. If so, the process returns to step 104; otherwise, the process returns to step 110. "Not ready" here means that the previous data from the write control unit has not yet been written to the current memory; the data is still stored in the write control unit's cache. In this case, data cannot be read from the FIFO buffer module because there is no storage space for the read data. This allows for mitigation of misconfiguration or abnormalities, preventing circuit operation errors.

[0064] like Figure 6 As shown, the following steps are included: Step 201, starting with the current count Counter not equal to 0; Step 202 , determining whether the accumulated unsent data read by the write address control unit from the FIFO buffer module meets the number of data to be written into one memory; if so, proceeding to step 204 , otherwise returning to step 202 ; Step 204: Calculate the total number of rotated sampled signals from each memory and the remainder of the current count to the total number of rotated sampled signals. For example, in the case of the three memories A, B, and C being written in turn, the number of sampled signals written each time is I, J, and K, respectively. The total number of rotated sampled signals is calculated as X = I + J + K, and the remainder is calculated as Y = Counter % X. Step 206, determining whether the remainder result Y falls within the preset alternating sampling signal interval of memory A; Step 208, determining whether the remainder result Y falls within the preset alternating sampling signal interval of memory B; Step 210, determining whether the remainder result Y falls within the preset alternating sampling signal interval of the memory C; Step 212, writing the sampled signal into memory A; Step 214, writing the sampled signal into memory B; Step 216, writing the sampled signal into the memory C; Step 218, determine whether any memory is currently full, if so, end writing to the memory, otherwise return to step 202 and continue writing to the memory.

[0065] As described above, in the embodiments of the present application, a portion of the existing memory within the chip can be used to store the sampled signals. This means that some of the memory still has space for other purposes, such as SRAM, to which the chip's CPU reads and writes data. If the CPU writes to the SRAM frequently, causing the master module's operations of writing sampled signals to the SRAM to frequently conflict with the CPU's operations of reading and writing data to the SRAM, this will reduce the master module's write bandwidth and may also cause a buildup of cached data in the FIFO storage module.

[0066] Therefore, optionally, the write address control unit 54 determines the write bandwidth of each memory when it is working normally before configuring the first storage space in the storage space of each memory for storing the sampled signal; and uses the memory with a write bandwidth less than a preset write bandwidth threshold as the memory for storing the sampled signal.

[0067] As mentioned above, the master module's write bandwidth should preferably be equal to or greater than the sampling module's sampling bandwidth. During actual debugging, if a memory's normal operating access bandwidth is relatively high, it may not be suitable for storing sampled signals. Alternatively, a memory with a lower actual access bandwidth may be selected. However, the write bandwidth of the selected memory with a lower actual access bandwidth should still be equal to or greater than the sampling module's sampling bandwidth.

[0068] In addition, after the write address control unit 54 roughly locates a memory that may have a relatively large working access bandwidth, it can also reduce the irrelevant or non-critical access volume of the memory by shutting down some functions of the memory, so that the memory can be selected for use as a storage sample signal.

[0069] When the storage space for sampled signals in any memory is full, the waveform reconstruction module reads the sampled signals from the memory, arranges them according to the same sequence rules, and reconstructs the waveform. This allows for simultaneous observation of a large number of internal chip signals and debugging.

[0070] In an embodiment of the present application, a chip internal signal observation circuit includes: a signal selection module, connected to a plurality of modules to be tested arranged inside a target chip, for selecting the signals of the modules to be observed among the plurality of modules to be tested and synthesizing and outputting them; a sampling module, connected to the signal selection module, for sampling the signals synthesized and outputted by the signal selection module and writing them into a FIFO cache module; the FIFO cache module, for caching the signals sampled by the sampling module; a main device module, connected to the FIFO cache module and connected to each memory through a bus, for reading the sampled signals from the FIFO cache module and writing them into corresponding memories for signal observation, thereby not being restricted by the number of chip pins, the number of internal signals to be observed can be set as needed, and the original chip pins can be free from being occupied, which has little impact on the original circuit, expands the debugging range, and improves the debugging efficiency.

[0071] Optionally, an embodiment of the present application further provides a chip internal signal observation system, comprising: A signal selection module is connected to a plurality of modules to be tested provided inside the target chip, and is used to select the signal of the module to be observed from the plurality of modules to be tested and synthesize and output the signal; A sampling module, connected to the signal selection module, for sampling the signal synthesized and output by the signal selection module and writing it into the FIFO buffer module; The FIFO buffer module is used to buffer the signal sampled by the sampling module; A main device module is connected to the FIFO buffer module and is connected to each memory through a bus, and is used to read the sampled signal from the FIFO buffer module and write it to the corresponding memory; The waveform reconstruction module is connected to each memory and is used to read the sampled data from the memory after sampling is completed, arrange and reconstruct the waveform for signal observation.

[0072] The waveform reconstruction module can be a computer to which the chip is connected through an interface, such as an Ethernet network port, a high-speed serial computer expansion bus (PCIe), a universal serial bus (USB), a universal asynchronous receiver and transmitter (UART), a joint test group (JTAG) interface, a bidirectional two-wire synchronous serial bus (I2C) or a serial peripheral interface (SPI).

[0073] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0074] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus the necessary general hardware platform. Of course, they can also be implemented by hardware, but in many cases the former is a more preferred embodiment. Based on this understanding, the technical solution of this application, or the part that contributes to the existing technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for enabling a terminal (which can be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in each embodiment of this application.

[0075] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A chip internal signal observation circuit, characterized in that: include: A signal selection module, connected to a plurality of modules to be tested arranged inside the target chip, for selecting signals of modules to be observed from the plurality of modules to be tested and synthesizing and outputting them; A sampling module, connected to the signal selection module, for sampling the signal synthesized and output by the signal selection module and writing it into the FIFO buffer module; The FIFO buffer module is used to buffer the signal sampled by the sampling module; The main device module is connected to the FIFO buffer module and to each memory through a bus, and is used to read the sampled signal from the FIFO buffer module and write it to the corresponding memory for signal observation.

2. The circuit according to claim 1, characterized in that The sampling bandwidth of the sampling module is less than or equal to the sum of the write bandwidths of the memories, the sampling bandwidth is the product of the sampling clock frequency of the sampling module and the sampled signal width, the write bandwidth is the product of the access clock frequency of the memory and the write data width, and the sampled signal width is the signal width of the synthesized output; Each memory is a different type of memory arranged inside the target chip, and the storage space size, access clock frequency, and write data width of the different types of memories are different.

3. The circuit according to claim 1, characterized in that The signal selection module includes a plurality of multiplexers and a synthesis unit, The input end of each multiplexer is connected to the plurality of modules to be tested and is used to receive all signals of the plurality of modules to be tested; The output end of each multiplexer is used to output the signal of the selected module to be observed; The synthesis unit is connected to the output ends of the multiplexers, and is used to synthesize the signals output from the output ends of the multiplexers and output them to the sampling module.

4. The circuit according to claim 2, characterized in that The memory includes a random access memory with low latency access characteristics in the CPU system of the target chip, a tightly coupled memory, an on-chip static random access memory connected to the bus, an off-chip double-rate synchronous dynamic random access memory, or a cache of each data processing module inside the target chip.

5. The circuit according to claim 2 or 4, characterized in that: The master device module includes a read control unit, a write address control unit and a write control unit. The read control unit initiates a read operation of reading the sampled signals from the FIFO buffer module when the number of sampled signals buffered in the FIFO buffer module is higher than a preset number threshold; The write address control unit, in response to the read operation, sends a write address of a corresponding memory in each memory to the write control unit based on a preset configuration; The write control unit, in response to the read operation, reads the sampled signal of the sampled signal width from the FIFO buffer module and writes the sampled signal into the write address through the bus.

6. The circuit according to claim 5, characterized in that The preset configuration includes: Configuring each memory to store the starting address of the sampled signal; configuring a first storage space in the storage space of each memory for storing the sampled signal; By configuring the number of unfinished and pending transactions in each memory to advance the number of transmission transactions and the write burst length of each memory, the sampled signals written to each memory in turn and the number of sampled signals written to the memory in turn each time are configured.

7. The circuit according to claim 6, characterized in that The read control unit counts up by 1 each time after initiating the read operation; The write address control unit determines the target memory in turn based on the current count and sends the write address of the first storage space of the target memory to the write control unit when it is determined that the number of sampled signals read by the read control unit from the FIFO buffer module satisfies the requirement of writing into the largest first storage space in each memory; The write control unit writes the sampled signal of the sampled signal width read from the FIFO buffer module into a write address of the first storage space of the target memory.

8. The circuit according to claim 7, characterized in that The write address control unit, Based on the number of sampled signals written into each configured memory in turn, the total amount of the sampled signals of each memory in turn is calculated; Calculate the remainder of the current count to the total amount of the alternately sampled signal; Based on the remainder result, the total amount of the rotating sampling signal and the preset rotating sampling signal interval of each memory, the rotating target memory is determined, and the preset rotating sampling signal interval is configured according to the number of sampled signals written each time to each rotating memory and the order of writing.

9. The circuit according to claim 7, characterized in that The write address control unit, Before configuring a first storage space in the storage space of each memory for storing the sampled signal, determining a write bandwidth of each memory when the memory is operating normally; A memory whose write bandwidth is less than a preset write bandwidth threshold is used as a memory for storing the sampled signal.

10. A chip internal signal observation system, characterized in that: include: A signal selection module, connected to a plurality of modules to be tested arranged inside the target chip, for selecting signals of modules to be observed from the plurality of modules to be tested and synthesizing and outputting them; A sampling module, connected to the signal selection module, for sampling the signal synthesized and output by the signal selection module and writing it into the FIFO buffer module; The FIFO buffer module is used to buffer the signal sampled by the sampling module; A main device module, connected to the FIFO buffer module and connected to each memory through a bus, and used for reading the sampled signal from the FIFO buffer module and writing it to the corresponding memory; The waveform reconstruction module is connected to each memory and is used to read the sampled data from the memory after sampling is completed to arrange and reconstruct the waveform for signal observation.

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