Static reference model design method and device of programmable delay block and electronic equipment

Abstract

The invention relates to a static reference model design method and device of a programmable delay block and electronic equipment. The method comprises the following steps: configuring a delay value of each channel through a register; sequencing the delay values of all the channels according to the sizes of the delay values and storing the delay values in a queue to obtain a sequenced channel data queue; when a data packet of a return value of a current channel x is received, traversing whether a channel with the same delay value as the channel x exists in the sorted channel data queue or not; if yes, the channel x directly reports an error; otherwise, judging whether the channel x needs to report an error or not by comparing the channel with the delay value smaller than the delay value of the channel x. According to the method, the channel is judged by comparing the delay values, and time sequence information does not need to be introduced, so that the design complexity is greatly reduced, the coupling between a time sequence and hardware design is reduced, and the quality risk of verification is reduced; the number of channels can be configured, and only the number of channels needs to be set during data preprocessing, so that reusability is provided.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a static reference model design method, device and electronic device for a programmable delay block. Background Art

[0002] The programmable delay block in the chip is a module that generates delayed output by configuring the delay value. It can integrate multiple channels. Each channel can configure the delay value through the register. When the internal counter counts the delay value, the output is generated. At the same time, after the output is generated, it needs to wait for the response of the return signal. If any other channel x generates a delayed output during the waiting period, channel x will report an error.

[0003] In the verification of this module, it is necessary to determine the output status of the remaining channels during the time between the delayed output of each channel and its return signal. In the hardware design of the chip, the status of the remaining channels during the time between the delayed output and the return signal can be monitored in real time based on the clock, so as to directly determine whether to report an error. The hardware design is based on the time dimension to design this module. However, in the design of the reference model in the chip verification environment (the reference model here refers to the reference model designed by the verification personnel in the chip verification using the common design method of the reference model), if the timing is introduced and real-time calculation is also performed, it will bring several disadvantages. First, the introduction of the clock increases the timing design and the design complexity of the reference model; second, when making a timing reference model, every time the hardware design has a timing modification or adjustment, the reference model will also be modified, making it not maintainable and reusable. Most importantly, the hardware design is based on real-time design. If the reference model is also based on real-time design, then there may be the same vulnerabilities in the two, which greatly increases the verification quality risk. Summary of the invention

[0004] Based on this, it is necessary to provide a static reference model design method, device and electronic device for a programmable delay block to address the above technical problems.

[0005] A static reference model design method for a programmable delay block, the method comprising: The delay value of each channel is configured through registers.

[0006] The delay values ​​of all channels are sorted according to the size of the delay values ​​and stored in a queue to obtain a sorted channel data queue.

[0007] When a data packet of the return value of the current channel x is received, the sorted channel data queue is traversed to see if there is a channel with the same delay value as channel x.

[0008] If yes, channel x will report an error directly.

[0009] Otherwise, it is determined whether channel x is to report an error by comparing the channels in the sorted channel data queue that have a smaller delay value than channel x.

[0010] In one embodiment, the delay values ​​of all channels are sorted according to the size of the delay values ​​and stored in a queue to obtain a sorted channel data queue, including: Starting from the first channel, determine whether the first channel is a bypass channel. If it is, the channel number and 0 form the channel data; otherwise, the channel number and the corresponding channel delay value form the channel data and push it into the channel data queue; continue to process the next channel until all channels are traversed to obtain an unsorted channel data queue.

[0011] The delay values ​​in each channel data in the unsorted channel data queue are sorted in ascending order to obtain a sorted channel data queue.

[0012] In one embodiment, determining whether channel x is to report an error by comparing channels in the sorted channel data queue with channels having a smaller delay value than channel x comprises: Compare whether the delay value of channel x is less than the sum of the delay value and the return value of each channel in front of channel x in the sorted channel data queue.

[0013] If yes, channel x reports an error; otherwise, channel x is correct.

[0014] In one embodiment, the method further comprises: When the data packet of the return value is obtained, the return value is updated; the default return value of the channel is hffffffff.

[0015] If no data packet with a return value is obtained when preparing for judgment, and the return value is hffffffff, the judgment will be reported as an error.

[0016] A static reference model design device for a programmable delay block, the device comprising: The data preprocessing module is used to configure the delay value of each channel through a register; the delay values ​​of all channels are sorted according to the size of the delay values ​​and stored in a queue to obtain a sorted channel data queue.

[0017] The data judgment module is used to traverse the sorted channel data queue to see if there is a channel with the same delay value as channel x when receiving the data packet of the return value of the current channel x; if so, channel x directly reports an error; otherwise, by comparing the channels with smaller delay values ​​than channel x in the sorted channel data queue, it is judged whether channel x should report an error.

[0018] In one of the embodiments, the data preprocessing module is also used to start from the first channel and determine whether the first channel is a bypass channel. If so, the channel number and 0 are used to form channel data; otherwise, the channel number and the corresponding channel delay value are used to form channel data and are pushed into the channel data queue; the next channel is processed until all channels are traversed to obtain an unsorted channel data queue; and the delay values ​​in each channel data in the unsorted channel data queue are sorted in ascending order to obtain a sorted channel data queue.

[0019] In one of the embodiments, the data judgment module is further used to compare whether the delay value of channel x is less than the sum of the delay value and return value of each channel in front of channel x in the sorted channel data queue; if so, channel x reports an error; otherwise, channel x is correct.

[0020] In one of the embodiments, the device also includes: an error reporting module for not receiving a return value data packet, which is used to update the return value when a data packet with a return value is obtained; the return value of the channel defaults to hffffffff; if no return value data packet is obtained when preparing for judgment, and the return value is hffffffff, an error is reported.

[0021] A computer device comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above method when executing the computer program.

[0022] The static reference model design method, device and electronic device of the programmable delay block mentioned above, the method includes: configuring the delay value of each channel through a register; sorting the delay values ​​of all channels according to the size of the delay value and storing them in a queue to obtain a sorted channel data queue; when receiving a data packet of the return value of the current channel x, traversing the sorted channel data queue to see if there is a channel with the same delay value as channel x; if so, channel x directly reports an error; otherwise, by comparing channels with smaller delay values ​​than channel x, it is determined whether channel x should report an error. This method realizes the judgment of the channel by comparing the delay value, and does not need to introduce timing information, thereby greatly reducing the design complexity, reducing the coupling between timing and hardware design, and reducing the quality risk of verification; the number of channels is configurable, and only the number of channels needs to be set during data preprocessing, thereby providing reusability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A schematic flow chart of a static reference model design method for a programmable delay block in one embodiment; Figure 2 A schematic diagram of a data preprocessing process in another embodiment; Figure 3A schematic diagram of a data judgment flow chart in another embodiment; Figure 4 A structural block diagram of a static reference model design apparatus for a programmable delay block in one embodiment; Figure 5 FIG. 4 is a diagram showing the internal structure of an electronic device in one embodiment. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0025] In one embodiment, Figure 1 As shown, a static reference model design method for a programmable delay block is provided, the method comprising the following steps: Step 100: Configure the delay value of each channel through a register.

[0026] Specifically, since the channel delay value is a register configuration, it is a static configuration.

[0027] The number of channels is configurable, and you only need to push the configured number of channels in the data preprocessing part, which provides reusability.

[0028] Step 102: sort the delay values ​​of all channels according to the size of the delay values ​​and store them in a queue to obtain a sorted channel data queue.

[0029] Step 104: When a data packet of the return value of the current channel x is received, the sorted channel data queue is traversed to see whether there is a channel with the same delay value as that of channel x.

[0030] Specifically, whether the channel reports an error is determined based on the delay value and the return value.

[0031] Step 106: If yes, channel x directly reports an error.

[0032] Step 108: Otherwise, determine whether channel x is to report an error by comparing channels in the sorted channel data queues with channels whose delay values ​​are smaller than that of channel x.

[0033] By designing through the above steps, the same calculation effect as the hardware design can be obtained, and it can be accurately determined whether the current channel will report an error, thereby achieving the purpose of verifying the hardware design by the reference model.

[0034] In the static reference model design method of the programmable delay block, the method includes: configuring the delay value of each channel through a register; sorting the delay values ​​of all channels according to the size of the delay value and storing them in a queue to obtain a sorted channel data queue; when receiving a data packet of the return value of the current channel x, traversing the sorted channel data queue to see if there is a channel with the same delay value as channel x; if so, channel x directly reports an error; otherwise, by comparing channels with smaller delay values ​​than channel x, it is determined whether channel x should report an error. This method realizes the judgment of the channel by comparing the delay value, and does not need to introduce timing information, thereby greatly reducing the design complexity, reducing the coupling between timing and hardware design, and reducing the quality risk of verification; the number of channels is configurable, and only the number of channels needs to be set during data preprocessing, thereby providing reusability.

[0035] In one embodiment, step 102 includes: starting from the first channel, determining whether the first channel is a bypass channel, and if so, forming channel data with the channel number and 0; otherwise, forming channel data with the channel number and the corresponding channel delay value, and pushing it into the channel data queue; continuing to process the next channel until all channels are traversed to obtain an unsorted channel data queue; and sorting the delay values ​​in each channel data in the unsorted channel data queue in ascending order to obtain a sorted channel data queue.

[0036] Specifically, the data preprocessing process is as follows: Figure 2 shown.

[0037] First, starting from the first channel, determine whether the channel is a bypass channel. If it is, the delay value is 0 and the channel number constitutes the channel data. If not, the channel number and the channel delay value constitute the channel data and push it into the channel data queue. After traversing all channels, sort the channel data queue according to the delay value in the channel data, with the smaller delay value at the front of the queue and the larger delay value at the back of the queue. In this way, a queue with the delay value sorted and the channel number is obtained, that is, Figure 2 Mid-channel data queue.

[0038] In one embodiment, step 108 includes: comparing whether the delay value of channel x is less than the sum of the delay value and the return value of each channel in front of channel x in the sorted channel data queue; if so, channel x reports an error; otherwise, channel x is correct.

[0039] Specifically, one input of the data judgment part is the sorted channel data queue, and the other is the trigger condition for the operation of the data judgment part. When the reference mode captures the data packet of the return value of the current channel x (the data packet here is sent by the relevant driver in the verification component environment, and the driver design is not included in this method), the data judgment part of the current channel x is triggered. Because, when the data packet of the return value of the current channel x is captured, it means that at this time in the operation of the hardware, the current channel x and the channel with a delay value smaller than that of channel x have been output. Before judging the relationship between the output of channel x and the return value of the remaining channels, you can first traverse the sorted channel data queue to see if there is a channel with the same delay value as channel x. If there is, you can directly report an error, because two or more delay values ​​are the same, and the return value must be greater than 0, then the channel with the same delay value must report an error. If there is no same value, you can proceed to the next step and compare the channels with a delay value smaller than that of channel x in the sorted channel data queue to determine whether channel x is to report an error. Since the sorted channel data queue sorted by delay value has been obtained, the delay value of channel x is traversed and compared to see if it is less than the sum of the delay value and return value of each channel before channel x in the sorted channel data queue. If it is less than the delay value of any previous channel y plus the return value of channel y, it means that when channel x is output, the return signal of channel y has not been received, and channel x will report an error.

[0040] In one of the embodiments, the method further includes: when a data packet of a return value is obtained, the return value is updated; the return value of the channel defaults to hffffffff; if a data packet of a return value is not obtained when preparing for judgment, and the return value is hffffffff, then an error is reported.

[0041] This method does not introduce the time dimension to implement the static reference model design of the programmable delay block. First, it solves the technical problem that the introduction of the clock increases the timing design and increases the design complexity of the reference model; secondly, it solves the technical problem that because the timing reference model is made, each time the hardware design has a timing modification or adjustment, the reference model must also be modified, making it not maintainable and reusable; most importantly, it solves the technical problem that since both the hardware design and the reference model are based on real-time design, the vulnerabilities of the two may be consistent, thereby greatly increasing the verification quality risk.

[0042] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0043] In one embodiment, Figure 4 As shown, a static reference model design device for a programmable delay block is provided, comprising: a data preprocessing module and a data judgment module, wherein: The data preprocessing module is used to configure the delay value of each channel through a register; the delay values ​​of all channels are sorted according to the size of the delay values ​​and stored in a queue to obtain a sorted channel data queue.

[0044] The data judgment module is used to traverse the sorted channel data queue to see if there is a channel with the same delay value as channel x when receiving the data packet of the return value of the current channel x; if so, channel x directly reports an error; otherwise, by comparing the channels with smaller delay values ​​than channel x in the sorted channel data queue, it is judged whether channel x should report an error.

[0045] In one of the embodiments, the data preprocessing module is also used to start from the first channel and determine whether the first channel is a bypass channel. If so, the channel number and 0 are used to form channel data; otherwise, the channel number and the corresponding channel delay value are used to form channel data and are pushed into the channel data queue; the next channel is processed until all channels are traversed to obtain an unsorted channel data queue; and the delay values ​​in each channel data in the unsorted channel data queue are sorted in ascending order to obtain a sorted channel data queue.

[0046] In one of the embodiments, the data judgment module is further used to compare whether the delay value of channel x is less than the sum of the delay value and return value of each channel in front of channel x in the sorted channel data queue; if so, channel x reports an error; otherwise, channel x is correct.

[0047] In one of the embodiments, the device also includes: an error reporting module for not receiving a return value data packet, which is used to update the return value when a data packet with a return value is obtained; the return value of the channel defaults to hffffffff; if no return value data packet is obtained when preparing for judgment, and the return value is hffffffff, an error is reported.

[0048] The specific definition of the static reference model design device for programmable delay blocks can be found in the definition of the static reference model design method for programmable delay blocks in the above text, which will not be repeated here. Each module in the above-mentioned static reference model design device for programmable delay blocks can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

[0049] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 5 As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a static reference model design method for a programmable delay block is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0050] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0051] In one embodiment, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps in the above method embodiment when executing the computer program.

[0052] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0053] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A static reference model design method for a programmable delay block, characterized in that: The method comprises: Configure the delay value of each channel through registers; The delay values ​​of all channels are sorted according to the size of the delay values ​​and stored in a queue to obtain a sorted channel data queue; When receiving the data packet of the return value of the current channel x, traverse the sorted channel data queue to see if there is a channel with the same delay value as channel x; If yes, channel x will report an error directly; Otherwise, it is determined whether channel x is to report an error by comparing the channels in the sorted channel data queue that have a smaller delay value than channel x.

2. The method according to claim 1, characterized in that The delay values ​​of all channels are sorted according to the size of the delay values ​​and stored in a queue to obtain a sorted channel data queue, including: Starting from the first channel, determine whether the first channel is a bypass channel. If it is, the channel number and 0 form the channel data; otherwise, the channel number and the corresponding channel delay value form the channel data and push it into the channel data queue; continue to process the next channel until all channels are traversed to obtain an unsorted channel data queue; The delay values ​​in each channel data in the unsorted channel data queue are sorted in ascending order to obtain a sorted channel data queue.

3. The method according to claim 1, characterized in that By comparing the channels with smaller delay values ​​than channel x in the sorted channel data queue, it is determined whether channel x is to report an error, including: Compare whether the delay value of channel x is less than the sum of the delay value and return value of each channel before channel x in the sorted channel data queue; If yes, channel x reports an error; otherwise, channel x is correct.

4. The method according to claim 1, characterized in that: The method further comprises: When the data packet of the return value is obtained, the return value is updated; the default return value of the channel is hffffffff; If no data packet with a return value is obtained when preparing for judgment, and the return value is hffffffff, the judgment will be reported as an error.

5. A static reference model design device method for a programmable delay block, characterized in that: The device comprises: The data preprocessing module is used to configure the delay value of each channel through a register; the delay values ​​of all channels are sorted according to the size of the delay values ​​and stored in a queue to obtain a sorted channel data queue; The data judgment module is used to traverse the sorted channel data queue to see whether there is a channel with the same delay value as channel x when receiving a data packet of the return value of the current channel x; if so, channel x directly reports an error; otherwise, by comparing the channels in the sorted channel data queue with a smaller delay value than channel x, it is determined whether channel x should report an error.

6. The device according to claim 5, characterized in that The data preprocessing module is further used to start from the first channel and determine whether the first channel is a bypass channel. If yes, the channel number and 0 are combined into channel data; Otherwise, the channel number and the corresponding channel delay value are combined into channel data and pushed into the channel data queue; Continue to process the next channel until all channels are traversed to obtain an unsorted channel data queue; sort the delay values ​​in each channel data in the unsorted channel data queue from small to large to obtain a sorted channel data queue.

7. The device according to claim 5, characterized in that The data judgment module is also used to compare whether the delay value of channel x is less than the sum of the delay value and return value of each channel in front of channel x in the sorted channel data queue; if so, channel x reports an error; otherwise, channel x is correct.

8. The device according to claim 5, characterized in that The device also includes: a module for reporting an error when a return value packet is not received, which is used to update the return value when a return value packet is obtained; the return value of the channel defaults to hffffffff; if a return value packet is not obtained when preparing for judgment, and the return value is hffffffff, then an error is reported.

9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 4 is implemented.

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