Chip optimization method and device of intelligent chip factory, controller and medium

Abstract

The invention discloses a chip optimization method and device for an intelligent chip factory, a controller and a medium, and relates to the technical field of chips. The method comprises the following steps: acquiring defect monitoring data of a chip; determining a target type defect according to the defect monitoring data of the chip and a preset defect diagnosis model; determining yield information of the target type defect according to the digital defect graph data corresponding to the target type defect, the integrated layout of the chip, the mask pattern information and a preset yield prediction model; and adjusting the integrated layout and / or mask pattern information of the chip according to the yield information of the target type defect. Therefore, the chip yield of an intelligent chip factory is improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a chip optimization method for an intelligent chip factory, a chip optimization device for an intelligent chip factory, a computer-readable storage medium, and a controller. Background Art

[0002] In the related technology, digital defect map data is not used when training the yield prediction model, and the defect scanning is lacking in full digitization capability, which causes the training data of the artificial intelligence computing system to be distorted, resulting in poor prediction effect of the yield prediction model, thus affecting the yield of the smart chip factory. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first purpose of the present application is to propose a chip optimization method for an intelligent chip factory, the method comprising: obtaining chip defect monitoring data; determining target type defects based on chip defect monitoring data and a preset defect diagnosis model; determining the yield information of the target type defects based on the digital defect map data corresponding to the target type defects, the integrated layout and mask pattern information of the chip and a preset yield prediction model; adjusting the integrated layout and / or mask pattern information of the chip based on the yield information of the target type defects. In this way, the chip yield of the intelligent chip factory is improved.

[0004] The second purpose of this application is to propose a chip optimization device for an intelligent chip factory.

[0005] The third object of the present application is to provide a computer-readable storage medium.

[0006] The fourth objective of the present application is to provide a controller.

[0007] To achieve the above-mentioned objectives, the first aspect of the present application proposes a chip optimization method for an intelligent chip factory, the method comprising: obtaining chip defect monitoring data; determining a target type defect based on the chip defect monitoring data and a preset defect diagnosis model; determining the yield information of the target type defect based on the digitized defect map data corresponding to the target type defect, the integrated layout and mask pattern information of the chip and a preset yield prediction model; adjusting the integrated layout and / or mask pattern information of the chip based on the yield information of the target type defect.

[0008] According to one embodiment of the present application, the yield information of the target type defect includes a layout line yield value, wherein the integrated layout of the chip is adjusted according to the yield information of the target type defect, including: when the layout line yield value is less than a first preset yield threshold, the integrated layout of the chip is adjusted.

[0009] According to one embodiment of the present application, the yield information of the target type defect includes a mask design yield value, wherein the mask pattern information of the chip is adjusted according to the yield information of the target type defect, including: when the mask design yield value is less than a second preset yield threshold, the mask pattern information of the chip is adjusted.

[0010] According to one embodiment of the present application, the above method also includes: modifying the simulated digital twins of the process tool and the reactor chamber to test the integrated layout and / or mask pattern information of the adjusted chip.

[0011] According to one embodiment of the present application, the above method also includes: obtaining offline defect monitoring data and online defect monitoring data of the chip; training a preset defect diagnosis model based on the offline defect monitoring data and the online defect monitoring data, wherein the offline defect monitoring data includes the defect type, defect information, digitized defect map data of the control wafer and the corresponding process machine and reactor chamber, and the online defect monitoring data includes the defect type, defect information, digitized defect map data of the product wafer and the corresponding process machine and reactor chamber.

[0012] According to one embodiment of the present application, the above method also includes: obtaining wafer acceptance test data, wafer capability test data, lithography exposure image data, integrated circuit layout data and integrated circuit mask pattern data; training a preset yield prediction model based on the wafer acceptance test data, wafer capability test data, lithography exposure image data, integrated circuit layout data and integrated circuit mask pattern data.

[0013] According to an embodiment of the present application, the above method further includes: maintaining the target type defect according to the maintenance technology corresponding to the target type defect to reduce the degree of the defect.

[0014] To achieve the above-mentioned objectives, the second aspect of the embodiment of the present application proposes a chip optimization device for an intelligent chip factory, the device comprising: an acquisition module for acquiring chip defect monitoring data; a first determination module for determining a target type defect based on the chip defect monitoring data and a preset defect diagnosis model; a second determination module for determining the yield information of the target type defect based on the digitized defect map data corresponding to the target type defect, the integrated layout and mask pattern information of the chip and a preset yield prediction model; an adjustment module for adjusting the integrated layout and / or mask pattern information of the chip according to the yield information of the target type defect.

[0015] To achieve the above-mentioned objectives, the third aspect embodiment of the present application proposes a computer-readable storage medium, on which a chip optimization program of an intelligent chip factory is stored. When the chip optimization program of the intelligent chip factory is executed by a processor, the aforementioned chip optimization method of the intelligent chip factory is implemented.

[0016] To achieve the above-mentioned objectives, the fourth aspect embodiment of the present application proposes a controller, including a memory, a processor, and a chip optimization program of an intelligent chip factory stored in the memory and executable on the processor. When the processor executes the chip optimization program of the intelligent chip factory, the aforementioned control method of the intelligent chip factory is implemented.

[0017] According to the chip optimization method, device, controller and medium of the smart chip factory of the embodiment of the present application, the method includes: obtaining chip defect monitoring data; determining the target type defect according to the chip defect monitoring data and the preset defect diagnosis model; determining the yield information of the target type defect according to the digital defect map data corresponding to the target type defect, the chip's integrated layout and mask pattern information and the preset yield prediction model; adjusting the chip's integrated layout and / or mask pattern information according to the yield information of the target type defect. In this way, the chip yield of the smart chip factory is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A flowchart of a chip optimization method of a smart chip factory according to some embodiments of the present application;

[0019] Figure 2 An analysis diagram of a chip optimization method of a smart chip factory according to some embodiments of the present application;

[0020] Figure 3 A block diagram of a chip optimization device of an intelligent chip factory according to some embodiments of the present application;

[0021] Figure 4 is a block diagram of a controller according to some embodiments of the present application. DETAILED DESCRIPTION

[0022] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0023] The chip optimization method, device, controller and medium of the smart chip factory of the embodiment of the present application are described in detail below with reference to the accompanying drawings.

[0024] Figure 1 Flow chart of a chip optimization method of an intelligent chip factory according to some embodiments of the present application. Figure 1 The chip optimization method of the smart chip factory of the embodiment of the present application may include the following steps:

[0025] S110, obtaining chip defect monitoring data.

[0026] Specifically, the chip defect monitoring data can be acquired through high-speed industrial cameras, and the specific acquisition method is not limited here.

[0027] S120, determining a target type defect according to the chip defect monitoring data and a preset defect diagnosis model.

[0028] Specifically, there are defects that affect chip yield and defects that do not affect chip yield among chip defects, and target type defects refer to defects that affect chip yield. Inputting chip defect monitoring data into a preset defect diagnosis model can diagnose target type defects among chip defects.

[0029] S130, determining yield information of the target type defect according to the digital defect map data corresponding to the target type defect, the integrated layout and mask pattern information of the chip, and a preset yield prediction model.

[0030] Specifically, after determining the target type defects that affect the yield, it is necessary to further determine the reasons why the target type defects affect the yield, such as determining whether the chip yield is low due to the chip's integrated layout or the chip's mask pattern. Therefore, it is necessary to input the digital defect map data corresponding to the target type defects, the chip's integrated layout and mask pattern information into the preset yield prediction model to predict the yield information of the target type defects, such as predicting the layout line yield value and the mask design yield value.

[0031] S140, adjusting the integrated layout and / or mask pattern information of the chip according to the yield information of the target type defect.

[0032] Specifically, after determining the yield information of the target type defect, for example, determining the layout line yield value and the mask design yield value, the layout line yield value and the mask design yield value are compared with the preset yield value, and based on the comparison result, it is determined whether the target type defect affects the chip yield due to the integrated layout, mask pattern information, or the integrated layout and mask pattern information, and based on the comparison result, the integrated layout, mask pattern information, or the integrated layout and mask pattern information are adjusted to improve the yield.

[0033] Exemplarily, if the layout line yield value is relatively low, it means that the target type defects caused by the integrated layout affect the chip yield, and the integrated layout is adjusted; if the mask design yield value is relatively low, it means that the target type defects caused by the mask design affect the chip yield, and the mask pattern information is adjusted; if the layout line yield value and the mask design yield value are both relatively low, it means that the target type defects caused by the integrated layout and grinding design affect the chip yield, and the integrated layout and mask pattern information are adjusted.

[0034] In this way, the chip yield of the smart chip factory is improved.

[0035] In some embodiments, the yield information of the target type defect includes a layout line yield value, wherein adjusting the integrated layout of the chip according to the yield information of the target type defect includes: when the layout line yield value is less than a first preset yield threshold, adjusting the integrated layout of the chip. The first preset yield threshold can be determined according to actual conditions and is not specifically limited here.

[0036] Specifically, the layout line yield value is compared with the first preset yield threshold, and it is determined based on the comparison result whether the target type defect caused by the integrated layout affects the chip yield. When it is determined that the chip yield is low due to the integrated layout, the integrated layout of the chip is adjusted to improve the chip yield.

[0037] Exemplarily, if the layout line yield value is greater than or equal to the first preset yield threshold, it means that the integrated layout is not the cause of the target type defects affecting the chip yield, and there is no need to adjust the integrated layout of the chip; if the layout line yield value is less than the first preset yield threshold, it means that the integrated layout is the cause of the target type defects affecting the chip yield, and the integrated layout of the chip needs to be adjusted to improve the chip yield.

[0038] In some embodiments, the yield information of the target type defect includes a mask design yield value, wherein the mask pattern information of the chip is adjusted according to the yield information of the target type defect, including: when the mask design yield value is less than a second preset yield threshold, the mask pattern information of the chip is adjusted. The second preset yield threshold can be determined according to actual conditions and is not specifically limited here.

[0039] Specifically, the mask design yield value is compared with the second preset yield threshold, and a determination is made based on the comparison result as to whether the target type defects caused by the mask design have affected the chip yield. If it is determined that the chip yield is low due to the mask design, the mask pattern information of the chip is adjusted to improve the chip yield.

[0040] Exemplarily, if the mask design yield value is greater than or equal to the second preset yield threshold, it means that the mask design is not the reason why the target type defects affect the chip yield, and there is no need to adjust the mask pattern information of the chip; if the mask design yield value is less than the second preset yield threshold, it means that the mask design is the reason why the target type defects affect the chip yield, and it is necessary to adjust the mask pattern information of the chip to improve the chip yield.

[0041] In some embodiments, the above method also includes: modifying the simulated digital twins of the process tool and the reactor chamber to test the integrated layout and / or mask pattern information of the adjusted chip.

[0042] Specifically, after adjusting the integrated layout, mask pattern information, or the integrated layout and mask pattern information of the chip, the simulated digital twin of the process tool and the reactor cavity also needs to be modified accordingly to test the adjusted integrated layout, mask pattern information, or the integrated layout and mask pattern information of the chip, and determine whether to modify the process tool and the reactor cavity based on the test results.

[0043] Exemplarily, if the test results show that the chip yield is improved after the integrated layout, mask pattern information, or integrated layout and mask pattern information of the adjusted chip are modified, the process tool and the reactor chamber are also modified accordingly; if the test results show that the chip yield is not improved after the integrated layout, mask pattern information, or integrated layout and mask pattern information of the adjusted chip are modified, the process tool and the reactor chamber are not modified accordingly.

[0044] In some embodiments, the above method also includes: obtaining offline defect monitoring data and online defect monitoring data of the chip; training a preset defect diagnosis model based on the offline defect monitoring data and the online defect monitoring data, wherein the offline defect monitoring data includes the defect type, defect information, digitized defect map data of the control wafer and the corresponding process machine and reactor chamber, and the online defect monitoring data includes the defect type, defect information, digitized defect map data of the product wafer and the corresponding process machine and reactor chamber.

[0045] Exemplarily, the surface of the control wafer is scanned and captured by a high-precision industrial camera and an optical system, and defect features are extracted using image processing technology, defect types (such as particles, scratches, contact defects, voids, bubbles, and contamination, etc.) and defect information (such as the length, position, and shape of the defect, etc.) of the defect features are annotated, and the defect information is digitized and converted into corresponding digital defect map data, and combined with the corresponding process machine and reactor cavity, the offline defect monitoring data of the chip (the defect data of the control wafer) is jointly constituted. The acquisition method of the online defect monitoring data of the chip (the defect data of the product wafer) is the same as the acquisition method of the offline defect monitoring data, which will not be repeated here. The offline monitoring data and the online monitoring data are integrated to form a unified data set, and the data is preprocessed, such as standardization and normalization. Further, a suitable defect diagnosis model is selected, such as a convolutional neural network based on deep learning or a YOLOv8 model, and the training parameters are set. The model is trained using the integrated data set to obtain a preset defect diagnosis model.

[0046] It should be noted that the specific defect diagnosis model training method is not specifically limited here.

[0047] In some embodiments, the above method also includes: obtaining wafer acceptance test data, wafer capability test data, lithography exposure image data, integrated circuit layout data and integrated circuit mask pattern data; training a preset yield prediction model based on the wafer acceptance test data, wafer capability test data, lithography exposure image data, integrated circuit layout data and integrated circuit mask pattern data.

[0048] Exemplarily, the wafer acceptance test data includes the test results of each position on the wafer (for example, whether the pattern route signal of the wafer is powered on), which can be detected and obtained through the wafer fab's production management system. Wafer capability test data includes the capability test results of each position of the wafer (for example, whether the response speed of the CPU of the wafer pattern route is qualified), which can be obtained through the wafer fab's statistical process control system. Lithography exposure map data refers to the exposure conditions during the lithography process, which can be obtained through the control system of the lithography machine. Integrated circuit layout data refers to the design layout of the integrated circuit, which can be exported from the integrated circuit design software. Integrated circuit mask pattern data contains mask patterns used to manufacture integrated circuits, which are usually provided by the mask production system. The above data are integrated to form a unified data set, and the data is preprocessed, such as normalization, denoising, missing value processing, etc. Further, a suitable yield prediction model is selected, such as a support vector machine, K-nearest neighbor, random forest, etc., training parameters are set, and the model is trained using the integrated data set to obtain a yield prediction model.

[0049] It should be noted that the specific yield prediction model training method is not specifically limited here.

[0050] In some embodiments, the above method further includes: maintaining the target type defect according to a maintenance technology corresponding to the target type defect to reduce the degree of the defect.

[0051] Specifically, the digital defect map data corresponding to the target type defect is transmitted to the PMS (Periodical Maintenance System). The PMS maintains the target type defect according to the maintenance technology corresponding to the target type defect to reduce the degree of defect. In addition, the digital defect map data corresponding to defects other than the target type defect can also be transmitted to the PMS. The PMS maintains the defects other than the target type defect according to the maintenance technology corresponding to the defects other than the target type defect to further reduce the degree of defect. In this way, the PMS is dynamically supported to adjust the machine warranty and guide the direction of machine warranty to timely reduce defects and failure rates.

[0052] It should be noted that virtual measurement technology may be used during the production process of product wafers. For example, the operating parameters of the process tools are input into the preset virtual measurement AI model to predict the product parameters. If the prediction result is inaccurate, it may also affect the chip yield. Therefore, after determining the yield information of the target type defects and adjusting the chip's integrated layout and / or mask pattern information according to the yield information of the target type defects, if the chip yield still cannot be improved, the preset virtual measurement AI model needs to be adjusted to improve the chip yield.

[0053] As a specific example, see Figure 2 , train the preset defect diagnosis model according to the defect type, defect information, digital defect map data of the control wafer and the corresponding process machine and reactor chamber and the defect type, defect information, digital defect map data of the product wafer and the corresponding process machine and reactor chamber, input the chip defect monitoring data into the preset defect diagnosis model for defect diagnosis, and diagnose the target type defects in the chip defects, that is, determine the defects that affect the chip yield.

[0054] The preset yield prediction model is trained based on wafer acceptance test data, wafer capability test data, photolithography exposure map data, integrated circuit layout data, and integrated circuit mask pattern data. The digital defect map data corresponding to the target type defect, the integrated layout of the chip, and the mask pattern information are input into the preset yield prediction model to predict the layout line yield value and the mask design yield value of the target type defect. The integrated layout and / or mask pattern information of the chip are adjusted according to the layout line yield value and the mask design yield value to improve the chip yield. After adjusting the integrated layout and / or mask pattern information of the chip, the simulated digital twin of the process machine and the reactor cavity is also modified to test the adjusted integrated layout and / or mask pattern information of the chip. In addition, the preset defect diagnosis model also transmits the digital defect map data corresponding to the target type defect and the digital defect map data corresponding to the defect other than the target type defect to the PMS, and the PMS maintains the defect according to the corresponding maintenance technology to reduce the degree of the defect.

[0055] In summary, the optimization method of the present application fully digitizes the defect information scanning, collects data and information such as defect location, defect characteristics, defect quantity, defect composition and defect classification, and defect cause source, and uses these data to train a preset defect diagnosis model and a preset yield prediction model, and uses the preset defect diagnosis model to determine the defect type that affects the yield, and uses the preset yield prediction model to determine the reason why the defect affects the yield, and makes corresponding adjustments based on the reason that affects the yield, thereby improving the chip yield; it can also avoid the damage of electron beam scanning ions to the product to a certain extent, reduce or replace the machine or product defect scanning frequency or sampling number and scanning frequency area, dynamically support PMS to adjust the machine warranty, guide the machine warranty direction to timely reduce defects and failure rates, provide real-time feedback on machine or chip anomalies and failures, search for machines with poor performance or outliers in the machine group, assist in machine evaluation to assist in dynamic optimization of the process machine system, assist in digital twin simulation of process machines and reactor chambers, and optimize process machines.

[0056] Corresponding to the above embodiments, the present application also proposes a chip optimization device for an intelligent chip factory.

[0057] Reference Figure 3 The chip optimization device 300 of the intelligent chip factory includes: an acquisition module 310, a first determination module 320, a second determination module 330 and an adjustment module 340.

[0058] Among them, the acquisition module 310 is used to acquire the defect monitoring data of the chip. The first determination module 320 is used to determine the target type defect according to the defect monitoring data of the chip and the preset defect diagnosis model. The second determination module 330 is used to determine the yield information of the target type defect according to the digital defect map data corresponding to the target type defect, the integrated layout and mask pattern information of the chip and the preset yield prediction model. The adjustment module 340 is used to adjust the integrated layout and / or mask pattern information of the chip according to the yield information of the target type defect.

[0059] According to an embodiment of the present application, the yield information of the target type defect includes a layout line yield value, and the adjustment module 340 is specifically used to adjust the integrated layout of the chip when the layout line yield value is less than a first preset yield threshold.

[0060] According to an embodiment of the present application, the yield information of the target type defect includes a mask design yield value, and the adjustment module 340 is specifically used to adjust the mask pattern information of the chip when the mask design yield value is less than a second preset yield threshold.

[0061] According to one embodiment of the present application, the simulated digital twins of the process tool and the reactor chamber are modified to test the integrated layout and / or mask pattern information of the adjusted chip.

[0062] According to one embodiment of the present application, offline defect monitoring data and online defect monitoring data of a chip are obtained; a preset defect diagnosis model is trained based on the offline defect monitoring data and the online defect monitoring data, wherein the offline defect monitoring data includes defect types, defect information, digitized defect map data of a control wafer, and corresponding process machines and reactor chambers, and the online defect monitoring data includes defect types, defect information, digitized defect map data of a product wafer, and corresponding process machines and reactor chambers.

[0063] According to one embodiment of the present application, wafer acceptance test data, wafer capability test data, lithography exposure image data, integrated circuit layout data and integrated circuit mask pattern data are obtained; and a preset yield prediction model is trained based on the wafer acceptance test data, wafer capability test data, lithography exposure image data, integrated circuit layout data and integrated circuit mask pattern data.

[0064] According to an embodiment of the present application, the target type defect is maintained according to the maintenance technology corresponding to the target type defect to reduce the defect degree.

[0065] It should be pointed out that the above-mentioned explanation of the embodiments and beneficial effects of the chip optimization method of the smart chip factory is also applicable to the chip optimization device of the smart chip factory of the embodiment of the present application. In order to avoid redundancy, it will not be elaborated here.

[0066] Corresponding to the above embodiments, the present application also proposes a computer-readable storage medium.

[0067] The computer-readable storage medium of the present application stores a chip optimization program of an intelligent chip factory, and when the chip optimization program of the intelligent chip factory is executed by a processor, the aforementioned chip optimization method of the intelligent chip factory is implemented.

[0068] It should be pointed out that the above-mentioned explanation of the embodiments and beneficial effects of the chip optimization method of the smart chip factory is also applicable to the computer-readable storage medium of the embodiment of the present application. In order to avoid redundancy, it will not be expanded here in detail.

[0069] Corresponding to the above embodiments, the present application also proposes a controller.

[0070] See also Figure 4 As shown, the controller 400 of the present application includes a memory 410, a processor 420, and a chip optimization program of the smart chip factory stored in the memory 410 and executable on the processor 420. When the processor 420 executes the chip optimization program of the smart chip factory, the aforementioned control method of the smart chip factory is implemented.

[0071] It should be pointed out that the above-mentioned explanation of the embodiments and beneficial effects of the control method of the smart chip factory are also applicable to the controller of the embodiment of the present application. In order to avoid redundancy, they will not be elaborated here.

[0072] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0073] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0074] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0075] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0076] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0077] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A chip optimization method for an intelligent chip factory, characterized in that: The method comprises: Obtain chip defect monitoring data; Determining a target type defect according to defect monitoring data of the chip and a preset defect diagnosis model; Determining yield information of the target type defect according to the digitized defect map data corresponding to the target type defect, the integrated layout and mask pattern information of the chip, and a preset yield prediction model; The integrated layout and / or mask pattern information of the chip is adjusted according to the yield information of the target type defect.

2. The chip optimization method of the smart chip factory according to claim 1, characterized in that: The yield information of the target type defect includes a layout line yield value, wherein adjusting the integrated layout of the chip according to the yield information of the target type defect includes: When the layout line yield value is less than a first preset yield threshold, the integrated layout of the chip is adjusted.

3. The chip optimization method of the smart chip factory according to claim 1 or 2, characterized in that: The yield information of the target type defect includes a mask design yield value, wherein the mask pattern information of the chip is adjusted according to the yield information of the target type defect, including: When the mask design yield value is less than a second preset yield threshold, the mask pattern information of the chip is adjusted.

4. The chip optimization method of the smart chip factory according to claim 3, characterized in that: The method further comprises: The simulated digital twins of the process tool and the reactor chamber are modified to test the adjusted integrated layout and / or mask pattern information of the chip.

5. The chip optimization method of the smart chip factory according to claim 1, characterized in that: The method further comprises: Obtain offline defect monitoring data and online defect monitoring data of chips; The preset defect diagnosis model is trained according to the offline defect monitoring data and the online defect monitoring data, wherein the offline defect monitoring data includes the defect type, defect information, digitized defect map data of the control wafer and the corresponding process machine and reactor cavity, and the online defect monitoring data includes the defect type, defect information, digitized defect map data of the product wafer and the corresponding process machine and reactor cavity.

6. The chip optimization method of the smart chip factory according to claim 1, characterized in that: The method further comprises: Obtain wafer acceptance test data, wafer capability test data, photolithography exposure map data, integrated circuit layout data, and integrated circuit mask pattern data; The preset yield prediction model is trained according to the wafer acceptance test data, the wafer capability test data, the photolithography exposure map data, the integrated circuit layout data and the integrated circuit mask pattern data.

7. The chip optimization method of the smart chip factory according to claim 1, characterized in that: The method further comprises: The target type defect is maintained according to the maintenance technology corresponding to the target type defect to reduce the defect degree.

8. A chip optimization device for an intelligent chip factory, characterized in that: The device comprises: An acquisition module, used to acquire chip defect monitoring data; A first determination module, configured to determine a target type defect according to defect monitoring data of the chip and a preset defect diagnosis model; A second determination module is used to determine the yield information of the target type defect according to the digital defect map data corresponding to the target type defect, the integrated layout and mask pattern information of the chip and a preset yield prediction model; An adjustment module is used to adjust the integrated layout and / or mask pattern information of the chip according to the yield information of the target type defect.

9. A computer-readable storage medium, characterized in that: A chip optimization program of an intelligent chip factory is stored thereon, and when the chip optimization program of an intelligent chip factory is executed by a processor, the chip optimization method of an intelligent chip factory according to claims 1-7 is implemented.

10. A controller, characterized in that: It includes a memory, a processor, and a chip optimization program of an intelligent chip factory stored in the memory and executable on the processor. When the processor executes the chip optimization program of the intelligent chip factory, the control method of the intelligent chip factory according to claims 1-7 is implemented.

Images