Storage detection circuit and method, electronic equipment and storage medium

Abstract

The invention provides a storage detection circuit and method, electronic equipment and a storage medium. The storage detection circuit comprises a first-stage detection circuit, a second-stage detection circuit and an exception handling circuit, the first stage detection circuit is used for detecting the system-on-chip storage unit in the first stage to obtain a first detection result; the first detection result is sent to the abnormity processing circuit; the second-stage detection circuit is used for detecting the system-on-chip storage unit in a second stage to obtain a second detection result; the second detection result is sent to the abnormity processing circuit; and the exception processing circuit is used for processing the first detection result and the second detection result to obtain a processing result of the system on chip. According to the method, the storage unit of the system on chip is detected through two stages, so that the detection comprehensiveness is improved, and the accuracy of a detection result is ensured.

Description

Technical Field

[0001] The present application relates to the field of storage detection technology, and in particular to a storage detection circuit, method, electronic device and storage medium. Background Art

[0002] Integrated circuit English: integrated circuit, abbreviated as IC; also known as microcircuit, microchip, wafer / chip, in electronics, is a way to miniaturize circuits (mainly including semiconductor devices, but also passive components, etc.), and is often manufactured on the surface of semiconductor wafers. During use, the chip (system on chip) needs to be configured with storage units (including flash, sram, etc.). In order to ensure the normal working process, the storage units of the system on chip need to be tested.

[0003] In the prior art, the detection method for the upper system storage unit takes fewer factors into consideration and the detection of the storage unit is not comprehensive enough, resulting in the risk that the storage unit still has abnormalities after detection. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide a storage detection circuit, method, electronic device and storage medium to overcome the problems in the prior art.

[0005] In a first aspect, an embodiment of the present application provides a storage detection circuit, the storage detection circuit comprising: a first-stage detection circuit, a second-stage detection circuit and an abnormality processing circuit; wherein the first-stage detection circuit is connected to the abnormality processing circuit, and the second-stage detection circuit is connected to the abnormality processing circuit;

[0006] The first stage detection circuit is used to detect the on-chip system storage unit in the first stage to obtain a first detection result; and send the first detection result to the abnormality processing circuit;

[0007] The second stage detection circuit is used to detect the system-on-chip storage unit in the second stage to obtain a second detection result; and send the second detection result to the exception processing circuit;

[0008] The exception processing circuit is used to process the first detection result and the second detection result to obtain a processing result of the system on chip.

[0009] In some technical solutions of the present application, the first-stage detection circuit is a power-on self-test circuit; the first-stage detection circuit is used to detect the on-chip system storage unit in the first stage to obtain a first detection result; and send the first detection result to the exception handling circuit, including:

[0010] The power-on self-test circuit is used to test the storage units in all areas of the on-chip system in the power-on stage to obtain a first test result; and send the first test result to the abnormality processing circuit.

[0011] In some technical solutions of the present application, the power-on self-test circuit comprises: a power-on circuit, a storage verification unit and a first result processing unit; wherein the power-on circuit is connected to the storage verification unit, and the storage verification unit is connected to the first result processing unit;

[0012] The power-on circuit is used to perform power-on detection on the system on chip to obtain the connection status of the system on chip; and send the connection status of the system on chip to the storage verification unit;

[0013] The storage verification unit is used to verify the storage unit using a preset verification algorithm when the connection state of the system on chip is in the power-on stage to obtain a first verification result; and send the first verification result to the first result processing unit;

[0014] The first result processing unit is used to determine a corresponding result processing method according to the first verification result.

[0015] In some technical solutions of the present application, the second-stage detection circuit is an idle detection circuit; the second-stage detection circuit is used to detect the system-on-chip storage unit in the second stage to obtain a second detection result; and send the second detection result to the exception processing circuit, including:

[0016] The idle detection circuit is used to detect the storage unit of the target area of ​​the on-chip system in an idle state during operation to obtain a second detection result; and send the second detection result to the exception processing circuit.

[0017] In some technical solutions of the present application, the idle time detection circuit includes: a bus application unit, a storage area detection unit and a second result processing unit; wherein the bus application unit is connected to the storage area detection unit, and the storage area detection unit is connected to the second result processing unit;

[0018] The bus application unit is used to configure the address range of the target area;

[0019] The storage area detection unit is used to verify the storage unit using a preset verification algorithm when the storage unit in the target area of ​​the system on chip is in an idle state during operation, to obtain a second verification result; and send the second verification result to the second result processing unit;

[0020] The second result processing unit is used to determine a corresponding result processing method according to the second verification result.

[0021] In some technical solutions of the present application, the storage area detection unit, when the storage unit used for the target area of ​​the system on chip is in an idle state during operation, verifies the storage unit using a preset verification algorithm to obtain a second verification result; and sends the second verification result to the second result processing unit, includes:

[0022] According to the detection requirements, configure the starting address and the ending address of the target area;

[0023] According to the detection accuracy, a target verification algorithm is configured from a plurality of verification algorithms to be selected; wherein the target verification algorithm includes using one or more of the verification algorithms to be selected;

[0024] When the storage unit in the target area of ​​the system on chip is in an idle state during operation, the storage unit is verified using the target verification algorithm to obtain a second verification result; and the second verification result is sent to the second result processing unit.

[0025] In some technical solutions of the present application, the storage unit includes a first subunit and a second subunit;

[0026] The storage area detection unit, when the storage unit used for the target area of ​​the system on chip is in an idle state during operation, verifies the storage unit using a preset verification algorithm to obtain a second verification result; and sends the second verification result to the second result processing unit, includes:

[0027] When the storage unit in the target area of ​​the system on chip is in an idle state during operation, using a preset verification algorithm to verify the first sub-unit and the second sub-unit respectively to obtain a first sub-result and a second sub-result;

[0028] The second verification result is obtained according to the first sub-result and the second sub-result; and the second verification result is sent to the second result processing unit.

[0029] In a second aspect, an embodiment of the present application provides a storage detection method, which acts on a storage detection circuit, wherein the storage detection circuit includes: a first-stage detection circuit, a second-stage detection circuit, and an exception processing circuit; wherein the first-stage detection circuit is connected to the exception processing circuit, and the second-stage detection circuit is connected to the exception processing circuit; the method includes:

[0030] The first stage detection circuit detects the on-chip system storage unit in the first stage to obtain a first detection result; and sends the first detection result to the abnormality processing circuit;

[0031] The second stage detection circuit detects the system-on-chip storage unit in the second stage to obtain a second detection result; and sends the second detection result to the exception processing circuit;

[0032] The exception processing circuit processes the first detection result and the second detection result to obtain a processing result of the system on chip.

[0033] In a third aspect, an embodiment of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned storage detection method when executing the computer program.

[0034] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned storage detection method are executed.

[0035] The technical solution provided by the embodiments of the present application may have the following beneficial effects:

[0036] An embodiment of the present application provides a storage detection circuit, which includes: a first-stage detection circuit, a second-stage detection circuit and an exception processing circuit; wherein the first-stage detection circuit is connected to the exception processing circuit, and the second-stage detection circuit is connected to the exception processing circuit; the first-stage detection circuit is used to detect a system-on-chip storage unit in the first stage to obtain a first detection result; and send the first detection result to the exception processing circuit; the second-stage detection circuit is used to detect the system-on-chip storage unit in the second stage to obtain a second detection result; and send the second detection result to the exception processing circuit; the exception processing circuit is used to process the first detection result and the second detection result to obtain a processing result of the system-on-chip.

[0037] The present application detects the storage unit of the system on chip in two stages, thereby improving the comprehensiveness of the detection and ensuring the accuracy of the detection results.

[0038] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 A schematic diagram of a storage detection circuit provided in an embodiment of the present application is shown;

[0041] Figure 2 A schematic diagram of another storage detection circuit provided in an embodiment of the present application is shown;

[0042] Figure 3 A schematic diagram of a power-on self-test circuit provided in an embodiment of the present application is shown;

[0043] Figure 4 A schematic diagram of a storage verification unit provided in an embodiment of the present application is shown;

[0044] Figure 5 A schematic diagram of an idle detection circuit provided in an embodiment of the present application is shown;

[0045] Figure 6 A schematic diagram of a storage detection method provided in an embodiment of the present application is shown;

[0046] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0048] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0049] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0050] Integrated circuit English: integrated circuit, abbreviated as IC; also known as microcircuit, microchip, wafer / chip, in electronics, is a way to miniaturize circuits (mainly including semiconductor devices, but also passive components, etc.), and is often manufactured on the surface of semiconductor wafers. During use, the chip (system on chip) needs to be configured with storage units (including flash, sram, etc.). In order to ensure the normal working process, the storage units of the system on chip need to be tested.

[0051] In the prior art, the detection method for the upper system storage unit takes fewer factors into consideration and the detection of the storage unit is not comprehensive enough, resulting in the risk that the storage unit still has abnormalities after detection.

[0052] Based on this, the embodiments of the present application provide a storage detection circuit, method, electronic device and storage medium, which are described below through embodiments.

[0053] Figure 1A schematic diagram of the structure of a storage detection circuit provided in an embodiment of the present application is shown, wherein the storage detection circuit comprises: a first-stage detection circuit, a second-stage detection circuit and an abnormality processing circuit; wherein the first-stage detection circuit is connected to the abnormality processing circuit, and the second-stage detection circuit is connected to the abnormality processing circuit;

[0054] The first stage detection circuit is used to detect the on-chip system storage unit in the first stage to obtain a first detection result; and send the first detection result to the abnormality processing circuit;

[0055] The second stage detection circuit is used to detect the system-on-chip storage unit in the second stage to obtain a second detection result; and send the second detection result to the exception processing circuit;

[0056] The exception processing circuit is used to process the first detection result and the second detection result to obtain a processing result of the system on chip.

[0057] The present application detects the storage unit of the system on chip in two stages, thereby improving the comprehensiveness of the detection and ensuring the accuracy of the detection results.

[0058] Some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0059] In order to detect the storage unit more accurately, the present application uses two detection circuits (first stage detection circuit and second stage detection circuit) to detect the storage unit in two stages (first stage and second stage) of the on-chip system respectively.

[0060] like Figure 2 As shown, the first-stage detection circuit in the embodiment of the present application is a power-on self-test circuit, and the second-stage detection circuit is an idle detection circuit. The power-on self-test circuit detects the storage unit of the system-on-chip that is in the upper electrolysis stage, and the idle detection circuit detects the storage unit of the system-on-chip that is in the working state and in the idle state. It should be noted that the first-stage detection circuit detects all the storage units of the system-on-chip, while the second-stage detection circuit detects the storage units in the target area of ​​the system-on-chip. The target area here can be all areas of the system-on-chip, or it can be a partial area of ​​the system-on-chip. That is, the embodiment of the present application can obtain a more comprehensive detection result by detecting the storage units of the system-on-chip in more states.

[0061] In an optional embodiment, if Figure 3As shown, the power-on self-test circuit in the embodiment of the present application includes: a power-on circuit, a storage verification unit and a first result processing unit; wherein the power-on circuit is connected to the storage verification unit, and the storage verification unit is connected to the first result processing unit; the power-on circuit is used to perform power-on detection on the system on chip to obtain the connection status of the system on chip; and send the connection status of the system on chip to the storage verification unit; the storage verification unit is used to use a preset verification algorithm to verify the storage unit when the connection status of the system on chip is in the power-on stage, and obtain a first verification result; and send the first verification result to the first result processing unit; the first result processing unit is used to determine the corresponding result processing method according to the first verification result.

[0062] When implementing it, Figure 4 As shown, the power-on self-test circuit mainly completes the detection of the storage unit inside the on-chip system when power is turned on. Power-on circuit: mainly performs power-on detection. When the power is completed, the power-on reset of the chip is canceled, and the storage verification unit starts automatic verification. The on-chip system generally includes multiple sub-units, such as a first sub-unit (FLASH) and a second sub-unit (SRAM). The storage verification unit needs to distinguish between FLASH and SRAM. For SRAM: the verification control unit first initializes SRAM before verification, that is, writes verification data (such as: 0x55555555) into SRAM, and then reads SRAM data to complete, and verifies the written data through the preset verification algorithm. For FLASH: only need to execute FLASH reading, and then verify through the preset verification algorithm to see if the corresponding error occurs.

[0063] For example, the preset check algorithm is ECC check, and other check methods such as CRC or parity check can also be used. The ECC algorithm can generate single-bit or multi-bit error types, among which single-bit errors can be corrected and multi-bit errors cannot be corrected. The type and address corresponding to the error will be output to the port, that is, sram_error_type (0, no error; 1, single-bit error; 2 multi-bit error), sram_error_addr (the corresponding address of the error); after checking all addresses, write the first bit-inverted data (0xaaaaaaaa) again, and then perform the same operation.

[0064] When the verification of FLASH and SRAM is completed, check_finish is generated, indicating the end of the verification, and the first sub-result and the second sub-result are obtained. The first sub-result and the second sub-result are integrated to obtain the first verification result. The first result processing unit determines the corresponding result processing method for the first verification result. For example, when a multi-bit error is generated by the verification, a non-maskable error interrupt is generated and given to the CPU. When a single-bit error is generated, it is correctable at this time, and a corresponding error flag bit, i.e., single_error_flag, is generated, which can be checked through the application. For the error addresses generated, the application can query where they come from.

[0065] In an optional embodiment, if Figure 5 As shown, the idle time detection circuit in the embodiment of the present application includes: a bus application unit, a storage area detection unit and a second result processing unit; wherein the bus application unit is connected to the storage area detection unit, and the storage area detection unit is connected to the second result processing unit;

[0066] The bus application unit is used to configure the address range of the target area;

[0067] The storage area detection unit is used to verify the storage unit using a preset verification algorithm when the storage unit in the target area of ​​the system on chip is in an idle state during operation, to obtain a second verification result; and send the second verification result to the second result processing unit;

[0068] The second result processing unit is used to determine a corresponding result processing method according to the second verification result.

[0069] In the specific implementation, the idle detection circuit is mainly used to detect the storage area of ​​the system on chip when the system on chip is idle. This detection function needs to be enabled in the customer application, that is, only when the corresponding function is enabled can the storage area be detected accordingly. Before performing the detection, it is necessary to configure the address range of the detection, start_addr or end_addr. The corresponding preset verification algorithm also needs to be configured. For example, the detection mode is configured to be CRC, ECC, or parity check; and the check mode can also control whether to continue multiple detections or only detect once. Configure the golden_data for the detection, such as: configure it as CRC check, what is the CRC check value. Turn on check_enable, that is, start the detection enable, configure it to 1, and perform the verification.

[0070] When the verification starts, the idle detection circuit will apply for access rights to the storage area. This access right has the lowest priority. If the system on chip accesses the storage area, it cannot obtain access rights to the storage area. Only when other master devices do not access it can it obtain bus rights. Storage area detection detects data according to the configured detection mode and records the errors and addresses generated.

[0071] Specifically, the storage area detection unit needs to distinguish between FLASH and SRAM when performing detection. For SRAM: the verification control unit first initializes SRAM before performing the verification, that is, writes verification data (such as: 0x55555555) into SRAM, and then reads the SRAM data to complete, and verifies the written data through a preset verification algorithm. For FLASH: it is only necessary to execute FLASH reading, and then verify through a preset verification algorithm to see if a corresponding error occurs. When the verification of FLASH and SRAM is completed, check_finish is generated, indicating the end of the verification, and the first sub-result and the second sub-result are obtained. The first sub-result and the second sub-result are integrated to obtain a second verification result. The second result processing unit determines the corresponding result processing method for the first verification result.

[0072] After the test is completed, the check_mode mode is used to determine whether to exit the test. If a single test is configured, the test will only perform a data test once. If the continuous test mode is used, the storage area will be tested continuously.

[0073] After detecting the storage units of the system-on-chip at different stages, the exception handling circuit obtains the first detection result and the second detection result of the corresponding stage. The processing result is obtained by processing the first detection result and the second detection result. For example, when the system is powered on, when an uncorrectable error is detected, an NMI interrupt will be generated. The application layer can issue a system error alarm based on the uncorrectable error and put the chip into an idle state. When powered on, if it is detected that a single area SRAM or flash has an error exceeding the rated number or a single-bit error has occurred in both flash and SRAM, an interrupt will be generated and an alarm will be issued at the application layer. When an error occurs during idle detection, an interrupt will be generated and an alarm will be issued at the application layer.

[0074] In an optional implementation, the storage area detection unit, when the storage unit used in the target area of ​​the system on chip is in an idle state during operation, verifies the storage unit using a preset verification algorithm to obtain a second verification result; and sends the second verification result to the second result processing unit, includes:

[0075] According to the detection requirements, configure the starting address and the ending address of the target area;

[0076] According to the detection accuracy, a target verification algorithm is configured from a plurality of verification algorithms to be selected; wherein the target verification algorithm includes using one or more of the verification algorithms to be selected;

[0077] When the storage unit in the target area of ​​the system on chip is in an idle state during operation, the storage unit is verified using the target verification algorithm to obtain a second verification result; and the second verification result is sent to the second result processing unit.

[0078] The check algorithms to be selected here include ECC check, parity check and CRC check. For example, ECC (Error Checking and Correcting) check: a code encrypted with data is stored in an extra bit on the data bit. When the data is written into the memory, the corresponding ECC code is also saved at the same time. When the data just stored is read back, the saved ECC code will be compared with the ECC code generated when the data is read. If the two ECC check bits are inconsistent, an alarm will be issued. In addition, ECC check also has error correction capabilities. When the ECC check adopts the "correct one and check two" algorithm, an alarm accumulation and correction function is performed for 1bit errors, and an alarm is issued for 2bit errors; when the ECC check adopts the "correct two and check three" algorithm, an alarm accumulation and correction function is performed for 1 / 2bit errors, and an alarm is issued for 3bit errors.

[0079] Parity Check: It is a method to check the correctness of code transmission. It is checked based on whether the number of "1" in the digits of a set of binary codes being transmitted is odd or even. The use of an odd number is called odd parity, and vice versa, it is called even parity. The type of parity to be used is predetermined. Usually, a parity check bit is specially set to make the number of "1" in this set of codes odd or even. If odd parity is used, when the receiving end receives this set of codes, it checks whether the number of "1" is an odd number, thereby determining the correctness of the transmitted code.

[0080] CRC (Cyclic Redundancy Check) is a fast algorithm that generates a short fixed-bit check code based on network data packets or computer files. It is mainly used to detect or check errors that may occur after data transmission or storage. CRC uses the principle of division and remainder to realize the function of error detection. It has the advantages of clear principle and simple implementation.

[0081] The target check algorithm here can be ECC check, the target check algorithm can be parity check, the target check algorithm can be CRC check, the target check algorithm can be ECC check and CRC check, the target check algorithm can be ECC check and parity check, the target check algorithm can be ECC check, parity check and CRC check, etc.

[0082] Figure 6 A flow chart of a storage detection method provided by an embodiment of the present application is shown, wherein the method acts on a storage detection circuit, wherein the storage detection circuit comprises: a first-stage detection circuit, a second-stage detection circuit and an abnormality processing circuit; wherein the first-stage detection circuit is connected to the abnormality processing circuit, and the second-stage detection circuit is connected to the abnormality processing circuit; comprising steps S101-S103; specifically:

[0083] S101, the first stage detection circuit detects the on-chip system storage unit in the first stage to obtain a first detection result; and sends the first detection result to the abnormality processing circuit;

[0084] S102, the second stage detection circuit detects the system-on-chip storage unit in the second stage to obtain a second detection result; and sends the second detection result to the exception processing circuit;

[0085] S103: The exception processing circuit processes the first detection result and the second detection result to obtain a processing result of the system on chip.

[0086] The first-stage detection circuit is a power-on self-test circuit; the first-stage detection circuit detects the on-chip system storage unit in the first stage to obtain a first detection result; and sends the first detection result to the abnormality processing circuit, including:

[0087] The power-on self-test circuit detects storage units in all areas of the on-chip system in the power-on stage to obtain a first test result; and sends the first test result to the abnormality processing circuit.

[0088] The power-on self-check circuit comprises: a power-on circuit, a storage verification unit and a first result processing unit; wherein the power-on circuit is connected to the storage verification unit, and the storage verification unit is connected to the first result processing unit;

[0089] The power-on circuit performs power-on detection on the system on chip to obtain a connection status of the system on chip; and sends the connection status of the system on chip to a storage verification unit;

[0090] When the connection state of the system on chip is in the power-on stage, the storage verification unit verifies the storage unit using a preset verification algorithm to obtain a first verification result; and sends the first verification result to the first result processing unit;

[0091] The first result processing unit determines a corresponding result processing method according to the first verification result.

[0092] The second stage detection circuit is an idle detection circuit; the second stage detection circuit detects the system-on-chip storage unit in the second stage to obtain a second detection result; and sends the second detection result to the exception processing circuit, including:

[0093] The idle detection circuit detects the storage unit of the target area of ​​the system on chip that is in an idle state during operation to obtain a second detection result; and sends the second detection result to the exception processing circuit.

[0094] The idle time detection circuit comprises: a bus application unit, a storage area detection unit and a second result processing unit; wherein the bus application unit is connected to the storage area detection unit, and the storage area detection unit is connected to the second result processing unit;

[0095] The bus application unit configures the address range of the target area;

[0096] When the storage unit in the target area of ​​the system on chip is in an idle state during operation, the storage area detection unit verifies the storage unit using a preset verification algorithm to obtain a second verification result; and sends the second verification result to the second result processing unit;

[0097] The second result processing unit determines a corresponding result processing method according to the second verification result.

[0098] The storage area detection unit is used to verify the storage unit using a preset verification algorithm when the storage unit in the target area of ​​the system on chip is in an idle state during operation, to obtain a second verification result; and send the second verification result to the second result processing unit, including:

[0099] According to the detection requirements, configure the starting address and the ending address of the target area;

[0100] According to the detection accuracy, a target verification algorithm is configured from a plurality of verification algorithms to be selected; wherein the target verification algorithm includes using one or more of the verification algorithms to be selected;

[0101] When the storage unit in the target area of ​​the system on chip is in an idle state during operation, the storage unit is verified using the target verification algorithm to obtain a second verification result; and the second verification result is sent to the second result processing unit.

[0102] The storage unit includes a first subunit and a second subunit;

[0103] When the storage unit in the target area of ​​the system on chip is in an idle state during operation, the storage area detection unit verifies the storage unit using a preset verification algorithm to obtain a second verification result; and sends the second verification result to the second result processing unit, including:

[0104] When the storage unit in the target area of ​​the system on chip is in an idle state during operation, using a preset verification algorithm to verify the first sub-unit and the second sub-unit respectively to obtain a first sub-result and a second sub-result;

[0105] The second verification result is obtained according to the first sub-result and the second sub-result; and the second verification result is sent to the second result processing unit.

[0106] like Figure 7 As shown, an embodiment of the present application provides an electronic device for executing the storage detection method in the present application, the device includes a memory, a processor, a bus, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the storage detection method when executing the computer program.

[0107] Specifically, the above-mentioned memory and processor may be general-purpose memory and processor, which are not specifically limited here. When the processor runs the computer program stored in the memory, the above-mentioned storage detection method can be executed.

[0108] Corresponding to the storage detection method in the present application, an embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned storage detection method are executed.

[0109] Specifically, the storage medium can be a general storage medium, such as a mobile disk, a hard disk, etc. When the computer program on the storage medium is run, the above-mentioned storage detection method can be executed.

[0110] In the embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. The system embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of systems or units, which can be electrical, mechanical or other forms.

[0111] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0112] In addition, each functional unit in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0113] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0114] It should be noted that similar numbers and letters represent similar items in the following figures. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are only used to distinguish the description and are not to be understood as indicating or implying relative importance.

[0115] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-mentioned embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-mentioned embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application. They should all be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A storage detection circuit, characterized in that: The storage detection circuit comprises: a first-stage detection circuit, a second-stage detection circuit and an abnormality processing circuit; wherein the first-stage detection circuit is connected to the abnormality processing circuit, and the second-stage detection circuit is connected to the abnormality processing circuit; The first stage detection circuit is used to detect the on-chip system storage unit in the first stage to obtain a first detection result; and send the first detection result to the abnormality processing circuit; The second stage detection circuit is used to detect the system-on-chip storage unit in the second stage to obtain a second detection result; and send the second detection result to the exception processing circuit; The exception processing circuit is used to process the first detection result and the second detection result to obtain a processing result of the system on chip.

2. The storage detection circuit according to claim 1, characterized in that: The first stage detection circuit is a power-on self-test circuit; the first stage detection circuit is used to detect the system-on-chip storage unit in the first stage to obtain a first detection result; and sending the first detection result to the abnormality processing circuit, comprising: The power-on self-test circuit is used to test the storage units in all areas of the system on chip in the power-on stage to obtain a first test result; And send the first detection result to the abnormality processing circuit.

3. The storage detection circuit according to claim 2, characterized in that: The power-on self-check circuit comprises: a power-on circuit, a storage verification unit and a first result processing unit; wherein the power-on circuit is connected to the storage verification unit, and the storage verification unit is connected to the first result processing unit; The power-on circuit is used to perform power-on detection on the system on chip to obtain the connection status of the system on chip; and send the connection status of the system on chip to the storage verification unit; The storage verification unit is used to verify the storage unit using a preset verification algorithm when the connection state of the system on chip is in the power-on stage to obtain a first verification result; and send the first verification result to the first result processing unit; The first result processing unit is used to determine a corresponding result processing method according to the first verification result.

4. The storage detection circuit according to claim 1, characterized in that: The second stage detection circuit is an idle time detection circuit; the second stage detection circuit is used to detect the system-on-chip storage unit in the second stage to obtain a second detection result; and sending the second detection result to the abnormality processing circuit, comprising: The idle detection circuit is used to detect the storage unit of the target area of ​​the system on chip that is in an idle state during operation to obtain a second detection result; And send the second detection result to the abnormality processing circuit.

5. The storage detection circuit according to claim 4, characterized in that: The idle time detection circuit comprises: a bus application unit, a storage area detection unit and a second result processing unit; wherein the bus application unit is connected to the storage area detection unit, and the storage area detection unit is connected to the second result processing unit; The bus application unit is used to configure the address range of the target area; The storage area detection unit is used to verify the storage unit using a preset verification algorithm when the storage unit in the target area of ​​the system on chip is in an idle state during operation, to obtain a second verification result; and send the second verification result to the second result processing unit; The second result processing unit is used to determine a corresponding result processing method according to the second verification result.

6. The storage detection circuit according to claim 5, characterized in that: The storage area detection unit verifies the storage unit using a preset verification algorithm to obtain a second verification result when the storage unit used in the target area of ​​the system on chip is in an idle state during operation; and sending the second verification result to the second result processing unit, comprising: According to the detection requirements, configure the starting address and the ending address of the target area; According to the detection accuracy, a target verification algorithm is configured from a plurality of verification algorithms to be selected; wherein the target verification algorithm includes using one or more of the verification algorithms to be selected; When the storage unit in the target area of ​​the system on chip is in an idle state during operation, the storage unit is verified using the target verification algorithm to obtain a second verification result; and the second verification result is sent to the second result processing unit.

7. The storage detection circuit according to claim 5, characterized in that: The storage unit includes a first subunit and a second subunit; The storage area detection unit verifies the storage unit using a preset verification algorithm to obtain a second verification result when the storage unit used in the target area of ​​the system on chip is in an idle state during operation; and sending the second verification result to the second result processing unit, comprising: When the storage unit in the target area of ​​the system on chip is in an idle state during operation, using a preset verification algorithm to verify the first sub-unit and the second sub-unit respectively to obtain a first sub-result and a second sub-result; The second verification result is obtained according to the first sub-result and the second sub-result; and the second verification result is sent to the second result processing unit.

8. A storage detection method, characterized in that: Acting on a storage detection circuit, the storage detection circuit includes: a first-stage detection circuit, a second-stage detection circuit and an abnormality processing circuit; wherein the first-stage detection circuit is connected to the abnormality processing circuit, and the second-stage detection circuit is connected to the abnormality processing circuit; the method includes: The first stage detection circuit detects the on-chip system storage unit in the first stage to obtain a first detection result; and sends the first detection result to the abnormality processing circuit; The second stage detection circuit detects the system-on-chip storage unit in the second stage to obtain a second detection result; and sends the second detection result to the exception processing circuit; The exception processing circuit processes the first detection result and the second detection result to obtain a processing result of the system on chip.

9. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of the storage detection method as described in claim 8 are performed.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the storage detection method as claimed in claim 8 are executed.

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