Storage device, test fixture and test system

Abstract

The embodiment of the invention provides a storage device, a test fixture and a test system. Wherein the storage device comprises a main circuit board and a memory controller, the main circuit board comprises a test interface, and the test interface is used for receiving first starting data; the memory controller is arranged on the main circuit board and is connected to the test interface; second starting data are stored in the memory controller; the memory controller is configured to: obtain the second boot data; when the obtaining of the second starting data fails, obtaining the first starting data through the test interface; and performing an initialization operation on the storage device according to the first boot data.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a storage device, a test fixture, and a test system. Background Art

[0002] Solid State Drive (SSD) has gradually become the mainstream of the market with its advantages of faster reading and writing speed, super strong shock resistance, extremely low power consumption, etc. And with the development of cloud computing and big data technology, solid state drives still have a very broad market prospect.

[0003] Before leaving the factory, the SSD needs to be activated, and a series of tests and debugging are required to ensure that the SSD has good storage performance, reliability and stability. Since the SSD has very sophisticated hardware and complex firmware, it is inevitable that it will not start normally in some cases, affecting the subsequent testing or debugging of the SSD. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a storage device, a test fixture, and a test system.

[0005] According to a first aspect of the present disclosure, there is provided a storage device, comprising:

[0006] A main circuit board, comprising a test interface, wherein the test interface is used to receive first startup data;

[0007] A memory controller is arranged on the main circuit board and connected to the test interface; the memory controller stores second startup data;

[0008] The memory controller is configured to: acquire the second startup data; when acquiring the second startup data fails, acquire the first startup data through the test interface; and perform an initialization operation on the storage device according to the first startup data.

[0009] In some embodiments, the memory controller is configured to:

[0010] When the acquisition of the second startup data fails, enabling the external storage device providing the first startup data based on the selection signal, generating a startup data request signal, and receiving the first startup data provided by the external storage device in response to the startup data request signal;

[0011] The test interface is further used to output the selection signal and the start data request signal.

[0012] In some embodiments, the memory controller is configured to:

[0013] Outputting a clock signal through the test interface, and sampling the first startup data based on the clock signal;

[0014] A power supply voltage and a ground voltage are provided to the external storage device through the test interface.

[0015] In some embodiments, the test interface includes a plurality of test pads;

[0016] The memory controller is connected to the plurality of test pads to output the selection signal, the start-up data request signal, the clock signal, the power supply voltage, and the ground voltage through the plurality of test pads, and to receive the first start-up data.

[0017] In some embodiments, the test interface includes:

[0018] A first test pad, connected to a power pin of the memory controller, for outputting the power voltage;

[0019] A second test pad, connected to a ground pin of the memory controller, for outputting the ground voltage;

[0020] A third test pad, connected to a chip select signal pin of the memory controller, for outputting the selection signal;

[0021] a fourth test pad connected to a clock pin of the memory controller and configured to output the clock signal;

[0022] a fifth test pad connected to a signal output pin of the memory controller and configured to output the start data request signal;

[0023] A sixth test pad is connected to a signal input pin of the memory controller and is used to receive the first startup data.

[0024] In some embodiments, the first boot data includes a read-only memory program code and a boot loader program code;

[0025] The memory controller is configured to: run a read-only memory program according to a read-only memory program code, verify the boot loader program code using the read-only memory program, and run the boot loader program according to the verified boot loader program code to complete the initialization operation.

[0026] In some embodiments, the memory controller is further configured to:

[0027] After power-on, obtaining the second startup data;

[0028] When the second startup data is successfully acquired, an initialization operation is performed on the storage device according to the second startup data.

[0029] In some embodiments, the main circuit board includes a first surface and a second surface that are oppositely disposed, and the memory controller is disposed on the first surface of the main circuit board;

[0030] The test interface is arranged on the first surface or the second surface of the main circuit board.

[0031] In some embodiments, the storage device further comprises: an input / output connector disposed at one end of the main circuit board, the test interface being located between the memory controller and the input / output connector;

[0032] The storage device also includes:

[0033] The non-volatile memory is arranged on the first surface of the main circuit board and is located at a side of the memory controller away from the input / output connector.

[0034] In some embodiments, the processor is configured to: when acquisition of the second startup data fails, output a startup data loading failure signal through the input / output connector.

[0035] According to a second aspect of the present disclosure, a test fixture is provided, comprising:

[0036] Test substrate;

[0037] A startup data storage device is provided on the test substrate, wherein the startup data storage device stores first startup data;

[0038] A test connector is arranged on the test substrate and connected to the startup data storage device. The test connector is used to contact and connect with a test interface on the storage device.

[0039] In some embodiments, the startup data storage device includes: a read-only memory, and the first startup data is stored in the read-only memory.

[0040] In some embodiments, the test connector includes: a plurality of ejector pins, each ejector pin being used for contacting and connecting with a test pad in the test interface.

[0041] In some embodiments, the test fixture further comprises:

[0042] A signal conversion module is provided on the test substrate;

[0043] A first conversion interface, connected to the signal conversion module;

[0044] A second conversion interface is connected to the signal conversion module. The second conversion interface is used to connect to the input / output connector of the storage device. The first conversion interface is different from the second conversion interface.

[0045] In some embodiments, a switch is provided between the test connector and the startup data storage device;

[0046] After the storage device outputs a startup data loading failure signal, the switch is closed to enable the startup data storage device.

[0047] According to a third aspect of the present disclosure, there is provided a test system, comprising: a test fixture and a storage device;

[0048] The test fixture comprises: a startup data storage device and a test connector arranged on a test substrate, the startup data storage device storing first startup data, and the test connector connected to the startup data storage device;

[0049] The storage device comprises: a main circuit board and a memory controller, the main circuit board comprises a test interface, the memory controller is arranged on the main circuit board and connected to the test interface, wherein the storage device is installed on the test fixture, and the test interface is in contact with the test connector.

[0050] In some embodiments, the memory controller stores second startup data;

[0051] The memory controller is configured to: obtain the second startup data, and when the acquisition of the second startup data fails, obtain the first startup data in the startup data storage device; and perform an initialization operation on the memory controller according to the first startup data.

[0052] In some embodiments, the memory controller is configured to:

[0053] When acquiring the second startup data fails, enabling the startup data storage device based on a selection signal, sending a startup data request signal to the startup data storage device, and receiving the first startup data provided by the startup data storage device in response to the startup data request signal.

[0054] In some embodiments, the test interface includes a plurality of test pads, and the memory controller is connected to the plurality of test pads;

[0055] The test connector includes a plurality of ejector pins, the startup data storage device is connected to the plurality of ejector pins, and each of the ejector pins is in contact with and connected to one of the test pads.

[0056] In some embodiments, the test interface includes:

[0057] A first test pad connected to a power pin of the memory controller and used to supply a power voltage to the startup data storage device;

[0058] a second test pad connected to a ground pin of the memory controller and used to supply a ground voltage to the startup data storage device;

[0059] A third test pad, connected to a chip select signal pin of the memory controller, for outputting the selection signal to the startup data storage device;

[0060] a fourth test pad connected to a clock pin of the memory controller and used to provide a clock signal to start the data storage device;

[0061] A fifth test pad, connected to the signal output pin of the memory controller, for outputting the startup data request signal to the startup data storage device;

[0062] The sixth test pad is connected to the signal input pin of the memory controller and is used to receive the first startup data from the startup data storage device.

[0063] The storage device provided by the embodiment of the present disclosure sets a test interface on the main circuit board to receive the first startup data provided by the external storage device, so that when the memory controller fails to obtain the second startup data stored internally, the first startup data can be used to continue to complete the initialization operation. This setting can firstly avoid the situation where the second startup data is damaged and the storage device cannot complete the initialization; secondly, the location and routing method of the test interface are more flexible, and the area of ​​the main circuit board occupied by the test interface can be smaller. These characteristics are conducive to reducing the size of the main circuit board, thereby facilitating the miniaturization of the device, and can also reduce the difficulty of layout and simplify the motherboard design.

[0064] Furthermore, the first startup data in the external storage device can be pre-programmed, and different storage devices can share the external storage device, so that the first startup data can be obtained by connecting the external storage device through the test interface, which can shorten the test cycle. In particular, when multiple storage devices cannot be initialized during the test, these storage devices can share the same external storage device, which can greatly simplify the debugging process, improve the debugging efficiency of the product, and reduce costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1A A schematic diagram of an exemplary system provided for an embodiment of the present disclosure;

[0066] Figure 1BAn architectural diagram of a memory card provided in an embodiment of the present disclosure;

[0067] Figure 1C An architectural diagram of an SSD provided in an embodiment of the present disclosure;

[0068] Figure 2 A schematic diagram of the structure of a storage device provided in an embodiment of the present disclosure;

[0069] Figure 3 A schematic diagram of the structure of another storage device provided in an embodiment of the present disclosure;

[0070] Figure 4 for Figure 3 Another partial structural schematic diagram of the storage device shown;

[0071] Figure 5 A connection diagram of a memory controller and a test interface provided in an embodiment of the present disclosure;

[0072] Figure 6 A schematic diagram of the structure of a test fixture provided in an embodiment of the present disclosure;

[0073] Figure 7 A schematic diagram of the connection between the startup data storage device and the test connector provided in an embodiment of the present disclosure;

[0074] Figure 8 A schematic diagram of a test system provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0075] The technical solution of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments.

[0076] It should be understood that spatial relationship terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0077] The terminology used herein is intended only to describe specific embodiments and is not intended to be limiting of the present disclosure. The terms "consisting of" and / or "comprising", when used in this specification, identify the presence of features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0078] It should be noted that the technical solutions described in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0079] like Figure 1A As shown, an embodiment of the present disclosure provides an exemplary system 10, which may include a host 20 and a storage device 30. The exemplary system 10 may include, but is not limited to, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory 40; the host 20 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of the electronic device.

[0080] In an embodiment of the present disclosure, the host 20 may be configured to send data to or receive data from the storage device 30. Here, the storage device 30 may include a memory controller 300 and one or more memories 40. The memory 40 may include, but is not limited to, NAND Flash Memory, 3D NAND Flash Memory, NOR Flash Memory, Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Magnetic Random Access Memory (MRAM), Phase Change Random Access Memory (PCRAM), Resistive Random Access Memory (RRAM), Nano Random Access Memory (NRAM), etc.

[0081] In one embodiment of the present disclosure, a memory controller 300 may be coupled to a memory 40 and a host 20, and used to control the memory 40. Exemplarily, the memory controller 300 may be designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 300 may also be designed to operate in a high duty cycle environment, such as an SSD or an embedded Multi-Media Card (eMMC), and the SSD or eMMC may be used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as an enterprise storage array.

[0082] In an embodiment of the present disclosure, the memory controller 300 and one or more memories 40 may be integrated into various types of storage devices, for example, included in the same package (for example, a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 30 may be implemented and packaged into different types of terminal electronic products. Figure 1B As shown, the memory controller 300 and the single memory 40 can be integrated together to form a memory card 50. The memory card 50 may include a PC card (Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC (Multi-Media Card), RS-MMC (Reduced-Size MMC), MMCmicro), an SD card (SD, miniSD, microSD, SDHC (Secure Digital High Capacity)), UFS, etc. The memory card 50 may also include a memory card 50 that connects the memory card 50 to a host (e.g., Figure 1A The host 20 in the memory card connector 51 is coupled. Figure 1C In another embodiment shown in FIG. 4 , the memory controller 300 and the plurality of memories 40 may be integrated together to form an SSD 60. The SSD 60 may also include a processor that connects the SSD 60 to a host (eg, Figure 1A In some embodiments, the storage capacity and / or operating speed of the SSD 60 is greater than the storage capacity and / or operating speed of the memory card 50.

[0083] The memory controller 300 can manage the data in the memory 40 and communicate with the host. The memory controller 300 can be configured to control operations such as reading, erasing, and programming of the memory 40; it can also be configured to manage various functions related to the data stored or to be stored in the memory 40, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc.; it can also be configured to process error correction codes (Error Checking and Correction, ECC) for data read from or written to the memory 40. In addition, the memory controller 300 can also be configured to communicate with external devices (for example, Figure 1AThe host interface controller 300 can communicate with the external host 20. Exemplarily, the host interface controller can communicate with the external host through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Development Equipment (IDE) protocol, Firewire protocol, etc. It should be understood that the memory controller 300 can also perform any other suitable functions, such as formatting the memory 40, initializing the storage device 30, etc.

[0084] In one embodiment, the startup of the storage device 30, which can also be called the initialization of the storage device 30, mainly includes two stages. The first stage is that the memory controller 300 executes the read-only memory program code (ROM Code), and the second stage is loading and executing the boot loader program code (Bootloader).

[0085] In one embodiment, the memory controller 300 may include a processor, a read-only memory (ROM) and a tightly coupled memory (TCM). For example, the tightly coupled memory may be implemented by taking a random access memory (RAM) as an example.

[0086] The ROM code is stored inside the memory controller 300. Specifically, the ROM code is fixed in the read-only memory. After the memory controller 300 is powered on, the ROM code is executed first. Generally speaking, after the memory controller 300 is powered on, the processor reads the ROM code from the fixed address stored in the read-only memory to run the read-only memory program (ROM program).

[0087] In some embodiments, the bootloader may be stored in a read-only memory.

[0088] When the processor runs the ROM program, the ROM program searches for the Bootloader file in the read-only memory and loads the Bootloader file into the tightly coupled memory. The processor runs the ROM program to verify the Bootloader file in the tightly coupled memory. After the verification is passed, the processor jumps and runs the bootloader according to the Bootloader to complete the initialization operation of the storage device.

[0089] The memory controller 300 completes the initialization of the entire system by executing the ROM code and the Bootloader. During the initialization process, the memory controller 300 performs the relevant settings of the storage device so that after the initialization is completed, the host or the card opening device can identify the storage device. At this time, the card opening device can burn the firmware program required for the storage device (e.g., SSD) to the storage device.

[0090] In view of the important role that ROM code and Bootloader play in system initialization, in order to prevent the ROM code and Bootloader inside the memory controller from being damaged, which would cause the storage device to be unable to perform initialization, in some embodiments, installation locations for external storage devices and related components can be reserved on the main circuit board of the storage device.

[0091] If during debugging, the ROM code and / or Bootloader in the memory controller 300 fails and the boot loader cannot be run, the external memory device and related components can be manually mounted, and the ROM code and / or Bootloader files can be burned in the external memory device. The memory controller 300 can retrieve the ROM code and / or Bootloader files from the external memory device to complete the system initialization, thereby debugging the storage device.

[0092] Although this method can remedy the problem that the storage device cannot be started due to an error inside the memory controller, it is time-consuming and laborious to manually mount the external storage device and related components, and after mounting, the ROM code and / or Bootloader file must be written into the external storage device, which increases the test cycle and cost. In particular, when multiple storage devices cannot be started, these operations need to be repeated many times, which greatly increases the production cycle and cost. In addition, the installation position reserved for the external storage device and related components occupies a large area of ​​the mainboard, which is not conducive to the miniaturization of the device.

[0093] Another embodiment of the present disclosure provides a storage device, which can not only solve the problem that the storage device cannot be started due to internal failure of the memory controller, but also reduce the debugging cycle and cost. Figure 2 A schematic diagram of a storage device provided in an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the storage device 30 includes:

[0094] The main circuit board includes a test interface 200, and the test interface 200 is used to receive the first startup data;

[0095] The memory controller 300 is arranged on the main circuit board and connected to the test interface 200; the memory controller 300 stores the second startup data;

[0096] The memory controller 300 is configured to: acquire the second startup data, acquire the first startup data through the test interface 200 when the acquisition of the second startup data fails; and perform an initialization operation on the storage device according to the first startup data.

[0097] Figure 3 and Figure 4 A schematic diagram of a storage device according to another embodiment of the present disclosure is provided below. Figure 3 and Figure 4 The storage device provided by the embodiment of the present disclosure is described in detail.

[0098] In the disclosed embodiment, the main circuit board 100 may be a printed circuit board (PCB), which is a support for electronic components and a carrier for the electronic components to be electrically connected to each other. The main circuit board 100 includes a first surface 101 and a second surface 102 opposite to each other. The components may be concentrated on one side of the main circuit board 100, such as the first surface 101. Alternatively, the components may be arranged on both sides of the main circuit board 100, that is, the first surface 101 and the second surface 102 of the main circuit board 100 are both provided with components.

[0099] Device pads (not shown in the figure) are provided on the surface of the main circuit board 100, and electronic components are soldered on the device pads of the main circuit board. Metal traces and guide holes are arranged on the surface and / or inside of the main circuit board, and the metal traces are connected to the device pads corresponding to different components, so that the electronic components are electrically connected to each other.

[0100] Continue to see Figure 3 and Figure 4In this embodiment, the storage device 30 includes a memory controller 300 and one or more memory devices, and the memory controller 300 and the memory device are integrated on the same main circuit board 100. The memory device may include a non-volatile memory 410, and the non-volatile memory 410 may include a NAND memory or other non-volatile memory (such as PCRAM, FRAM) included in the memory 40 as described above. By way of example, the memory controller 300 and the non-volatile memory 410 are both disposed on the first surface 101 of the main circuit board 100.

[0101] The first surface 101 of the main circuit board 100 is provided with a plurality of first device pads corresponding to the memory controller 300, and a plurality of second device pads corresponding to the memory device. The plurality of pins of the memory controller 300 are welded to the plurality of first device pads in a one-to-one correspondence, and the plurality of pins of the memory device are welded to the plurality of second device pads in a one-to-one correspondence. The first device pads and the second device pads are connected by metal traces and guide holes, thereby realizing electrical connection between the memory controller 300 and the memory device.

[0102] It should be understood that in another embodiment, the memory controller 300 and some memory devices therein may be disposed on the first side 101 of the main circuit board 100 , and other memory devices may be disposed on the second side 102 of the main circuit board 100 .

[0103] The storage device further includes an input / output connector 500, which is used to install the storage device on the host and is responsible for signal transmission between the host and the storage device. During the test process of the storage device, the input / output connector 500 is connected to the test device, and the test device sends a signal to the storage device through the input / output connector 500 to test or debug the storage device.

[0104] In some embodiments, Figure 3 As shown, the input / output connector 500 is disposed at one end of the main circuit board 100 for easy installation to the host. The memory controller 300 is disposed adjacent to the input / output connector 500 , and the nonvolatile memory 410 is disposed at one end of the memory controller 300 away from the input / output connector 500 .

[0105] In some embodiments, the input / output connector 500 in the SSD is usually a gold finger. The gold finger is used to be inserted into a corresponding slot on the host to install the SSD to the host and achieve electrical connection. The specific structure of the gold finger is determined by the interface protocol between the memory controller 300 and the host.

[0106] In addition, the storage device may further include a DRAM 420, which is connected to the memory controller 300 and is a data transfer station between the host and the memory controller 300. The data sent by the host to the storage device 30 may be first cached in the DRAM 420, and then written into the non-volatile memory 410 by the memory controller 300, that is, the provision of the DRAM 420 can improve the data transmission efficiency between the host and the storage device 30.

[0107] Continue to see Figure 3 In this embodiment, the main circuit board 100 further includes a test interface 200 , which is connected to the memory controller 300 . The test interface 200 receives the first startup data sent by the external storage device and transmits it to the memory controller 300 .

[0108] That is, in this embodiment, the device pads reserved for the external storage device and related components on the main circuit board 100 are replaced by the test interface 200, and the external storage device and related components are set on a structure outside the storage device. For example, the "external storage device and related components" can be set on the test fixture as a startup data storage device. During the test process, when the storage device fails to initialize, the test interface 200 is connected to the external startup data storage device to provide the first startup data to the memory controller 300 so that the storage device completes the system initialization.

[0109] The present disclosure does not limit the specific structure of the test interface 200. Figure 3 and Figure 4 As shown, the test interface 200 may include one or more test pads 210 (also referred to as test points). The test pads 210 may be formed at the same time as the device pads and have a similar structure. For example, the test pads may be flat metal pads.

[0110] The present disclosure does not limit the shape of the test pad 210. For example, the test pad 210 may be circular, elliptical, square, polygonal (eg, hexagonal), teardrop-shaped, or the like.

[0111] Compared with the device pad, the size, spacing and arrangement of the device pad must be consistent with the pins of the components, while the size, spacing and arrangement of the test pad 210 are more flexible, and the arrangement of multiple test pads can be adjusted according to the size of the main circuit board 100 or the layout of other components, and the size and spacing of the test pad can also be adjusted (for example, reduced). In addition, when the test pad is not involved in the test related thereto, it can be covered with solder mask ink (commonly referred to as green oil) to reduce the probability of oxidation. When it is needed, the green oil covering the test pad can be removed.

[0112] It should be understood that in some other embodiments, the test interface 200 may also be a connector commonly used for testing in the art.

[0113] In some embodiments, Figure 4 As shown, the test interface 200 and the memory controller 300 can be arranged on the same side of the main circuit board 100. That is, the test interface 200 is also arranged on the first side 101 of the main circuit board. In other embodiments, the test interface 200 and the memory controller 300 can also be arranged on two sides of the main circuit board, that is, the test interface 200 is arranged on the second side 102 of the main circuit board.

[0114] It should be understood that if the test interface 200 is a test pad, the test interface 200 can be set on any side of the main circuit board without affecting the thickness of the storage device. If the test interface 200 is a connector, the test interface 200 can be set on the same side as other components (such as the memory controller 300) to avoid increasing the thickness of the storage device.

[0115] In addition, the present disclosure does not limit the electrical connection method between the test interface 200 and the memory controller 300. Taking the test interface 200 including multiple test pads 210 as an example, the multiple test pads and the multiple first device pads corresponding to the memory controller 300 may be electrically connected one-to-one, that is, one test pad is electrically connected to one first device pad, but they may not be electrically connected one-to-one. The connection method between the multiple first device pads and the multiple test pads 210 depends on the signal interaction between the memory controller 300 and the external startup data storage device. In actual use, the connection relationship between the first device pad and the test pad 210 is set according to the signal between the memory controller 300 and the external startup data storage device.

[0116] In some embodiments, the first device pad and the test pad 210 are connected by metal traces, or metal traces and guide holes. For example, the memory controller 300 and the test pad 210 are arranged on the first side 101 of the main circuit board 100, and the first device pad and the test pad 210 can be connected by metal traces arranged on the first side 101 of the main circuit board 100. In other embodiments, the first device pad and the test pad 210 can be connected to the inner layer circuit or the second side 102 circuit of the main circuit board 100 through guide holes, and metal traces are used in the inner layer circuit or the second side 102 circuit for interconnection, so as to electrically connect the memory controller 300 and the test pad 210.

[0117] Continue to see Figure 3In the embodiment of the present disclosure, the memory controller 300 includes a processor 310 and a first memory 320. The processor 310 and the first memory 320 are integrated inside the chip of the memory controller 300, and can be considered as a processor module and a storage module inside the memory controller 300.

[0118] The first memory 320 is a memory in which data will not be lost after power failure, that is, a non-volatile memory. In this embodiment, the first memory 320 can be a read-only memory ROM, and the read-only memory ROM can include a mask read-only memory (Mask ROM, MROM), a programmable read-only memory (Programmable ROM, PROM), an erasable programmable read-only memory (Erasable Programmable ROM, EPROM), an electrically erasable programmable read-only memory (Electrically Erasable Programmable ROM, EEPROM), etc. The first memory 320 stores the second startup data. Among them, the second startup data may include a read-only memory program code ROM code and a boot loader program code Bootloader.

[0119] As described above, when the memory controller 300 is powered on, the processor 310 first obtains the ROM code from the internal first memory 320 (e.g., read-only memory) to run the ROM program, and the ROM program searches for the Bootloader file from the first memory 320 to run the bootloader to complete the initialization. That is, the memory controller 300 can complete the device initialization only after loading and executing the ROM code and the Bootloader.

[0120] If the processor 310 fails to obtain the second startup data, the processor 310 obtains the first startup data stored in the external startup data storage device through the test interface 200, and performs an initialization operation on the storage device according to the first startup data.

[0121] In some embodiments, the reason for the processor 310 failing to obtain the second startup data may be: the internal ROM program is damaged, or the boot loader is damaged, which ultimately leads to the inability to complete the initialization operation. The reason for the damage of the ROM program or the boot loader may be an error in the ROM code, or an error in the Bootloader, or the first memory 320 may be physically damaged, resulting in the inability to call out the ROM code and / or Bootloader file.

[0122] In some embodiments, the first startup data and the second startup data may be the same. That is, the first startup data also includes a read-only memory program code ROM code and a boot loader program code Bootloader. Regardless of the reason why the processor 310 fails to obtain the second startup data, the processor 310 can obtain the ROM code and / or Bootloader from an external startup data storage device as needed to complete the initialization.

[0123] For example, if the ROM program inside the memory controller 300 is damaged, resulting in failure to complete initialization, the processor 310 obtains the ROM code from the startup data storage device and then runs the ROM program, and the ROM program obtains the Bootloader from the first memory 320. Alternatively, the processor 310 can also obtain the ROM code and the Bootloader from the startup data storage device to complete the initialization, which makes it easier to write the setting code, improves the initialization efficiency, and avoids the situation where the external startup data storage device needs to be accessed again in case the Bootloader program inside the memory controller 300 is also wrong.

[0124] As another example, if the boot loader program inside the memory controller 300 is damaged, resulting in failure to complete initialization, the ROM program may obtain the Bootloader from the startup data storage device to complete the initialization.

[0125] As another example, no matter what the reason is that causes the processor 310 to fail to obtain the second startup data, the processor 310 obtains the ROM code and the Bootloader from the external startup data storage device to complete the initialization.

[0126] In other embodiments, the first startup data may also be different from the second startup data. It should be understood that in some examples, after the processor 200 fails to obtain the second startup data, it will output a startup data loading failure signal through the input / output connector 500. The startup data loading failure signal can be presented in the form of a code on the display screen of the host computer, so the reason why the processor failed to obtain the second startup data can be known by analyzing the startup data loading failure signal, so as to prescribe the right remedy to burn the ROM code or Bootloader in the external startup data storage device. For example, the first startup data may only include Bootloader, which is used for the situation that the ROM program can run normally, but the Bootloader file cannot be called out from the first memory 320, or the called out Bootloader file is damaged and the boot loader cannot be run.

[0127] In some embodiments, the second boot data may include only a read-only memory program code ROM code, and the boot loader program code Bootloader may be stored in the non-volatile memory 410. Correspondingly, the first boot data may include ROM code. Alternatively, the first boot data may also include ROM code and Bootloader, that is, after the processor obtains ROM code from an external boot data storage device to run the ROM program, the ROM program may obtain the Bootloader file from the non-volatile memory 410 or the boot data storage device to complete initialization.

[0128] In summary, during the test process, when the memory controller 300 fails to complete initialization due to an internal fault, an external startup data storage device is enabled and connected to the test interface to provide the first startup data to the memory controller 300 to help the memory controller 300 complete initialization.

[0129] The storage device provided by the embodiment of the present disclosure adopts the test interface 200 to replace the reserved position of the external storage device and related components on the main circuit board 100. Compared with the device pads of the external storage device and related components, the position and routing method of the test interface 200 are more flexible, and the area occupied by the test interface 200 on the main circuit board can be smaller. These characteristics are conducive to reducing the size of the main circuit board 100, thereby facilitating the miniaturization of the device, and can also reduce the layout difficulty and shorten the design cycle.

[0130] Furthermore, the external storage device and related components are arranged outside the storage device, and are electrically connected to the memory controller 300 through the test interface 200, so there is no need to mount the external storage device and related components on the storage device, thereby shortening the test cycle. In particular, when multiple storage devices cannot be initialized during the test, these storage devices can be connected to the same startup data storage device to obtain the first startup data, without having to mount the chip on each storage device and write the first startup data. That is, after writing the first startup data to the external storage device once, it can be applied to multiple storage devices, without repeating the process of mounting the chip on the faulty storage device and writing the first startup data, thereby greatly simplifying the debugging process and improving the debugging efficiency of the product.

[0131] In some embodiments, the processor 310 of the memory controller 300 is configured to:

[0132] When the acquisition of the second startup data fails, enabling the external storage device providing the first startup data based on the selection signal, generating a startup data request signal, and receiving the first startup data provided by the external storage device in response to the startup data request signal;

[0133] The test interface 200 is further used to output a selection signal and a start data request signal.

[0134] The select signal is also called a chip select enable signal. The memory controller 300 includes a plurality of chip select pins, which can lead out a plurality of chip select enable signal lines to the outside and connect to a plurality of chips respectively. The chip select enable signal is usually controlled by a master device (here, the memory controller 300). For example, the chip select enable signal is low level effective. When the memory controller 300 accesses a chip, the chip select pin connected to the chip is pulled down to select the chip.

[0135] In this embodiment, Figure 5 As shown, a chip select pin SPI CS (Serial Peripheral Interface Chip Select) of the memory controller 300 is connected to the test interface 200. When the processor 310 fails to obtain the second startup data, the memory controller 300 changes the level of the chip select pin SPI CS from high to low, that is, changes the selection signal from high level to low level, so as to select the external startup data storage device, that is, to start the data storage device.

[0136] The memory controller 300 also includes: a master output / slave input (MOSI) pin connected to the test interface. The MOSI pin (also referred to as the signal output pin herein) is used by the master device to send a signal or data to the slave device. In this embodiment, the memory controller 300 sends a startup data request signal to the startup data storage device through the MOSI pin and the test interface 200 to request to obtain the first startup data.

[0137] The memory controller 300 also includes: a master input / slave output (Master Input Slave Output, MISO) pin connected to the test interface. The MISO pin (also referred to as the signal input pin herein) is used for the master device to receive data sent by the slave device. After receiving the startup data request signal sent by the memory controller 300, the external startup data storage device provides the first startup data in response to the startup data request signal, and the first startup data is sent to the memory controller 300 via the test interface 200 and the MISO pin.

[0138] In some embodiments, the memory controller 300 is further configured to:

[0139] Outputting a clock signal through the test interface 200, and sampling first startup data based on the clock signal;

[0140] A power supply voltage and a ground voltage are provided to the external memory device through the test interface 200 .

[0141] The clock signal is generated by the memory controller 300 and is used to synchronize the timing of data transmission. Correspondingly, the memory controller also includes: a clock pin SPI CLK connected to the test interface. The memory controller sends a clock signal to the external startup data storage device via the clock pin and the test interface 200 to control the timing of data transmission.

[0142] When the memory controller 300 starts communicating with the external startup data storage device, the memory controller 300 pulls down the selection signal of the connection test interface 200 to enable the startup data storage device. Then, the memory controller 300 sends a clock signal to the startup data storage device through the clock pin SPI CLK, and sends a startup data request signal through the MOSI pin. After receiving the startup data request signal, the startup data storage device sends the first startup data to the memory controller 300 through the MISO pin according to the clock signal sent by the memory controller 300. After the communication is completed, the memory controller 300 pulls up the selection signal from a low level to release the external startup data storage device.

[0143] In some embodiments, the external boot data storage device is powered by the memory controller 300 during the communication process with the memory controller 300. Correspondingly, the memory controller 300 also includes a power pin SPI VCC and a ground pin GND, and both the power pin SPI VCC and the ground pin GND are connected to the test interface 200. During the communication process between the memory controller 300 and the boot data storage device, the memory controller 300 provides power to the boot data storage device via the power pin SPI VCC and the test interface 200, and provides a reference ground to the boot data storage device via the ground pin GND and the test interface 200, so that the boot data storage device can work.

[0144] It should be understood that in some other embodiments, other devices may also provide power and reference ground to the startup data storage device. For example, a test device, such as a host computer, may provide power and reference ground to the startup data storage device. Alternatively, the startup data storage device may be equipped with a power module for separate power supply.

[0145] As described above, the test interface 200 may include a plurality of test pads 210. A plurality of pins of the memory controller 300 may be connected to the plurality of test pads 210 in a one-to-one correspondence to output a selection signal, a start data request signal, a clock signal, a power supply voltage and a ground voltage through the plurality of test pads 210, and receive the first start data.

[0146] In some embodiments, Figure 5As shown, corresponding to the signal interaction between the memory controller 300 and the external boot data storage device, the test interface 200 may include:

[0147] A first test pad 211 is connected to a power pin SPI VCC of the memory controller and is used to output a power supply voltage;

[0148] A second test pad 212 is connected to a ground pin GND of the memory controller and is used to output a ground voltage;

[0149] The third test pad 213 is connected to the chip selection signal pin SPI CS of the memory controller and is used to output a selection signal;

[0150] The fourth test pad 214 is connected to the clock pin SPI CLK of the memory controller and is used to output a clock signal;

[0151] A fifth test pad 215, connected to the MOSI pin of the memory controller, for outputting a start data request signal;

[0152] The sixth test pad 216 is connected to the MISO pin of the memory controller and is used to receive the first startup data.

[0153] Here, the first test pad 211, the second test pad 212, the third test pad 213, the fourth test pad 214, the fifth test pad 215 and the sixth test pad 216 all belong to the test pad 210. The present disclosure does not limit the arrangement of the above six test pads. Figure 2 As shown, the six test pads can be arranged in a 2×3 array. Alternatively, the six test pads can also be arranged in a 3×2 array. Alternatively, the six test pads can be arranged in a row or a column. The six test pads can be arranged in any form according to the layout and routing requirements.

[0154] In some embodiments, see Figure 4 The memory controller 300 further includes a second memory 330 connected to the test interface 200 and the processor 310 , and the second memory 330 is configured to receive and store at least part of the first startup data.

[0155] For example, the second memory 330 may be a random access memory RAM, and the second memory 330 may be defined as a tightly coupled memory TCM. In some embodiments, the processor 310 directly obtains the ROM code from an external boot data storage device to run the ROM program, and the second memory 330 may at least be used to receive and store the boot loader code Bootloader. In some embodiments, the second memory 330 may be configured to receive and store the ROM code and Bootloader, and the processor 310 obtains the first boot data from the second memory 330 to complete the initialization.

[0156] In some embodiments, the memory controller 300 is configured to automatically obtain the first startup data from the external storage device when the memory controller 300 fails to obtain the second startup data. That is, after the memory controller 300 fails to obtain the second startup data, it will default to obtaining the first startup data from the external startup data storage device.

[0157] The following is a detailed description of the process of completing initialization of a memory controller 300 using a specific embodiment. Specifically,

[0158] After the processor 310 detects that the memory controller 300 is powered, the processor 310 reads the ROM code from the fixed address stored in the first memory 320 (read-only memory) to run the ROM program. Then, the ROM program searches for the Bootloader file in the first memory 320 and loads the Bootloader file into the second memory 330 (tightly coupled memory). The processor 310 runs the ROM program to verify the bootloader file in the second memory 330. After the verification is passed, the processor 310 jumps and executes the Bootloader file, that is, runs the boot loader, and completes the initialization operation.

[0159] If the ROM program and / or the Bootloader program fails and the initialization cannot be completed, the memory controller 300 will send a startup data failure signal to the test device through the input / output connector, and will pull down the chip select pin SPI CS connected to the test interface 200 by default to select the external startup data storage device. After that, the memory controller 300 sends a clock signal to the startup data storage device through the clock pin SPI CLK, and at the same time sends a startup data request signal through the MOSI pin, and supplies power to the startup data storage device through the power pin SPI VCC and the ground pin GND. After receiving the startup data request signal, the external startup data storage device sends the first startup data to the memory controller 300 through the MISO pin according to the clock signal sent by the memory controller 300. The first startup data can be stored in the second memory 330 of the memory controller 300.

[0160] After the communication is completed, the memory controller 300 pulls the selection signal from low level to high level to release the external startup data storage device. The memory controller 300 is initialized according to the first startup data in the second memory 330.

[0161] The embodiment of the present disclosure also provides a test fixture for testing or debugging the storage device 30 . Figure 6 A schematic diagram of the structure of a test fixture provided in an embodiment of the present disclosure is shown in FIG. Figure 6 As shown, the test fixture 70 includes: a test substrate 610, and a first conversion interface 630, a second conversion interface 640 and a signal conversion module 620 arranged on the test substrate 610, the signal conversion module 620 is connected to the first conversion interface 630 and the second conversion interface 640 respectively, wherein the first conversion interface 630 is used to connect to the host computer, the second conversion interface 640 is used to connect to the input / output connector 500 of the storage device, the first conversion interface 630 is different from the second conversion interface 640, and the signal conversion module 620 is used to convert the signal of the first conversion interface 630 and the signal of the second conversion interface 640.

[0162] The input / output connector 500 in the above storage device usually complies with the PCIe protocol or the SATA protocol, and the input / output connector 500 can be presented in the form of a gold finger. The host computer is usually a computer, which uses a USB interface for communication. That is, the input / output connector 500 in the storage device and the USB interface of the host computer have different interface types and cannot be directly plugged in. Therefore, a conversion interface and a signal conversion module 620 are required to realize the connection and signal transmission between the storage device and the host computer.

[0163] In some embodiments, the first conversion interface 630 may be a USB plug, and the USB connector is used to be inserted into a USB interface of a host computer.

[0164] According to the interface protocol followed by the storage device, the second conversion interface 640 may be a PCIe interface or a SATA interface, and the specific structure of the PCIe interface or the SATA interface may be a slot. The gold finger of the storage device may be inserted into the slot of the test fixture.

[0165] In some embodiments, the signal conversion module 620 converts the signal of the first conversion interface 630 and the signal of the second conversion interface 640 according to the PCIe protocol (or SATA protocol) and the USB protocol. In addition, a power conversion module may be provided on the test substrate 610, connecting the first conversion interface 630 and the signal conversion module 620, and used to increase the power supply voltage that meets the requirements of the storage device. For example, the power conversion module is used to convert the 5V voltage received by the first conversion interface 630 (USB plug) into a 3.3V voltage.

[0166] In the embodiment of the present disclosure, the test substrate 610 may be a printed circuit board. The test substrate 610 is provided with metal traces and guide holes for connecting the first conversion interface 630 , the second conversion interface 640 and the signal conversion module 620 .

[0167] Continue to see Figure 6 In this embodiment, further, a startup data storage device 700 and a test connector 800 are provided on the test fixture 70. Specifically, the test fixture further includes:

[0168] A startup data storage device 700 is disposed on the test substrate 610, and the startup data storage device 700 stores first startup data;

[0169] The test connector 800 is disposed on the test substrate 610 and connected to the boot data storage device 700 . The test connector 800 is used to contact and connect with the test interface 200 on the storage device.

[0170] The startup data storage device 700 includes a non-volatile memory. The non-volatile memory may be a read-only memory ROM, and the read-only memory ROM may include a programmable read-only memory PROM, an erasable programmable read-only memory EPROM, an electrically erasable programmable read-only memory EEPROM, etc. The non-volatile memory may also be a NAND memory, a phase change random access memory PCRAM, a ferroelectric random access memory FRAM, etc. In this embodiment, the startup data storage device 700 includes an EEPROM. In addition, the startup data storage device 700 may also include some related components that enable the EEPROM to work normally.

[0171] The first startup data is stored in the startup data storage device 700. As shown above, the first startup data may include a read-only memory program code ROM code and a boot loader program code Bootloader. It should be understood that in actual use, the first startup data can be burned into the startup data storage device 700 according to a failure of the storage device or according to demand.

[0172] The test connector 800 is disposed on the test substrate 610 and connected to the boot data storage device 700. The test connector 800 is disposed corresponding to the test interface 200 on the storage device, and the test connector 800 is used to make physical contact with the test interface 200.

[0173] In some embodiments, when the test interface 200 includes a plurality of test pads 210, the test connector 800 may include a plurality of ejector pins 810. The number of ejector pins is equal to the number of test pads. The arrangement of the plurality of ejector pins and the spacing between adjacent ejector pins are equal to the arrangement of the plurality of test pads and the spacing between adjacent test pads, so that each ejector pin can be in contact with a test pad.

[0174] In the above embodiment of the present disclosure, the test interface 200 includes six test pads 210 (211 to 216), and correspondingly, the test connector 800 may include six ejector pins 810, each of which is connected to a test pad 210. Figure 7 As shown, the test connector 800 includes:

[0175] A first ejector pin 811 is connected to a power pin SPI VCC' of the EEPROM 710. The first ejector pin is used to contact and connect with the first test pad 211. The power pin SPI VCC' of the EEPROM is used to receive a power voltage provided by a memory controller.

[0176] A second ejector pin 812 is connected to a ground pin GND' of the EEPROM. The second ejector pin is used to contact and connect with the second test pad 212. The ground pin GND' of the EEPROM is used to receive a ground voltage provided by the memory controller.

[0177] The third ejector pin 813 is connected to the chip select signal pin SPI CS' of the EEPROM. The third ejector pin is used to contact and connect with the third test pad 213. The chip select signal pin SPI CS' of the EEPROM is used to receive a selection signal from the memory controller.

[0178] A fourth ejector pin 814 is connected to a clock pin SPI CK' of the EEPROM. The fourth ejector pin is used to contact and connect with the fourth test pad 214. The clock pin SPI CK' of the EEPROM is used to receive a clock signal provided by the memory controller.

[0179] A fifth ejector pin 815 is connected to a signal input pin MISO' of the EEPROM. The fifth ejector pin is used to contact and connect with the fifth test pad 215. The signal input pin MISO' of the EEPROM is used to receive a start data request signal provided by the memory controller.

[0180] The sixth ejector pin 816 is connected to the signal output pin MOSI' of the EEPROM. The sixth ejector pin is used to contact and connect with the sixth test pad 216. The signal output pin MOSI' of the EEPROM is used to output the first startup data to the memory controller.

[0181] Here, the first ejector pin 811, the second ejector pin 812, the third ejector pin 813, the fourth ejector pin 814, the fifth ejector pin 815 and the sixth ejector pin 816 are all ejector pins 810. For example, the ejector pin 810 may be a spring ejector pin, so that the ejector pin can abut against the test pad to improve the connection reliability between the ejector pin and the test pad.

[0182] For example, the ejector pin 810 is soldered on the test substrate 610. For example, the ejector pin 810 can be mounted on the test substrate 610 by using SMT (Surface Mounted Technology) or soldered on the test substrate 610 by using a wave soldering process.

[0183] It should be understood that when the test interface 200 on the storage device is a connector, the test connector 800 on the test fixture should be a connector that matches the connector.

[0184] During the test process (e.g., the card opening process), when the input / output connector 500 of the storage device is inserted into the second adapter interface 640 on the test fixture, the test connector 800 on the test fixture is in physical contact with the test interface 200 of the storage device, so that the line between the memory controller 300 and the boot data storage device 700 is connected. After the test starts, the host computer supplies power to the memory controller 300, and the memory controller 300 starts to obtain the internal second startup data for initialization. If the memory controller 300 fails to obtain the second startup data, the memory controller 300 supplies power to the boot data storage device 700 based on the link of the test interface 200 and the test connector 800, and sends a selection signal, a startup data request signal and a clock signal to it to obtain the first startup data from the boot data storage device 700, and initialize based on the first startup data. After the storage device completes the initialization, the test device (e.g., the card opening device) burns the firmware to the storage device through the host computer to complete the card opening of the storage device.

[0185] In some embodiments, when the memory controller 300 fails to obtain the second startup data, the memory controller will default to obtaining the first startup data from the startup data storage device 700. That is, the memory controller can select the startup data storage device 700 and obtain the first startup data without waiting for instructions.

[0186] In some embodiments, when the memory controller 300 fails to obtain the second startup data, the memory controller 300 will also send a startup data loading failure signal to the host computer through the input / output connector 500. The startup data loading failure signal can present the process of the memory controller failing to obtain the second startup data in the form of code. The tester can determine the reason why the memory controller 300 cannot initialize the device based on the startup data loading failure signal displayed on the host computer display.

[0187] For example, the memory controller 300 can automatically obtain the first startup data from the startup data storage device 700 for initialization while sending the second startup data loading failure signal to the host computer. The advantage of this setting is that the storage device initialization process will not be interrupted, which can speed up the test efficiency.

[0188] In other embodiments, the memory controller 300 is not allowed to obtain the first startup data from the startup data storage device 700 on its own. For example, after the memory controller 300 sends a startup data loading failure signal to the host computer, the host computer or the human control of the memory controller 300 is required to obtain the first startup data from the startup data storage device. This arrangement can provide the first startup data after the cause of the failure of the memory controller 300 is clearly determined.

[0189] In some embodiments, the host computer may send an instruction to the memory controller 300 through software, instructing the memory controller 300 to obtain the first startup data from the startup data storage device.

[0190] In other embodiments, a switch 720 is provided between the test connector 800 and the storage device; after the host computer receives the startup data loading failure signal output by the storage device, the switch 720 is closed to enable the startup data storage device 700. Afterwards, the memory controller can obtain the first startup data from the startup data storage device 700. By way of example, the switch 720 can be closed manually, or the host computer can control the closing of the switch 720. By way of example, the switch 720 can be set between any pin of the startup data storage device 700 and a pin 810. For example, the switch 720 can be set between the power pin SPIVCC' and the first pin of the EEPROM, or the switch 720 can be set between the signal input pin MISO' and the fifth pin of the EEPROM.

[0191] In some embodiments, if the memory controller 300 fails to obtain the second startup data, after the memory controller 300 completes initialization according to the first startup data, that is, after the storage device 30 is started, the ROM code and / or Bootloader can be re-burned into the first memory 320 according to the fault information of the second startup data displayed by the startup data loading failure signal, so as to ensure that if the storage device needs to be re-initialized later (including after leaving the factory), it can be initialized according to the second startup data in the memory controller 300. By way of example, the first memory 320 may include PROM, EPROM, and EEPROM.

[0192] In the disclosed embodiment, a startup data storage device and a test connector are provided on the test fixture. After the first startup data is written to the startup data storage device once, it can be applied to multiple storage devices, which can greatly improve the test efficiency. Moreover, test interfaces can be reserved at the same position on storage devices of different models, so the test fixture can be applied to more storage devices, that is, the test interfaces of different products can be set at the same coordinate position, so multiple projects can share a set of test fixtures, reducing the test cost.

[0193] It should be understood that in some embodiments, a startup data storage device and a test connector can be newly added to the original test fixture (such as a card opening fixture) to use a test fixture to complete the initialization of the storage device and the card opening. By way of example, the test fixture provided in the present disclosure is a card opening fixture, and the card opening device includes a host computer and a card opening fixture, and the card opening fixture is connected to the host computer and the storage device. In this embodiment, after the storage device is powered on, the storage device is initialized first. After the initialization is completed, the host computer is used to burn the firmware (Firmware, FW) program required for the operation of the solid-state hard disk to the storage device to complete the card opening of the storage device.

[0194] In other embodiments, a test fixture may be provided to install the startup data storage device and the test connector, so that when the memory controller cannot be initialized due to failure to obtain the second startup data, the test fixture can be used to perform initialization.

[0195] The present disclosure also provides a testing system. Figure 8 A schematic diagram of a test system provided in an embodiment of the present disclosure, such as Figure 8 As shown, the test system 80 includes: a test fixture 70 and a storage device 30;

[0196] The test fixture 70 includes: a startup data storage device 700 and a test connector 800 disposed on the test substrate 610, the startup data storage device 700 stores first startup data, and the test connector 800 is connected to the startup data storage device 700;

[0197] The storage device 30 includes: a main circuit board and a memory controller 300, the main circuit board includes a test interface 200, the memory controller 300 is arranged on the main circuit board and connected to the test interface 200, wherein the storage device 30 is installed on a test fixture 70, and the test interface 200 is in contact with a test connector 800.

[0198] Furthermore, the test system 90 also includes a host computer 900, and the host computer 900 and the test fixture 70 belong to the test equipment. In this embodiment, the test equipment can be a card opening device, the host computer 900 is also used to burn firmware to the storage device 30, and the test fixture 70 is a card opening fixture.

[0199] Continue to see Figure 8 The test fixture 70 further includes: a first conversion interface 630 and a second conversion interface 640, both of which are connected to the signal conversion module 620, wherein the first conversion interface 630 is connected to the host computer 900, and can communicate using the USB protocol, and the second conversion interface 640 is connected to the input / output connector 500 on the storage device 30, and can communicate using the PCIe protocol or the SATA protocol. For example, the firmware program code output by the host computer 900 is sent to the storage device 30 via the first conversion interface 630, the signal conversion module 620, and the second conversion interface 640.

[0200] Further, the memory controller 300 includes: a first memory and a processor connected to the first memory, wherein the first memory stores second startup data, and the processor is configured to: obtain the second startup data in the first memory; when the acquisition of the second startup data fails, obtain the first startup data in the startup data storage device 700 via the test interface 200 and the test connector 800; and perform an initialization operation on the storage device 30 according to the first startup data.

[0201] For example, the memory controller 300 is configured to: when the acquisition of the second startup data fails, select the startup data storage device 700 in the test fixture based on the selection signal, and supply power to the startup data storage device 700; then, send a clock signal and a startup data request signal to the startup data storage device 700, and then, based on the clock signal, sample the first startup data provided by the startup data storage device 700 in response to the startup data request signal. Finally, perform an initialization operation on the memory controller 300 according to the first startup data.

[0202] In some embodiments, the test interface 200 may include a plurality of test pads, and the memory controller 300 is connected to each test pad;

[0203] The test connector 800 includes a plurality of ejector pins, each of which is connected to the startup data storage device 700 , and each of which is contact-connected to a test pad to form a conductive line between the memory controller 300 and the startup data storage device 700 .

[0204] The connection relationship between the plurality of test pads and the pins of the memory controller 300 , and the connection relationship between the plurality of eject pins and the test pads and the pins of the startup data storage device 700 can be referred to above and will not be described in detail here.

[0205] In the test system provided by the embodiment of the present disclosure, a startup data storage device for providing the first startup data is set on the test fixture. When the memory controller in the storage device fails to obtain the second startup data inside it and cannot complete the system initialization, the startup data storage device on the test fixture is enabled to provide the first startup data to the memory controller. In this embodiment, the test interface replaces the installation position reserved for the external storage device and related components on the storage device. First, there is basically no effect on the layout of other devices on the storage device, and the test interface has a smaller occupied area and a more flexible routing method, which simplifies the design of the main circuit board and is conducive to the miniaturization of the device. And when there is a problem with the initialization, there is no need to manually weld the external storage device and related components, and there is no need to burn the first startup data into the external storage device, which greatly improves the debugging efficiency. Furthermore, storage devices of different models can reserve test interfaces at the same position and uniformly manufacture test fixtures. That is, several test fixtures 70 are invested at a time, and each project can use the test fixture, saving the test cost.

[0206] The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The above description is only a specific implementation method of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, which should be covered by the protection scope of the present disclosure.

Claims

1. A storage device, characterized in that: include: A main circuit board, comprising a test interface, wherein the test interface is used to receive first startup data; A memory controller, arranged on the main circuit board and connected to the test interface; The memory controller stores second startup data; The memory controller is configured to: acquire the second startup data; when acquiring the second startup data fails, acquire the first startup data through the test interface; and perform an initialization operation on the storage device according to the first startup data.

2. The storage device according to claim 1, characterized in that The memory controller is configured to: When the acquisition of the second startup data fails, enabling the external storage device providing the first startup data based on the selection signal, generating a startup data request signal, and receiving the first startup data provided by the external storage device in response to the startup data request signal; The test interface is further used to output the selection signal and the start data request signal.

3. The storage device according to claim 2, characterized in that: The memory controller is configured to: Outputting a clock signal through the test interface, and sampling the first startup data based on the clock signal; A power supply voltage and a ground voltage are provided to the external storage device through the test interface.

4. The storage device according to claim 3, characterized in that: The test interface includes a plurality of test pads; The memory controller is connected to the plurality of test pads to output the selection signal, the start-up data request signal, the clock signal, the power supply voltage, and the ground voltage through the plurality of test pads, and to receive the first start-up data.

5. The storage device according to claim 4, characterized in that: The test interface includes: A first test pad, connected to a power pin of the memory controller, for outputting the power voltage; A second test pad, connected to a ground pin of the memory controller, for outputting the ground voltage; A third test pad, connected to a chip select signal pin of the memory controller, for outputting the selection signal; a fourth test pad connected to a clock pin of the memory controller and configured to output the clock signal; a fifth test pad connected to a signal output pin of the memory controller and configured to output the start data request signal; A sixth test pad is connected to a signal input pin of the memory controller and is used to receive the first startup data.

6. The storage device according to claim 1, characterized in that: The first startup data includes a read-only memory program code and a boot loader program code; The memory controller is configured to: run a read-only memory program according to a read-only memory program code, verify the boot loader program code using the read-only memory program, and run the boot loader program according to the verified boot loader program code to complete the initialization operation.

7. The storage device according to claim 1, characterized in that: The memory controller is further configured to: After power-on, obtaining the second startup data; When the second startup data is successfully acquired, an initialization operation is performed on the storage device according to the second startup data.

8. The storage device according to claim 1, characterized in that: The main circuit board comprises a first surface and a second surface which are arranged opposite to each other, and the memory controller is arranged on the first surface of the main circuit board; The test interface is arranged on the first surface or the second surface of the main circuit board.

9. The storage device according to claim 8, characterized in that: The storage device further comprises: an input / output connector disposed at one end of the main circuit board, the test interface being located between the memory controller and the input / output connector; The storage device also includes: The non-volatile memory is arranged on the first surface of the main circuit board and is located at a side of the memory controller away from the input / output connector.

10. The storage device according to claim 9, characterized in that: The memory controller is configured to output a startup data loading failure signal through the input / output connector when acquisition of the second startup data fails.

11. A test fixture, characterized in that: include: Test substrate; A startup data storage device is provided on the test substrate, wherein the startup data storage device stores first startup data; A test connector is arranged on the test substrate and connected to the startup data storage device. The test connector is used to contact and connect with a test interface on the storage device.

12. The test fixture according to claim 11, characterized in that: The startup data storage device includes a read-only memory, and the first startup data is stored in the read-only memory.

13. The test fixture according to claim 11, characterized in that: The test connector comprises: a plurality of ejector pins, each ejector pin being used for contacting and connecting with a test pad in the test interface.

14. The test fixture according to claim 11, characterized in that: The test fixture also includes: A signal conversion module is provided on the test substrate; A first conversion interface, connected to the signal conversion module; A second conversion interface is connected to the signal conversion module. The second conversion interface is used to connect to the input / output connector of the storage device. The second conversion interface is different from the first conversion interface.

15. The test fixture according to claim 14, characterized in that: A switch is provided between the test connector and the startup data storage device; After the storage device outputs a startup data loading failure signal, the switch is closed to enable the startup data storage device.

16. A testing system, characterized in that: include: Test fixtures and storage equipment; The test fixture comprises: a startup data storage device and a test connector arranged on a test substrate, the startup data storage device storing first startup data, and the test connector connected to the startup data storage device; The storage device comprises: a main circuit board and a memory controller, the main circuit board comprises a test interface, the memory controller is arranged on the main circuit board and connected to the test interface, wherein the storage device is installed on the test fixture, and the test interface is in contact with the test connector.

17. The test system according to claim 16, characterized in that: The memory controller stores second startup data; The memory controller is configured to: obtain the second startup data, and when the acquisition of the second startup data fails, obtain the first startup data in the startup data storage device; and perform an initialization operation on the storage device according to the first startup data.

18. The test system according to claim 17, characterized in that: The memory controller is configured to: When acquiring the second startup data fails, enabling the startup data storage device based on a selection signal, sending a startup data request signal to the startup data storage device, and receiving the first startup data provided by the startup data storage device in response to the startup data request signal.

19. The test system according to claim 18, characterized in that: The test interface includes a plurality of test pads, and the memory controller is connected to the plurality of test pads; The test connector includes a plurality of ejector pins, the startup data storage device is connected to the plurality of ejector pins, and each of the ejector pins is in contact with and connected to one of the test pads.

20. The test system according to claim 19, characterized in that: The test interface includes: A first test pad connected to a power pin of the memory controller and used to supply a power voltage to the startup data storage device; a second test pad connected to a ground pin of the memory controller and used to supply a ground voltage to the startup data storage device; A third test pad, connected to a chip select signal pin of the memory controller, for outputting the selection signal to the startup data storage device; a fourth test pad connected to a clock pin of the memory controller and used to provide a clock signal to start the data storage device; A fifth test pad, connected to the signal output pin of the memory controller, for outputting the startup data request signal to the startup data storage device; The sixth test pad is connected to the signal input pin of the memory controller and is used to receive the first startup data from the startup data storage device.

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