Clamp voltage generating circuit and power supply

Abstract

The invention relates to a clamp voltage generation circuit and a power supply. The clamping voltage generation circuit comprises a PWM signal generation circuit, a positive and negative power conversion circuit and an active filtering voltage stabilizing circuit. The positive and negative power conversion circuit is electrically connected between the PWM signal generation circuit and the active filtering voltage stabilizing circuit. A PWM signal generation circuit configured to alternately output a first high potential signal and a first low potential signal; the positive and negative power conversion circuit is configured to output a first positive voltage signal at a first conversion output end under the control of the first high-potential signal, and output a first negative voltage signal at a second conversion output end under the control of the first high-potential signal; and the active filtering voltage stabilizing circuit is configured to output a second positive voltage signal at a first filtering output end according to the first positive voltage signal and output a second negative voltage signal at a second filtering output end according to the first negative voltage signal. The problem that a clamping voltage generation circuit is complex and high in cost can be solved.

Description

Technical Field

[0001] The present application relates to the field of circuit technology, and in particular to a clamping voltage generating circuit and a power supply. Background Art

[0002] In many integrated circuits and circuit units, a voltage generator (or power supply) is required to provide a stable voltage for the system. In order to prevent the voltage output by the voltage generator (power supply) from exceeding the preset voltage value, or to reduce the voltage output by the voltage generator, the output of many voltage generators is usually connected to a clamping voltage circuit. For example, the test machine mainly uses FPGA (Field Programmable Gate Array) or CPLD (Complex Programmable Logic Device). The application of FPGA and CPLD is the generation and processing of programmable digital signals. When the test machine performs an open / short test, the pass / fail voltage judgment range is + / -1.2V, and when performing a DC (Direct Current) direct current parameter test, the pass / fail voltage range is + / -4.5V. In the test machine system, an adjustable clamp voltage (clamp voltage) is required to limit the output of the drive or feedback circuit to protect the device under test (DUT) and the test system. For example, during the Open / Short test, the clamp voltage requirement is + / -2V; for example, during the DC parameter test, the clamp voltage requirement is + / -6V. If there is no clamp voltage (clamp voltage generation circuit or clamp power supply) setting, the drive or feedback circuit will output the maximum positive voltage or the maximum negative voltage, which may cause the device under test or the test system to burn out.

[0003] However, FPGA or CPLD usually does not have analog signal or analog voltage output, so it is necessary to use DAC IC (Digital to Analog Converter) digital-to-analog converter and communication transmission interface (IIC or SPI) and other related circuits to convert digital signals into analog voltages for use as clamping voltages, which complicates the control system and increases costs.

[0004] Therefore, the circuit for generating the clamping voltage in the prior art has the problems of complex circuit and high cost. Summary of the invention

[0005] Based on this, it is necessary to provide a clamping voltage generating circuit and a power supply to address the problems of complex circuits and high costs in the prior art clamping voltage generating circuit.

[0006] According to a first aspect of the present application, there is provided a clamping voltage generating circuit, comprising a PWM signal generating circuit, a positive and negative power conversion circuit and an active filtering and voltage stabilizing circuit, wherein the positive and negative power conversion circuit is electrically connected between the PWM signal generating circuit and the active filtering and voltage stabilizing circuit;

[0007] The PWM signal generating circuit is configured to alternately output a first high potential signal and a first low potential signal at an output end;

[0008] The positive-negative power conversion circuit comprises a first conversion output terminal and a second conversion output terminal, wherein the positive-negative power conversion circuit is configured to output a first positive voltage signal at the first conversion output terminal under the control of the first high potential signal, and to output a first negative voltage signal at the second conversion output terminal under the control of the first high potential signal;

[0009] The active filtering and voltage stabilizing circuit comprises a first filtering output terminal and a second filtering output terminal. The active filtering and voltage stabilizing circuit is configured to output a second positive voltage signal at the first filtering output terminal according to the first positive voltage signal, and to output a second negative voltage signal at the second filtering output terminal according to the first negative voltage signal.

[0010] In some implementations, the PWM signal generating circuit includes at least one of an FPGA and a CPLD.

[0011] In some embodiments, the positive-negative power conversion circuit includes:

[0012] A first sub-power conversion circuit comprises the first conversion output terminal, the input terminal of the first sub-power conversion circuit is connected to a first input positive voltage, and the first sub-power conversion circuit is configured to output the first positive voltage signal at the first conversion output terminal according to the first input positive voltage under the control of the first high potential signal;

[0013] The second sub-power conversion circuit includes the second conversion output terminal, the input terminal of the second sub-power conversion circuit is connected to the first input negative voltage, and the second sub-power conversion circuit is configured to output the first negative voltage signal at the second conversion output terminal according to the first input negative voltage under the control of the first high potential signal.

[0014] In some embodiments, the first sub-power conversion circuit includes an N-type transistor and a first storage capacitor, the gate of the N-type transistor is electrically connected to the output end of the PWM signal generating circuit, the first electrode of the N-type transistor is connected to the first input positive voltage, the second electrode of the N-type transistor is electrically connected to the first capacitor electrode of the first storage capacitor, the second electrode of the N-type transistor is the first conversion output end, and the second capacitor electrode of the first storage capacitor is electrically connected to the ground end;

[0015] The second sub-power conversion circuit includes a P-type transistor and a second storage capacitor, the gate of the P-type transistor is electrically connected to the output end of the PWM signal generating circuit, the first pole of the P-type transistor is connected to the first input negative voltage, the second pole of the P-type transistor is electrically connected to the first capacitor electrode of the second storage capacitor, the second pole of the P-type transistor is the second conversion output end, and the second capacitor electrode of the second storage capacitor is electrically connected to the ground end.

[0016] In some implementations, the active filtering and voltage stabilization circuit includes:

[0017] A first sub-filter voltage stabilization circuit, comprising the first filter output terminal, wherein the first sub-filter voltage stabilization circuit is configured to output a second positive voltage signal at the first filter output terminal according to the first positive voltage signal;

[0018] The second sub-filter voltage stabilizing circuit comprises the second filter output terminal, and the second sub-filter voltage stabilizing circuit is configured to output a second negative voltage signal at the second filter output terminal according to the first negative voltage signal.

[0019] In some embodiments, the first sub-filter voltage stabilization circuit includes a first operational amplifier, the first conversion output terminal is electrically connected to the non-inverting input terminal of the first operational amplifier, the inverting input terminal of the first operational amplifier is electrically connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is the first filter output terminal;

[0020] The second sub-filter voltage stabilization circuit includes a second operational amplifier, the second conversion output terminal is electrically connected to the non-inverting input terminal of the second operational amplifier, the inverting input terminal of the second operational amplifier is electrically connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is the second filter output terminal.

[0021] In some embodiments, the first sub-filter voltage stabilization circuit further includes a first capacitor, a first capacitor electrode of the first capacitor is electrically connected to the non-inverting input terminal of the first operational amplifier, and a second capacitor electrode of the first capacitor is electrically connected to the output terminal of the first operational amplifier;

[0022] The second sub-filter voltage stabilization circuit also includes a third capacitor, a first capacitor electrode of the third capacitor is electrically connected to the in-phase input terminal of the second operational amplifier, and a second capacitor electrode of the third capacitor is electrically connected to the output terminal of the second operational amplifier.

[0023] In some embodiments, the first sub-filter voltage stabilization circuit further includes a first resistor, a second resistor and a second capacitor, the first resistor and the second resistor are arranged in series between the first conversion output terminal and the non-inverting input terminal of the first operational amplifier, the first capacitor electrode of the second capacitor is electrically connected to the non-inverting input terminal of the first operational amplifier, the second capacitor electrode of the second capacitor is electrically connected to the ground terminal, and the first capacitor electrode of the first capacitor is electrically connected between the first resistor and the second resistor;

[0024] The second sub-filter voltage stabilization circuit also includes a third resistor, a fourth resistor and a fourth capacitor. The third resistor and the fourth resistor are arranged in series between the second conversion output terminal and the non-inverting input terminal of the second operational amplifier. The first capacitor electrode of the fourth capacitor is electrically connected to the non-inverting input terminal of the second operational amplifier, the second capacitor electrode of the fourth capacitor is electrically connected to the ground terminal, and the first capacitor electrode of the third capacitor is electrically connected between the third resistor and the fourth resistor.

[0025] In some embodiments, an absolute value of the first positive voltage signal and an absolute value of the first negative voltage signal are both smaller than an absolute value of the first high potential signal.

[0026] According to a second aspect of the present application, a power supply is provided, comprising any one of the clamping voltage generating circuits described above.

[0027] In an embodiment of the present application, the positive-negative power conversion circuit is electrically connected between the PWM signal generating circuit and the active filtering voltage stabilizing circuit, and the positive-negative power conversion circuit is configured to output a first positive voltage signal at a first conversion output terminal and a first negative voltage signal at a second conversion output terminal under the control of a first high potential signal, and the active filtering voltage stabilizing circuit is configured to output a second positive voltage signal at the first filter output terminal according to the first positive voltage signal, and to output a second negative voltage signal at the second filter output terminal according to the first negative voltage signal. Therefore, the embodiment of the present application only needs to set the positive-negative power conversion circuit electrically connected between the PWM signal generating circuit and the active filtering voltage stabilizing circuit to provide a clamping voltage. Therefore, the clamping voltage generating circuit of the embodiment of the present application has a simple structure, which can greatly reduce the cost of the power supply in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of the present application, the drawings required for use in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0029] Figure 1 A schematic diagram of a first structural block diagram of a clamping voltage generating circuit provided in some embodiments of the present application.

[0030] Figure 2 A schematic diagram of a second structural block diagram of a clamping voltage generating circuit provided in some embodiments of the present application.

[0031] Figure 3 A schematic diagram of a detailed circuit of a clamping voltage generating circuit provided in some embodiments of the present application.

[0032] Figure 4 A first waveform diagram of part of the signals in a clamping voltage generating circuit provided in some embodiments of the present application.

[0033] Figure 5 A second waveform diagram of part of the signals in a clamping voltage generating circuit provided in some embodiments of the present application. DETAILED DESCRIPTION

[0034] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0035] In the description of the present application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0036] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, if the term "plurality" appears, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0037] In this application, unless otherwise clearly specified and limited, if the terms "installed", "connected", "connected", "fixed" and the like appear, these terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integrated connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two components or the interaction relationship between two components, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0038] In the present application, unless otherwise clearly specified and limited, if there is a description that a first feature is "above" or "below" a second feature, etc., or similar descriptions appear, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "above" and "above" the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0039] It should be noted that if a component is referred to as being "fixed to" or "disposed on" another component, it may be directly on the other component or there may be a central component. If a component is considered to be "connected to" another component, it may be directly connected to the other component or there may be a central component at the same time. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only implementation method.

[0040] In the prior art, FPGA or CPLD usually does not have analog signal or analog voltage output, so it is necessary to use DACIC (Digital to Analog Converter) digital analog converter and communication transmission interface (IIC or SPI) and other related circuits to convert digital signals into analog voltages for use as clamping voltages, which complicates the control system and increases costs. The circuit for generating clamping voltage in the prior art has the problem of complex circuits and high costs.

[0041] Based on the above problems, the present application provides a clamping voltage generating circuit and a power supply.

[0042] Figure 1 A schematic diagram of a first structural block diagram of a clamping voltage generating circuit provided in some embodiments of the present application. Figure 2 A schematic diagram of a second structural block diagram of a clamping voltage generating circuit provided in some embodiments of the present application. Figure 3 A schematic diagram of a detailed circuit of a clamping voltage generating circuit provided in some embodiments of the present application. Figure 4 A first waveform diagram of part of the signals in a clamping voltage generating circuit provided in some embodiments of the present application. Figure 5 A second waveform diagram of part of the signals in a clamping voltage generating circuit provided in some embodiments of the present application.

[0043] First, see Figures 1 to 5 The present application provides a clamping voltage generating circuit 100, the clamping voltage generating circuit 100 includes a PWM signal generating circuit 10, a positive and negative power conversion circuit 20 and an active filtering and voltage stabilizing circuit 30, and the positive and negative power conversion circuit 20 is electrically connected between the PWM signal generating circuit 10 and the active filtering and voltage stabilizing circuit 30;

[0044] The PWM signal generating circuit 10 is configured to alternately output a first high potential signal Hi and a first low potential signal Lo at an output terminal;

[0045] The positive-negative power conversion circuit 20 comprises a first conversion output terminal 211 and a second conversion output terminal 221. The positive-negative power conversion circuit 20 is configured to output a first positive voltage signal at the first conversion output terminal 211 under the control of a first high potential signal Hi, and to output a first negative voltage signal at the second conversion output terminal 221 under the control of the first high potential signal Hi;

[0046] The active filtering and voltage stabilizing circuit 30 includes a first filtering output terminal 311 and a second filtering output terminal 321. The active filtering and voltage stabilizing circuit 30 is configured to output a second positive voltage signal VCLH at the first filtering output terminal 311 according to a first positive voltage signal, and to output a second negative voltage signal VCLL at the second filtering output terminal 321 according to a first negative voltage signal.

[0047] By way of example, the positive-negative power conversion circuit 20 is configured to output a first positive voltage signal at the first conversion output terminal 211 under the control of the first high potential signal Hi.

[0048] For example, at the same time, the positive-negative power conversion circuit 20 is configured to output a first negative voltage signal at the second conversion output terminal 221 under the control of the first high potential signal Hi.

[0049] For example, the PWM signal generating circuit 10 is configured to alternately output a first high potential signal Hi and a first low potential signal Lo, and the periods of the first high potential signal Hi and the first low potential signal Lo are adjustable (changeable), the duty cycle of the first high potential signal Hi is adjustable, and the waveforms of the first high potential signal Hi and the first low potential signal Lo are as follows: Figure 4 and Figure 5 shown.

[0050] For example, the positive-negative power conversion circuit 20 is used to convert the periodic signal of the PWM signal generating circuit 10 into a voltage output.

[0051] For example, the active filtering and voltage stabilizing circuit 30 is used to eliminate the ripple effect of the positive and negative power conversion circuit 20, stabilize the voltage, and provide the voltage to the tester for use as a clamping power supply.

[0052] In the embodiment of the present application, the positive-negative power conversion circuit 20 is electrically connected between the PWM signal generating circuit 10 and the active filtering voltage stabilizing circuit 30. The positive-negative power conversion circuit 20 is configured to output a first positive voltage signal at the first conversion output terminal 211 and a first negative voltage signal at the second conversion output terminal 221 under the control of the first high potential signal Hi. The active filtering voltage stabilizing circuit 30 is configured to output a second positive voltage signal VCLH at the first filter output terminal 311 according to the first positive voltage signal, and to output a second negative voltage signal VCLL at the second filter output terminal 321 according to the first negative voltage signal. Therefore, the embodiment of the present application only needs to set the positive-negative power conversion circuit 20 electrically connected between the PWM signal generating circuit 10 and the active filtering voltage stabilizing circuit 30 to provide a clamping voltage. Therefore, the clamping voltage generating circuit structure of the embodiment of the present application is simple, which can greatly reduce the cost of the power supply in the prior art.

[0053] In the embodiment of the present application, PWM (Pulse Width Modulation) of FPGA or CPLD is used, or the period of the control signal is changed to be variable by FPGA, that is, the digital signal is converted into an adjustable analog voltage modulation circuit, which is used as a clamping voltage for the test machine.

[0054] In the embodiment of the present application, the system design can be simplified without using a DAC IC and a communication interface, and the cost can be reduced without using a DACIC. A single control signal can be used to provide a positive / negative power clamp voltage for the tester. Therefore, the clamp voltage generation circuit structure of the embodiment of the present application is simple, which can greatly reduce the cost of the power supply in the prior art.

[0055] In some implementations, the PWM signal generating circuit 10 includes at least one of an FPGA and a CPLD.

[0056] By way of example, the PWM signal generating circuit 10 includes at least one of an FPGA and a CPLD, but is not limited thereto. For example, the PWM signal generating circuit 10 may also use other related integrated circuit control ICs to output PWM signals.

[0057] The period conversion of the first high potential signal Hi and the first low potential signal Lo of the PWM signal generating circuit 10 satisfies the following formula (1) and formula (2):

[0058] Formula (1), , where Vtarget is the required clamping voltage (the voltage of the second positive voltage signal VCLH, or / and the voltage of the second negative voltage signal VCLL)

[0059] Formula (2), , where Ttarget is the required clamping voltage period, and variable duty is the period of the entire control signal changed by FPGA or CPLD to be variable.

[0060] For example, in one example, the first high potential signal Hi and the first low potential signal Lo are + / -12V (ie, Vmax / Vmin), and now a clamping voltage of + / -3.6V (Vtarget, the voltage of the second positive voltage signal VCLH is 3.6V, and the voltage of the second negative voltage signal VCLL is -3.6V) is required, then PWM / control signal=30%.

[0061] For example, in one example, the first high potential signal Hi and the first low potential signal Lo are + / -18V (ie, Vmax / Vmin), PWM / control signal=30%, then the clamping voltage becomes + / -5.4V (Vtarget, the voltage of the second positive voltage signal VCLH is 5.4V, and the voltage of the second negative voltage signal VCLL is -5.4V)

[0062] In some embodiments, the positive-negative power conversion circuit 20 includes a first sub-power conversion circuit 21 and a second sub-power conversion circuit 22;

[0063] The first sub-power conversion circuit 21 comprises a first conversion output terminal 211, the input terminal of the first sub-power conversion circuit 21 is connected to the first input positive voltage VDD, and the first sub-power conversion circuit 21 is configured to output a first positive voltage signal at the first conversion output terminal 211 according to the first input positive voltage VDD under the control of the first high potential signal Hi;

[0064] The second sub-power conversion circuit 22 includes a second conversion output terminal 221. The input terminal of the second sub-power conversion circuit 22 is connected to the first input negative voltage VSS. The second sub-power conversion circuit 22 is configured to output a first negative voltage signal at the second conversion output terminal 221 according to the first input negative voltage VSS under the control of the first high potential signal Hi.

[0065] In some embodiments, the first sub-power conversion circuit 21 includes an N-type transistor T1 and a first storage capacitor CL1, the gate of the N-type transistor T1 is electrically connected to the output end of the PWM signal generating circuit 10, the first electrode of the N-type transistor T1 is connected to the first input positive voltage VDD, the second electrode of the N-type transistor T1 is electrically connected to the first capacitor electrode of the first storage capacitor CL1, the second electrode of the N-type transistor T1 is at the first conversion output end 211, and the second capacitor electrode of the first storage capacitor CL1 is electrically connected to the ground end GND;

[0066] The second sub-power conversion circuit 22 includes a P-type transistor T2 and a second storage capacitor CL2, the gate of the P-type transistor T2 is electrically connected to the output end of the PWM signal generating circuit 10, the first electrode of the P-type transistor T2 is connected to the first input negative voltage VSS, the second electrode of the P-type transistor T2 is electrically connected to the first capacitor electrode of the second storage capacitor CL2, the second electrode of the P-type transistor T2 is the second conversion output end 221, and the second capacitor electrode of the second storage capacitor CL2 is electrically connected to the ground end GND.

[0067] For example, when the gate of the N-type transistor T1 is connected to the first high potential signal Hi, the N-type transistor T1 is turned on; when the gate of the N-type transistor T1 is connected to the first low potential signal Lo, the N-type transistor T1 is turned off.

[0068] For example, when the gate of the P-type transistor T2 is connected to the first high potential signal Hi, the P-type transistor T2 is turned on (the first input negative voltage VSS is less than 0); when the gate of the P-type transistor T2 is connected to the first low potential signal Lo, the P-type transistor T2 is turned off.

[0069] By way of example, the first storage capacitor CL1 is used to store the voltage of the first positive voltage signal, and the second storage capacitor CL2 is used to store the voltage of the first negative voltage signal.

[0070] For example, the N-type transistor T1 (ie, NMOS transistor) and the P-type transistor T2 (ie, PMOS transistor) may be thin film transistors (TFT for short) or field effect transistors (FET for short), etc.

[0071] For example, the first electrode of the N-type transistor T1 and the second electrode of the N-type transistor T1 may be different ones of a source and a drain, respectively. In some implementations, the source and the drain may be swapped.

[0072] For example, the first electrode of the P-type transistor T2 and the second electrode of the P-type transistor T2 may be different ones of a source and a drain, respectively. In some implementations, the source and the drain may be swapped.

[0073] In some embodiments, the active filtering and voltage stabilizing circuit 30 includes a first sub-filtering and voltage stabilizing circuit 31 and a second sub-filtering and voltage stabilizing circuit 32:

[0074] The first sub-filter voltage stabilization circuit 31 comprises a first filter output terminal 311, and the first sub-filter voltage stabilization circuit 31 is configured to output a second positive voltage signal VCLH at the first filter output terminal 311 according to the first positive voltage signal;

[0075] The second sub-filtering and voltage-stabilizing circuit 32 comprises a second filtering output terminal 321 . The second sub-filtering and voltage-stabilizing circuit 32 is configured to output a second negative voltage signal VCLL at the second filtering output terminal 321 according to the first negative voltage signal.

[0076] In some embodiments, the first sub-filter voltage stabilization circuit 31 includes a first operational amplifier M1, the first conversion output terminal 211 is electrically connected to the non-inverting input terminal of the first operational amplifier M1, the inverting input terminal of the first operational amplifier M1 is electrically connected to the output terminal of the first operational amplifier M1, and the output terminal of the first operational amplifier M1 is the first filter output terminal 311;

[0077] The second sub-filter voltage stabilization circuit 32 includes a second operational amplifier M2, the second conversion output terminal 221 is electrically connected to the non-inverting input terminal of the second operational amplifier M2, the inverting input terminal of the second operational amplifier M2 is electrically connected to the output terminal of the second operational amplifier M2, and the output terminal of the second operational amplifier M2 is the second filter output terminal 321.

[0078] In some embodiments, the first sub-filter voltage stabilization circuit 31 further includes a first capacitor C1, a first capacitor electrode of the first capacitor C1 is electrically connected to the non-inverting input terminal of the first operational amplifier M1, and a second capacitor electrode of the first capacitor C1 is electrically connected to the output terminal of the first operational amplifier M1;

[0079] The second sub-filter voltage stabilization circuit 32 further includes a third capacitor C3, a first capacitor electrode of the third capacitor C3 is electrically connected to the non-inverting input terminal of the second operational amplifier M2, and a second capacitor electrode of the third capacitor is electrically connected to the output terminal of the second operational amplifier M2.

[0080] In some embodiments, the first sub-filter voltage stabilization circuit 31 further includes a first resistor R1, a second resistor R2, and a second capacitor C2, the first resistor R1 and the second resistor R2 are arranged in series between the first conversion output terminal 211 and the non-inverting input terminal of the first operational amplifier M1, the first capacitor electrode of the second capacitor C2 is electrically connected to the non-inverting input terminal of the first operational amplifier M1, the second capacitor electrode of the second capacitor C2 is electrically connected to the ground terminal GND, and the first capacitor electrode of the first capacitor C1 is electrically connected between the first resistor R1 and the second resistor R2;

[0081] The second sub-filter voltage stabilization circuit 32 also includes a third resistor R3, a fourth resistor R4 and a fourth capacitor C4. The third resistor R3 and the fourth resistor R4 are arranged in series between the second conversion output terminal 221 and the in-phase input terminal of the second operational amplifier M2. The first capacitor electrode of the fourth capacitor C4 is electrically connected to the in-phase input terminal of the second operational amplifier M2, the second capacitor electrode of the fourth capacitor is electrically connected to the ground terminal GND, and the first capacitor electrode of the third capacitor C3 is electrically connected between the third resistor R3 and the fourth resistor R4.

[0082] For example, in some implementations, the clamping voltage generating circuit 100 operates as follows:

[0083] S1, FPGA or CPLD outputs a target signal (a first high potential signal Hi, and / or a first low potential signal Lo) periodically to the positive and negative power conversion circuit 20.

[0084] S2-1, please combine Figure 3 and Figure 4When the duty cycle of the target signal is at the first high potential signal Hi (the first high potential signal Hi>0V), the N-type transistor T1 is in the on state, and the connected first input positive voltage VDD charges the first storage capacitor CL1 (the first positive voltage signal VCL1 is stored in the first storage capacitor CL1), and the charged voltage can be calculated by formula (1) or formula (2); when the duty cycle of the target signal is at the first low potential signal Lo (for example, the first low potential signal Lo=0V), the N-type transistor T1 is in the off state, and the voltage of the first storage capacitor CL1 will be discharged due to the circuit leakage effect, such as Figure 4 The waveform of the first positive voltage signal VCL1 is shown in FIG.

[0085] S2-2, please combine Figure 4 and Figure 5 When the duty cycle of the target signal is at the first high potential signal Hi (the first high potential signal Hi>0V), the P-type transistor T2 is in the on state, and the connected first input negative voltage VSS charges the second storage capacitor CL2 (the first negative voltage signal VCL2 is stored in the second storage capacitor CL2), and the charged voltage can be calculated by (1) or formula (2); when the duty cycle of the target signal is at the first low potential signal Lo (for example, the first low potential signal Lo=0V), the P-type transistor T2 is in the non-conducting state, and the voltage of the second storage capacitor CL2 will be discharged due to the circuit leakage effect, such as Figure 5 The waveform of the first negative voltage signal VCL2 is shown in FIG.

[0086] S3, an active filtering and voltage stabilizing circuit 30, may be composed of a 2-stage low pass filter circuit or a low-pass-band pass filter plus an OPA (Operational Amplifier) ​​feedback operational amplifier feedback circuit.

[0087] S3-1, such as Figure 4 As shown, Figure 4 After the first positive voltage signal VCL1 passes through the active filtering and voltage stabilizing circuit 30, the ripple signal in the first positive voltage signal VCL1 can be eliminated; the high frequency and unwanted frequency can be removed, and the voltage output can be stabilized by the high CMRR (Common mode rejection ratio) capability of the OPA, and provided to the tester as a positive clamping voltage (second positive voltage signal VCLH) for use, such as Figure 4 As shown in the waveform of the second positive voltage signal VCLH.

[0088] S3-2, such as Figure 5 As shown, Figure 5 After the first negative voltage signal VCL2 passes through the active filtering and voltage stabilizing circuit 30, the ripple signal in the first negative voltage signal VCL2 can be eliminated; the high frequency and unwanted frequency can be removed, and the voltage output can be stabilized by the high CMRR (Common mode rejection ratio) capability of the OPA, and provided to the tester as a negative clamping voltage (second negative voltage signal VCLL) for use, such as Figure 5 As shown in the waveform of the second negative voltage signal VCLL.

[0089] In some embodiments, the absolute value of the first positive voltage signal VCL1 and the absolute value of the first negative voltage signal VCL2 are both smaller than the absolute value of the first high potential signal Hi.

[0090] For example, for example, the first input positive voltage VDD may be 12V, and the first input negative voltage VSS may be -12V.

[0091] For example, for example, the first high potential signal Hi and the first low potential signal Lo are + / -12V (ie Vmax / Vmin), PWM / control signal=30%, then the voltage of the second positive voltage signal VCLH is +3.6V; the voltage of the second negative voltage signal VCLL=-3.6V.

[0092] For example, the second positive voltage signal VCLH and the second negative voltage signal VCLL can be used as power supplies for the next stage circuit, and the second positive voltage signal VCLH and the second negative voltage signal VCLL can be input to the power supply terminal of other circuits, that is, the output voltage capability of the PA.

[0093] The present application also provides a power supply, which includes any one of the clamping voltage generating circuits 100 described above.

[0094] By way of example, the power supply includes any one of the clamping voltage generating circuits 100 described above, and the power supply can be used as the power supply of a circuit at a next level, and the signal of the power supply can be input to the power supply terminal of other circuits.

[0095] By way of example, the power supply includes any one of the clamping voltage generating circuits 100 described above, and the power supply may be an electronic product, and may be electrically connected to a power terminal of other devices or electronic products to provide a power signal for the other devices or electronic products.

[0096] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A clamping voltage generating circuit, characterized in that: It includes a PWM signal generating circuit, a positive and negative power conversion circuit and an active filtering and voltage stabilizing circuit, wherein the positive and negative power conversion circuit is electrically connected between the PWM signal generating circuit and the active filtering and voltage stabilizing circuit; The PWM signal generating circuit is configured to alternately output a first high potential signal and a first low potential signal at an output end; The positive-negative power conversion circuit comprises a first conversion output terminal and a second conversion output terminal, wherein the positive-negative power conversion circuit is configured to output a first positive voltage signal at the first conversion output terminal under the control of the first high potential signal, and to output a first negative voltage signal at the second conversion output terminal under the control of the first high potential signal; The active filtering and voltage stabilizing circuit comprises a first filtering output terminal and a second filtering output terminal. The active filtering and voltage stabilizing circuit is configured to output a second positive voltage signal at the first filtering output terminal according to the first positive voltage signal, and to output a second negative voltage signal at the second filtering output terminal according to the first negative voltage signal.

2. The clamping voltage generating circuit according to claim 1, characterized in that: The PWM signal generating circuit includes at least one of FPGA and CPLD.

3. The clamping voltage generating circuit according to claim 1, characterized in that: The positive and negative power conversion circuit comprises: A first sub-power conversion circuit comprises the first conversion output terminal, the input terminal of the first sub-power conversion circuit is connected to a first input positive voltage, and the first sub-power conversion circuit is configured to output the first positive voltage signal at the first conversion output terminal according to the first input positive voltage under the control of the first high potential signal; The second sub-power conversion circuit includes the second conversion output terminal, the input terminal of the second sub-power conversion circuit is connected to the first input negative voltage, and the second sub-power conversion circuit is configured to output the first negative voltage signal at the second conversion output terminal according to the first input negative voltage under the control of the first high potential signal.

4. The clamping voltage generating circuit according to claim 3, characterized in that: The first sub-power conversion circuit includes an N-type transistor and a first storage capacitor, the gate of the N-type transistor is electrically connected to the output end of the PWM signal generating circuit, the first electrode of the N-type transistor is connected to the first input positive voltage, the second electrode of the N-type transistor is electrically connected to the first capacitor electrode of the first storage capacitor, the second electrode of the N-type transistor is the first conversion output end, and the second capacitor electrode of the first storage capacitor is electrically connected to the ground end; The second sub-power conversion circuit includes a P-type transistor and a second storage capacitor, the gate of the P-type transistor is electrically connected to the output end of the PWM signal generating circuit, the first pole of the P-type transistor is connected to the first input negative voltage, the second pole of the P-type transistor is electrically connected to the first capacitor electrode of the second storage capacitor, the second pole of the P-type transistor is the second conversion output end, and the second capacitor electrode of the second storage capacitor is electrically connected to the ground end.

5. The clamping voltage generating circuit according to claim 3, characterized in that: The active filtering voltage stabilizing circuit comprises: A first sub-filter voltage stabilization circuit, comprising the first filter output terminal, wherein the first sub-filter voltage stabilization circuit is configured to output a second positive voltage signal at the first filter output terminal according to the first positive voltage signal; The second sub-filter voltage stabilizing circuit comprises the second filter output terminal, and the second sub-filter voltage stabilizing circuit is configured to output a second negative voltage signal at the second filter output terminal according to the first negative voltage signal.

6. The clamping voltage generating circuit according to claim 5, characterized in that: The first sub-filter voltage stabilization circuit includes a first operational amplifier, the first conversion output terminal is electrically connected to the non-inverting input terminal of the first operational amplifier, the inverting input terminal of the first operational amplifier is electrically connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is the first filter output terminal; The second sub-filter voltage stabilization circuit includes a second operational amplifier, the second conversion output terminal is electrically connected to the non-inverting input terminal of the second operational amplifier, the inverting input terminal of the second operational amplifier is electrically connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is the second filter output terminal.

7. The clamping voltage generating circuit according to claim 6, characterized in that: The first sub-filter voltage stabilization circuit further includes a first capacitor, a first capacitor electrode of the first capacitor is electrically connected to the non-inverting input terminal of the first operational amplifier, and a second capacitor electrode of the first capacitor is electrically connected to the output terminal of the first operational amplifier; The second sub-filter voltage stabilization circuit also includes a third capacitor, a first capacitor electrode of the third capacitor is electrically connected to the in-phase input terminal of the second operational amplifier, and a second capacitor electrode of the third capacitor is electrically connected to the output terminal of the second operational amplifier.

8. The clamping voltage generating circuit according to claim 7, characterized in that: The first sub-filter voltage stabilization circuit further includes a first resistor, a second resistor and a second capacitor, the first resistor and the second resistor are arranged in series between the first conversion output terminal and the non-inverting input terminal of the first operational amplifier, the first capacitor electrode of the second capacitor is electrically connected to the non-inverting input terminal of the first operational amplifier, the second capacitor electrode of the second capacitor is electrically connected to the ground terminal, and the first capacitor electrode of the first capacitor is electrically connected between the first resistor and the second resistor; The second sub-filter voltage stabilization circuit also includes a third resistor, a fourth resistor and a fourth capacitor. The third resistor and the fourth resistor are arranged in series between the second conversion output terminal and the non-inverting input terminal of the second operational amplifier. The first capacitor electrode of the fourth capacitor is electrically connected to the non-inverting input terminal of the second operational amplifier, the second capacitor electrode of the fourth capacitor is electrically connected to the ground terminal, and the first capacitor electrode of the third capacitor is electrically connected between the third resistor and the fourth resistor.

9. The clamping voltage generating circuit according to claim 1, characterized in that: An absolute value of the first positive voltage signal and an absolute value of the first negative voltage signal are both smaller than an absolute value of the first high potential signal.

10. A power supply, characterized in that: The invention comprises the clamping voltage generating circuit according to any one of claims 1 to 9.

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