Charge pump voltage stabilizing circuit, chip and electronic equipment

Abstract

The invention belongs to the field of integrated circuit design, and comprises a negative feedback loop and a load stage circuit, the negative feedback loop comprises a charge pump circuit and a voltage stabilizing circuit, the load stage circuit comprises at least one load stage, and each load stage comprises a corresponding filter circuit and a load circuit; the negative feedback loop is configured to generate and output bias voltage based on the charge pump circuit and the voltage stabilizing circuit; the filter circuit is connected with the negative feedback loop and is configured to filter the bias voltage and output the bias voltage to a load circuit in the same load stage; the load circuit is connected with the filter circuit in the same load stage, and is configured to generate and output a load voltage according to the filtered bias voltage. According to the invention, the bias voltage is provided for the load stage circuit through the single negative feedback loop, and a plurality of mutually isolated load voltages are generated on the plurality of load stages, so that the voltage stabilizing circuit structure in a related analog circuit system can be effectively simplified.

Description

Technical Field

[0001] The present application belongs to the field of integrated circuit design, and in particular relates to a charge pump voltage regulator circuit, a chip and an electronic device. Background Art

[0002] With the rapid development of integrated circuits, high-speed data transmission systems have gradually become a hot topic of current research, among which the research on high-speed Ethernet physical layer (PHY) interface chips is an important part. A complete Ethernet physical layer chip includes two major functions: sending and receiving. The sending and receiving functions of the high-speed serial signal SGMII (Serial Gigabit Media Independent Interface) are implemented through the SerDes (Serializer / Deserializer) circuit in the physical layer chip. SerDes is a technology that converts parallel data into serial data for transmission. It is widely used in the field of high-speed data communication. SerDes technology solves the problems of bandwidth limitation, signal integrity maintenance and communication cost control in high-speed data transmission through time division multiplexing and point-to-point methods.

[0003] In a large-scale mixed digital-analog circuit such as a SerDes circuit, the power supplies of each submodule in the analog system need to be isolated from each other and independently controlled in the system control. On this basis, the area needs to be as small as possible and each submodule needs to be powered independently. Figure 1 The power supply and module architecture of the high-speed SerDes module shown generally include functional modules such as a transmitting circuit TX, a receiving circuit RX, and a clock circuit PLL. Each internal functional module also requires a mutually independent voltage source for power supply to cope with the effects of power supply voltage drop and noise caused by the module's own power consumption. In common related architectures, a separate voltage stabilization circuit is provided for each voltage demand point, which results in redundancy in the voltage stabilization circuit structure. Summary of the invention

[0004] The purpose of the present application is to provide a charge pump voltage regulator circuit, aiming to solve the problem of voltage regulator circuit structure redundancy in related analog circuit systems.

[0005] A first aspect of an embodiment of the present application provides a charge pump voltage stabilization circuit, comprising a negative feedback loop and a load machine circuit, wherein the negative feedback loop comprises a charge pump circuit and a voltage stabilization circuit, the load stage circuit comprises at least one load stage, and each load stage comprises a corresponding filter circuit and a load circuit;

[0006] The negative feedback loop is configured to generate and output a bias voltage based on the charge pump circuit and the voltage regulator circuit;

[0007] The filter circuit is connected to the negative feedback loop and is configured to filter the bias voltage and output it to the load circuit in the same load stage;

[0008] The load circuit is connected to the filter circuit in the same load stage, and is configured to generate and output a load voltage according to the filtered bias voltage.

[0009] In one of the embodiments, the voltage stabilization circuit includes an operational amplifier and a negative feedback network;

[0010] The charge pump circuit is configured to generate a driving voltage based on an externally input clock signal and output the driving voltage to the operational amplifier;

[0011] The negative feedback network is configured to generate a feedback voltage based on the bias voltage and output the feedback voltage to the operational amplifier;

[0012] The non-inverting input terminal of the operational amplifier receives an input voltage, the inverting input terminal of the operational amplifier is connected to the output terminal of the negative feedback network, the output terminal of the operational amplifier is connected to the input terminal of the negative feedback network, and the operational amplifier is configured to generate and output the bias voltage based on the input voltage and the feedback voltage under the drive of the driving voltage.

[0013] In one embodiment, the negative feedback network includes an electronic switch tube, a first negative feedback resistor and a second negative feedback resistor;

[0014] The control end of the electronic switch tube is connected to the output end of the operational amplifier, the input end of the electronic switch tube is connected to the power supply, and the output end of the electronic switch tube is connected to the first end of the first negative feedback resistor; wherein the control end of the electronic switch tube constitutes the input end of the negative feedback network;

[0015] The second end of the first negative feedback resistor is connected to the first end of the second negative feedback resistor, and the second end of the second resistor is grounded;

[0016] The second end of the first negative feedback resistor is connected to the first end of the second negative feedback resistor; wherein the common connection end of the first negative feedback resistor and the second negative feedback resistor constitutes the output end of the negative feedback network.

[0017] In one of the embodiments, the charge pump circuit includes a first-stage charge pump, a second-stage charge pump and a switch circuit;

[0018] The first-stage charge pump is configured to generate and output a first voltage signal based on a power supply voltage and the clock signal;

[0019] The second-stage charge pump is configured to generate and output a second voltage signal based on a power supply voltage, the clock signal and the first voltage signal;

[0020] The switch circuit is configured to generate the driving voltage based on the second voltage signal and output the driving voltage to the operational amplifier.

[0021] In one of the embodiments, the first-stage charge pump includes a clock signal processing unit, a first controllable switch, a second controllable switch, a resistance unit, a first capacitor unit, a second capacitor unit, a first diode and a second diode, and the first voltage signal includes a third voltage signal and a fourth voltage signal;

[0022] The clock signal processing unit is configured to generate and output a first clock signal and a second clock signal based on the clock signal; wherein the first clock signal is inversely proportional to the second clock signal;

[0023] The moving end of the first controllable switch is connected to the first end of the first capacitor unit, the first fixed end of the first controllable switch is connected to the power supply, the second fixed end of the first controllable switch is grounded, and the control end of the first controllable switch is connected to the first output end of the clock signal processing unit, and is configured to control its own moving end to be connected to its own first fixed end or its own second fixed end according to the level state of the first clock signal; wherein, when the first clock signal is in a high level state, its own moving end is connected to its own first fixed end, and when the first clock signal is in a low level state, its own moving end is connected to its own second fixed end;

[0024] The moving end of the second controllable switch is connected to the first end of the second capacitor unit, the first fixed end of the second controllable switch is connected to the power supply, the second fixed end of the second controllable switch is grounded, and the control end of the second controllable switch is connected to the second output end of the clock signal processing unit, and is configured to control its own moving end to be connected to its own first fixed end or its own second fixed end according to the level state of the second clock signal; wherein, when the second clock signal is in a high level state, its own moving end is connected to its own first fixed end, and when the second clock signal is in a low level state, its own moving end is connected to its own second fixed end;

[0025] A first end of the resistance unit is connected to the power supply, and a second end of the resistance unit is connected to a first end of the first diode and a second end of the second diode respectively;

[0026] The second end of the first diode is connected to the second end of the first capacitor unit; wherein the common connection end of the first diode and the first capacitor unit constitutes the first output end of the first-stage charge pump, and is configured to output the third voltage signal;

[0027] The second end of the second diode is connected to the second end of the second capacitor unit; wherein the common connection end of the second diode and the second capacitor unit constitutes the second output end of the first-stage charge pump, which is configured to output the fourth voltage signal.

[0028] In one embodiment, the second-stage charge pump includes a first inverter, a second inverter, a third controllable switch, a fourth controllable switch, a fifth controllable switch, a sixth controllable switch, a seventh controllable switch, an eighth controllable switch, a third capacitor unit, a fourth capacitor unit, a fifth capacitor unit and a sixth capacitor unit, and the second voltage signal includes a fifth voltage signal, a sixth voltage signal, a seventh voltage signal and an eighth voltage signal;

[0029] The input terminal of the first inverter is connected to the first output terminal of the clock signal processing unit, and is configured to generate and output a third clock signal based on the first clock signal;

[0030] The input terminal of the second inverter is connected to the second output terminal of the clock signal processing unit, and is configured to generate and output a fourth clock signal based on the second clock signal;

[0031] The moving end of the third controllable switch is respectively connected to the first end of the third capacitor unit and the first end of the fourth capacitor unit, the first fixed end of the third controllable switch is connected to the power supply, the second fixed end of the third controllable switch is grounded, and the control end of the third controllable switch is connected to the output end of the first inverter, and is configured to control its own moving end to be connected to its own first fixed end or its own second fixed end according to the level state of the third clock signal; wherein, when the third clock signal is in a low level state, its own moving end is connected to its own first fixed end, and when the third clock signal is in a high level state, its own moving end is connected to its own second fixed end;

[0032] The moving end of the fourth controllable switch is respectively connected to the first end of the fifth capacitor unit and the first end of the sixth capacitor unit, the first fixed end of the fourth controllable switch is connected to the power supply, the second fixed end of the fourth controllable switch is grounded, and the control end of the fourth controllable switch is connected to the output end of the second inverter, and is configured to control its own moving end to be connected to its own first fixed end or its own second fixed end according to the level state of the fourth clock signal; wherein, when the fourth clock signal is in a low level state, its own moving end is connected to its own first fixed end, and when the fourth clock signal is in a high level state, its own moving end is connected to its own second fixed end;

[0033] The first end of the fifth controllable switch is connected to the second end of the resistor unit, the second end of the fifth controllable switch is connected to the second end of the fourth capacitor unit, and the control end of the fifth controllable switch is connected to the first output end of the first-stage charge pump, and is configured to enter a corresponding switch state according to the level state of the third voltage signal; wherein, when the third voltage signal is in a high level state, it enters a conducting state, and when the third voltage signal is in a low level state, it enters an off state;

[0034] The first end of the sixth controllable switch is connected to the second end of the resistor unit, the second end of the sixth controllable switch is connected to the second end of the third capacitor unit, and the control end of the sixth controllable switch is connected to the first output end of the first-stage charge pump, and is configured to enter a corresponding switch state according to the level state of the third voltage signal; wherein, when the third voltage signal is in a high level state, it enters a conducting state, and when the third voltage signal is in a low level state, it enters an off state;

[0035] The first end of the seventh controllable switch is connected to the second end of the resistor unit, the second end of the seventh controllable switch is connected to the second end of the sixth capacitor unit, and the control end of the seventh controllable switch is connected to the second output end of the first-stage charge pump, and is configured to enter a corresponding switch state according to the level state of the fourth voltage signal; wherein, when the fourth voltage signal is in a high level state, it enters a conducting state, and when the fourth voltage signal is in a low level state, it enters an off state;

[0036] The first end of the eighth controllable switch is connected to the second end of the resistor unit, the second end of the eighth controllable switch is connected to the second end of the fifth capacitor unit, and the control end of the eighth controllable switch is connected to the second output end of the first-stage charge pump, and is configured to enter a corresponding switch state according to the level state of the fourth voltage signal; wherein, when the fourth voltage signal is in a high level state, it enters a conducting state, and when the fourth voltage signal is in a low level state, it enters an off state;

[0037] The common connection terminal of the fifth controllable switch and the fourth capacitor unit constitutes a first output terminal of the second-stage charge pump, and is configured to output the fifth voltage signal;

[0038] The common connection terminal of the sixth controllable switch and the third capacitor unit constitutes a second output terminal of the second-stage charge pump, and is configured to output the sixth voltage signal;

[0039] A common connection terminal of the seventh controllable switch and the sixth capacitor unit constitutes a third output terminal of the second-stage charge pump, and is configured to output the seventh voltage signal;

[0040] A common connection terminal of the eighth controllable switch and the fifth capacitor unit constitutes a fourth output terminal of the second-stage charge pump, and is configured to output the eighth voltage signal.

[0041] In one embodiment, the switch circuit includes a first transmission gate and a second transmission gate;

[0042] The input end of the first transmission gate is connected to the first output end of the second-stage charge pump, the first control end of the first transmission gate is connected to the second output end of the second-stage charge pump, the second control end of the first transmission gate is connected to the fourth output end of the second-stage charge pump, and the first transmission gate is configured to enter a corresponding transmission state according to the level state of the sixth voltage signal and the level state of the eighth voltage signal; wherein, when the sixth voltage signal is in a low level state and the eighth voltage signal is in a high level state, the first transmission gate is turned on and outputs the fifth voltage signal;

[0043] The input terminal of the second transmission gate is connected to the third output terminal of the second-stage charge pump, the first control terminal of the second transmission gate is connected to the second output terminal of the second-stage charge pump, the second control terminal of the second transmission gate is connected to the fourth output terminal of the second-stage charge pump, and the second transmission gate is configured to enter a corresponding transmission state according to the level state of the sixth voltage signal and the level state of the eighth voltage signal; wherein, when the sixth voltage signal is in a low level state and the eighth voltage signal is in a high level state, the second transmission gate is turned on and outputs the seventh voltage signal;

[0044] The output end of the first transmission gate is connected to the output end of the second transmission gate, and together constitutes the output end of the charge pump circuit, which is configured to output the driving voltage according to the fifth voltage signal and the seventh voltage signal.

[0045] In one of the embodiments, the filter circuit includes a filter resistor and a filter capacitor;

[0046] The first end of the filter resistor is connected to the output end of the negative feedback loop, the second end of the filter resistor is connected to the first end of the filter capacitor, and the second end of the filter capacitor is grounded; wherein the common connection end of the filter resistor and the filter capacitor constitutes the output end of the filter circuit, and is configured to output the bias voltage after filtering.

[0047] In one of the embodiments, the load circuit includes an adjustment module and a load module;

[0048] The input end of the adjustment module is connected to the output end of the filter circuit, and the output end of the adjustment module is connected to the load module. The adjustment module is configured to adjust the bias voltage to obtain a load voltage and output the load voltage to the load module.

[0049] In one embodiment, the adjustment module includes a first transistor and a second transistor, and the load module includes a load capacitor and a load unit;

[0050] The control end of the first transistor is connected to the output end of the filter circuit, the input end of the first transistor is connected to the power supply, and the output end of the first transistor is connected to the input end of the second transistor;

[0051] The output end of the second transistor is respectively connected to the first end of the load capacitor and the first end of the load unit, and the control end of the second transistor is respectively connected to the second end of the load capacitor and the second end of the load unit, and is configured to generate and output the load voltage based on the bias voltage to power the load unit.

[0052] A second aspect of an embodiment of the present application provides a chip, which includes the charge pump voltage stabilization circuit as described above.

[0053] A third aspect of an embodiment of the present application provides an electronic device, which includes the charge pump voltage stabilization circuit as described above.

[0054] The charge pump voltage stabilization circuit mentioned above in the embodiment of the present application includes a negative feedback loop and a load stage circuit, the negative feedback loop includes a charge pump circuit and a voltage stabilization circuit, the load stage circuit includes at least one load stage, each of the load stages includes a corresponding filter circuit and a load circuit, the voltage stabilization circuit provides a bias voltage under the action of the charge pump, and the corresponding filter circuit in each load stage filters the bias voltage to ensure the noise isolation function between different load stages, and the corresponding load circuit generates and outputs a load voltage based on the filtered bias voltage, which is used to provide a load voltage for subsequent circuits. In summary, the present application provides a bias voltage to the load stage circuit through a single negative feedback loop, and generates multiple mutually isolated load voltages on multiple load stages, which can effectively simplify the voltage stabilization circuit structure in the relevant analog circuit system. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the related technologies or the embodiments of the present application, the drawings required for use in the description of the related technologies or the embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, not all embodiments. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0056] Figure 1 A schematic diagram of a high-speed SerDes module power supply architecture provided in an embodiment of the present application;

[0057] Figure 2 A schematic diagram of a structure of a charge pump voltage stabilizing circuit provided in the first aspect of the embodiment of the present application;

[0058] Figure 3 A detailed structural schematic diagram of the charge pump voltage stabilizing circuit provided in the first aspect of the embodiment of the present application;

[0059] Figure 4 Another detailed structural diagram of the charge pump voltage stabilizing circuit provided in the first aspect of the embodiment of the present application;

[0060] Figure 5 A schematic diagram of the structure of a charge pump circuit in the charge pump voltage stabilizing circuit provided in the first aspect of the embodiment of the present application;

[0061] Figure 6 A circuit schematic diagram of a first-stage charge pump in a charge pump circuit in a charge pump voltage stabilizing circuit provided in the first aspect of an embodiment of the present application;

[0062] Figure 7 A circuit schematic diagram of a second-stage charge pump in a charge pump circuit in a charge pump voltage stabilizing circuit provided in the first aspect of an embodiment of the present application;

[0063] Figure 8 A circuit schematic diagram of a switch circuit in a charge pump circuit in a charge pump voltage stabilizing circuit provided in the first aspect of an embodiment of the present application;

[0064] Fig. 9 A circuit schematic diagram of a filter circuit in a charge pump voltage stabilization circuit provided in the first aspect of the embodiment of the present application;

[0065] Fig.10 A circuit schematic diagram of a load circuit in a charge pump voltage stabilizing circuit provided in the first aspect of the embodiment of the present application;

[0066] Fig.11 A detailed circuit schematic diagram of a load circuit in the charge pump voltage stabilization circuit provided in the first aspect of the embodiment of the present application;

[0067] Fig.12 A schematic diagram of a chip provided in the second aspect of the embodiment of the present application;

[0068] Fig.13 A schematic diagram of an electronic device provided in accordance with the third aspect of an embodiment of the present application. DETAILED DESCRIPTION

[0069] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0070] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0071] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0072] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means one or more, unless otherwise clearly and specifically defined.

[0073] In the common architecture of the voltage regulator circuit of a large analog circuit system, a separate voltage regulator circuit is provided for each voltage demand point, which will cause redundancy in the circuit structure. Therefore, the present application proposes a charge pump voltage regulator circuit to simplify the voltage regulator circuit structure in the related analog circuit system.

[0074] Figure 2 A schematic diagram of the structure of the charge pump voltage stabilizing circuit provided in the first aspect of the embodiment of the present application is shown. For the sake of convenience, only the part related to the present embodiment is shown, which is described in detail as follows:

[0075] The charge pump voltage stabilization circuit 01 in this embodiment includes a negative feedback loop 10 and a load stage circuit 20. The negative feedback loop 10 includes a charge pump circuit 101 and a voltage stabilization circuit 102. The load stage circuit 20 includes at least one load stage 201. Each load stage includes a corresponding filter circuit and a load circuit.

[0076] The negative feedback loop 10 is configured to generate and output a bias voltage based on a charge pump circuit 101 and a voltage regulator circuit 102;

[0077] The filter circuit 2011 is connected to the negative feedback loop 10 and is configured to filter the bias voltage and output it to the load circuit 2012 in the same load stage;

[0078] The load circuit 2012 is connected to the filter circuit 2011 in the same load stage, and is configured to generate and output a load voltage according to the filtered bias voltage.

[0079] Understandably, Figure 1 The first load stage 201 and the corresponding filter circuit 2011 and load circuit 2012, as well as the second load stage 202 and the corresponding filter circuit 2021 and load circuit 2012 are described exemplarily. In actual situations, there will be at least one load stage in the load stage circuit 20, and each different load stage has its own filter circuit and load circuit. The size of the load voltage can be changed according to the actual load of the load circuit to change the size of the load stage, and each load stage can be individually enabled to be linked with the subsequent circuit for control, which is not specifically limited in this embodiment.

[0080] In detail, the bias voltage provided by the negative feedback loop can generate multiple voltages for output at different load levels, but the bias voltage provided by the negative feedback loop will change according to the output voltage requirements, so there are greater requirements for the output range of the op amp. In order to solve the requirements for the output voltage range, we introduce a charge pump circuit to increase the bias voltage output range, thereby obtaining a bias voltage of sufficient size for use at the load level. Since the power supply between each load usually needs to be isolated from each other, we introduce a filter circuit to achieve this effect, and finally output the corresponding load voltage through the load circuit. In summary, the charge pump voltage stabilization circuit proposed in this application provides a bias point through a single negative feedback loop to generate multiple independent output voltages at multiple load levels, which can effectively simplify the voltage stabilization circuit structure in the relevant analog circuit system.

[0081] exist Figure 2 Based on the schematic diagram of a charge pump voltage regulator circuit provided, the embodiment of the present application also provides a detailed schematic diagram of a charge pump voltage regulator circuit. For details, please refer to Figure 3 .

[0082] In one embodiment, the voltage stabilizing circuit 102 includes an operational amplifier 1021 and a negative feedback network 1022;

[0083] The charge pump circuit 101 is configured to generate a driving voltage based on an externally input clock signal and output the driving voltage to the operational amplifier 1021;

[0084] The negative feedback network 1022 is configured to generate a feedback voltage based on the bias voltage, and output the feedback voltage to the operational amplifier 1021;

[0085] The non-inverting input terminal of the operational amplifier 1021 receives the input voltage, the inverting input terminal of the operational amplifier 1021 is connected to the output terminal of the negative feedback network 1022, the output terminal of the operational amplifier 1021 is connected to the input terminal of the negative feedback network 1022, and the operational amplifier 1021 is configured to generate and output a bias voltage based on the input voltage and the feedback voltage under the drive of the driving voltage.

[0086] It is understandable that the charge pump circuit needs to increase the power supply voltage based on the external input clock signal, so that the op amp can have a wider range of voltage output. The negative feedback network makes the voltage output of the op amp more stable by providing negative feedback on the output of the op amp. Finally, under the action of the charge pump, the voltage regulator circuit increases the output range and can provide a sufficient voltage for the load level to use.

[0087] The present application also provides another detailed structural diagram of the charge pump voltage stabilizing circuit. Figure 4 .

[0088] In one embodiment, the negative feedback network includes an electronic switch tube M1, a first negative feedback resistor R1 and a second negative feedback resistor R2;

[0089] The control end of the electronic switch tube M1 is connected to the output end of the operational amplifier 1021, the input end of the electronic switch tube M1 is connected to the power supply, and the output end of the electronic switch tube M1 is connected to the first end of the first negative feedback resistor R1; wherein the control end of the electronic switch tube M1 constitutes the input end of the negative feedback network;

[0090] The second end of the first negative feedback resistor R1 is connected to the first end of the second negative feedback resistor R2, and the second end of the second resistor is grounded;

[0091] The second end of the first negative feedback resistor R1 is connected to the first end of the second negative feedback resistor R2; wherein the common connection end of the first negative feedback resistor R1 and the second negative feedback resistor R2 constitutes the output end of the negative feedback network.

[0092] Specifically, in some embodiments, the electronic switch tube is an NMOS tube, and its gate-source voltage can be expressed as vgs. Under the action of the negative feedback network, the negative feedback loop will eventually output a bias voltage Vg=VIN(R1+R2) / R2+vgs to the load-level circuit. The bias voltage is used to subsequently generate multiple output voltages Vo1, Vo2, Vo3, etc. at different load levels. The voltage stabilizing circuit of this structure realizes the function of providing multiple low-voltage power supplies with a certain degree of noise isolation performance by a single negative feedback network. When the load current changes, the voltage provided to the load circuit will change slightly, but the power tube current inside the regulator will not be drawn, and the negative feedback loop state is stable.

[0093] A schematic diagram of a structure of a charge pump circuit in a charge pump voltage stabilizing circuit provided in the first aspect of the embodiment of the present application is shown in FIG. Figure 5 .

[0094] In one embodiment, the charge pump circuit 101 includes a first-stage charge pump 1011 , a second-stage charge pump 1012 , and a switch circuit 1013 ;

[0095] The first stage charge pump 1011 is configured to generate and output a first voltage signal based on a power supply voltage VDD and a clock signal CLK;

[0096] The second stage charge pump 1012 is configured to generate and output a second voltage signal based on the power supply voltage VDD, the clock signal CLK and the first voltage signal;

[0097] The switch circuit 1013 is configured to generate a driving voltage based on the second voltage signal, and output the driving voltage VCP to the operational amplifier.

[0098] It is understandable that the Vg voltage provided by the negative feedback network changes according to the output voltage requirement, so there is a greater requirement for the output range of the op amp. In order to meet the requirements for the output voltage range, the op amp core uses a charge pump to increase the output range.

[0099] The present application also provides a circuit schematic diagram of a first-stage charge pump in a charge pump circuit in a charge pump voltage stabilization circuit. Figure 6 .

[0100] In one embodiment, the first-stage charge pump includes a clock signal processing unit D1, a first controllable switch S1, a second controllable switch S2, a resistor unit R0, a first capacitor unit C1, a second capacitor unit C2, a first diode VD1 and a second diode VD2, and the first voltage signal includes a third voltage signal and a fourth voltage signal;

[0101] The clock signal processing unit D1 is configured to generate and output a first clock signal and a second clock signal based on the clock signal; wherein the first clock signal is in antiphase with the second clock signal;

[0102] The moving end of the first controllable switch S1 is connected to the first end of the first capacitor unit C1, the first fixed end of the first controllable switch S1 is connected to the power supply, the second fixed end of the first controllable switch S1 is grounded, and the control end of the first controllable switch S1 is connected to the first output end of the clock signal processing unit D1, and is configured to control its own moving end to be connected to its own first fixed end or its own second fixed end according to the level state of the first clock signal; wherein, when the first clock signal is in a high level state, its own moving end is connected to its own first fixed end, and when the first clock signal is in a low level state, its own moving end is connected to its own second fixed end;

[0103] The moving end of the second controllable switch S2 is connected to the first end of the second capacitor unit C2, the first fixed end of the second controllable switch S2 is connected to the power supply, the second fixed end of the second controllable switch S2 is grounded, and the control end of the second controllable switch S2 is connected to the second output end of the clock signal processing unit D1, and is configured to control its own moving end to be connected to its own first fixed end or its own second fixed end according to the level state of the second clock signal; wherein, when the second clock signal is in a high level state, its own moving end is connected to its own first fixed end, and when the second clock signal is in a low level state, its own moving end is connected to its own second fixed end;

[0104] A first end of the resistance unit R0 is connected to a power source, and a second end of the resistance unit R0 is connected to a first end of a first diode VD1 and a second end of a second diode VD2 respectively;

[0105] The second end of the first diode VD1 is connected to the second end of the first capacitor unit C1; wherein the common connection end of the first diode VD1 and the first capacitor unit C1 constitutes the first output end of the first-stage charge pump, which is configured to output a third voltage signal;

[0106] The second end of the second diode VD2 is connected to the second end of the second capacitor unit C2; wherein the common connection end of the second diode VD2 and the second capacitor unit C2 constitutes the second output end of the first-stage charge pump, which is configured to output a fourth voltage signal.

[0107] Specifically, the power supply voltage provided for the charge pump circuit is AVDD18. The clock signal CLK received from the outside is processed by a clock signal processing unit to generate a pair of inverted first clock signals and second clock signals. Then, the switching states of the first controllable switch and the second controllable switch S2 are controlled respectively by the first clock signal and the second clock signal, so that the corresponding first capacitor unit C1 and the second capacitor unit C2 complete voltage bootstrapping, and finally the high level of the clock signal is raised to 2*AVDD18-vt, the low level is raised to AVDD-vt, and output to the subsequent second-stage charge pump, where vt is the voltage drop through the first diode VD1 and the second diode.

[0108] In detail, taking the first clock signal as an example, when the clock signal is at a high level, the active end A of the switch is connected to the fixed end C, at this time the capacitor is charged, and the voltage output by the first-stage charge pump is AVDD18-vt; when the clock signal is at a low level, the active end A of the switch is connected to the fixed end B, at this time the capacitor completes voltage bootstrapping, and the voltage output by the first-stage charge pump is 2*AVDD18-vt; that is to say, the voltage waveform output by the upper half of the first-stage charge pump here is inverted with the clock signal.

[0109] The present application also provides a circuit schematic diagram of a second-stage charge pump in a charge pump circuit in a charge pump voltage stabilization circuit. Figure 7 .

[0110] like Figure 7 As shown, in one embodiment, the second-stage charge pump includes a first inverter IC1, a second inverter IC2, a third controllable switch S3, a fourth controllable switch S4, a fifth controllable switch S5, a sixth controllable switch S6, a seventh controllable switch S7, an eighth controllable switch S8, a third capacitor unit C3, a fourth capacitor unit C4, a fifth capacitor unit C5 and a sixth capacitor unit C6, and the second voltage signal includes a fifth voltage signal, a sixth voltage signal, a seventh voltage signal and an eighth voltage signal;

[0111] An input terminal of the first inverter IC1 is connected to a first output terminal of the clock signal processing unit D1, and is configured to generate and output a third clock signal based on the first clock signal;

[0112] The input terminal of the second inverter IC2 is connected to the second output terminal of the clock signal processing unit D1, and is configured to generate and output a fourth clock signal based on the second clock signal;

[0113] The moving end of the third controllable switch S3 is connected to the first end of the third capacitor unit C3 and the first end of the fourth capacitor unit C4 respectively, the first fixed end of the third controllable switch S3 is connected to the power supply, the second fixed end of the third controllable switch S3 is grounded, and the control end of the third controllable switch S3 is connected to the output end of the first inverter IC1, and is configured to control its own moving end to be connected to its own first fixed end or its own second fixed end according to the level state of the third clock signal; wherein, when the third clock signal is in a high level state, its own moving end is connected to its own first fixed end, and when the third clock signal is in a low level state, its own moving end is connected to its own second fixed end;

[0114] The moving end of the fourth controllable switch S4 is connected to the first end of the fifth capacitor unit C5 and the first end of the sixth capacitor unit C6 respectively, the first fixed end of the fourth controllable switch S4 is connected to the power supply, the second fixed end of the fourth controllable switch S4 is grounded, and the control end of the fourth controllable switch S4 is connected to the output end of the second inverter IC2, and is configured to control its own moving end to be connected to its own first fixed end or its own second fixed end according to the level state of the fourth clock signal; wherein, when the fourth clock signal is in a high level state, its own moving end is connected to its own first fixed end, and when the fourth clock signal is in a low level state, its own moving end is connected to its own second fixed end;

[0115] A first end of the fifth controllable switch S5 is connected to the second end of the resistor unit R0, a second end of the fifth controllable switch S5 is connected to the second end of the fourth capacitor unit C4, a control end of the fifth controllable switch S5 is connected to the first output end of the first-stage charge pump 1011, and is configured to enter a corresponding switch state according to the level state of the third voltage signal; wherein, when the third voltage signal is in a high level state, the switch enters a conduction state, and when the third voltage signal is in a low level state, the switch enters an off state;

[0116] A first end of the sixth controllable switch S6 is connected to the second end of the resistor unit R0, a second end of the sixth controllable switch S6 is connected to the second end of the third capacitor unit C3, a control end of the sixth controllable switch S6 is connected to the first output end of the first-stage charge pump 1011, and is configured to enter a corresponding switch state according to the level state of the third voltage signal; wherein, when the third voltage signal is in a high level state, the switch enters a conduction state, and when the third voltage signal is in a low level state, the switch enters an off state;

[0117] A first end of the seventh controllable switch S7 is connected to the second end of the resistor unit R0, a second end of the seventh controllable switch S7 is connected to the second end of the sixth capacitor unit C6, a control end of the seventh controllable switch S7 is connected to the second output end of the first-stage charge pump 1011, and is configured to enter a corresponding switch state according to the level state of the fourth voltage signal; wherein, when the fourth voltage signal is in a high level state, the switch enters a conduction state, and when the fourth voltage signal is in a low level state, the switch enters an off state;

[0118] A first end of the eighth controllable switch S8 is connected to the second end of the resistor unit R0, a second end of the eighth controllable switch S8 is connected to the second end of the fifth capacitor unit C5, a control end of the eighth controllable switch S8 is connected to the second output end of the first-stage charge pump 1011, and is configured to enter a corresponding switch state according to the level state of the fourth voltage signal; wherein, when the fourth voltage signal is in a high level state, the switch enters a conduction state, and when the fourth voltage signal is in a low level state, the switch enters an off state;

[0119] A common connection terminal of the fifth controllable switch S5 and the fourth capacitor unit C4 constitutes a first output terminal of the second-stage charge pump, and is configured to output a fifth voltage signal;

[0120] A common connection terminal of the sixth controllable switch S6 and the third capacitor unit C3 constitutes a second output terminal of the second-stage charge pump, and is configured to output a sixth voltage signal;

[0121] The common connection terminal of the seventh controllable switch S7 and the sixth capacitor unit C6 constitutes the third output terminal of the second-stage charge pump, and is configured to output a seventh voltage signal;

[0122] The common connection terminal of the eighth controllable switch S8 and the fifth capacitor unit C5 constitutes the fourth output terminal of the second-stage charge pump, and is configured to output an eighth voltage signal.

[0123] In detail, the third and fourth controllable switches still need the previous clock signal for control, but due to the circuit logic relationship, we need to introduce the first inverter and the second inverter respectively to invert the clock signal, and finally obtain the third clock signal and the fourth clock signal, which act on the third controllable switch and the fourth controllable switch respectively, and the third voltage signal output by the first-stage charge pump acts on the fifth controllable switch and the sixth controllable switch, and the fourth voltage signal output by the first-stage charge pump acts on the seventh controllable switch and the eighth controllable switch. By making the third capacitor unit, the fourth capacitor unit, the fifth capacitor unit and the sixth capacitor unit complete voltage bootstrapping, the clock high level is finally raised to 2*AVDD18-vsw, the low level is raised to AVDD18-vsw, and output to the subsequent switching circuit, where vsw is the voltage drop through the third, fourth, fifth and sixth controllable switches.

[0124] Specifically, taking the upper part of the second-stage charge pump as an example, the inverted clock signal is in phase with the voltage signal output by the first-stage charge pump. When both signals are high, the lower end of the capacitor is grounded, and the fifth and sixth controllable switches above are turned on accordingly, and the capacitor is charged to AVDD18-vsw. In the next state, when both signals are low, the voltage is bootstrapped to 2*AVDD18-vsw, and finally a signal with a high level of 2*AVDD18-vsw and a low level of AVDD18-vsw is output.

[0125] This embodiment also provides a circuit schematic diagram of a switch circuit in a charge pump circuit in a charge pump voltage stabilization circuit. Figure 8 .

[0126] like Figure 8 As shown, in one embodiment, the switch circuit includes a first transmission gate TG1 and a second transmission gate TG2;

[0127] The input end of the first transmission gate TG1 is connected to the first output end of the second-stage charge pump, the first control end of the first transmission gate TG1 is connected to the second output end of the second-stage charge pump, the second control end of the first transmission gate TG1 is connected to the fourth output end of the second-stage charge pump, and the first transmission gate TG1 is configured to enter a corresponding transmission state according to the level state of the sixth voltage signal and the level state of the eighth voltage signal; wherein, when the sixth voltage signal is in a high level state and the eighth voltage signal is in a low level state, the first transmission gate TG1 is turned on and outputs a fifth voltage signal;

[0128] The input end of the second transmission gate TG2 is connected to the third output end of the second-stage charge pump, the first control end of the second transmission gate TG2 is connected to the second output end of the second-stage charge pump, the second control end of the second transmission gate TG2 is connected to the fourth output end of the second-stage charge pump, and the second transmission gate TG2 is configured to enter a corresponding transmission state according to the level state of the sixth voltage signal and the level state of the eighth voltage signal; wherein, when the sixth voltage signal is in a low level state and the eighth voltage signal is in a high level state, the second transmission gate TG2 is turned on and outputs the seventh voltage signal;

[0129] The output end of the first transmission gate TG1 is connected to the output end of the second transmission gate TG2 , and together constitutes an output end of the charge pump circuit, which is configured to output a driving voltage according to the fifth voltage signal and the seventh voltage signal.

[0130] In detail, the signal output by the second-stage charge pump is integrated with the first transmission gate and the second transmission gate to obtain a stable voltage, which is also the bias voltage provided for the load-stage circuit. Specifically, when the fifth voltage signal received by the input end of the first transmission gate is high, the sixth voltage signal used to control the first transmission gate is high, and the eighth voltage signal is low. At this time, the transmission gate is turned on and a high-level fifth voltage signal 2*AVDD-vsw-v_tgate is output, where v_tgate is the voltage drop across the transmission gate. At this time, the state of the second transmission gate is opposite to that of the first transmission gate and is in the off state; in the corresponding next state, the first transmission gate is turned off, the second transmission gate is turned on, and the second transmission gate outputs the seventh voltage signal 2*AVDD-vsw-v_tgate. Finally, the entire charge pump circuit will output a stable VCP=2*AVDD-vsw-v_tgate, providing sufficient bias voltage for the load-stage circuit.

[0131] In a first aspect, the present embodiment provides a circuit schematic diagram of a filter circuit in a charge pump voltage stabilization circuit. Fig. 9 .

[0132] In one embodiment, the filter circuit 2011 includes a filter resistor RL and a filter capacitor CL;

[0133] The first end of the filter resistor RL is connected to the output end of the negative feedback loop, the second end of the filter resistor EL is connected to the first end of the filter capacitor RL, and the second end of the filter capacitor RL is grounded; wherein the common connection end of the filter resistor RL and the filter capacitor CL constitutes the output end of the filter circuit 2011, which is configured to output the filtered bias voltage.

[0134] It can be understood that, on the one hand, the filtering circuit realizes the function of providing multiple low-voltage power supplies with a certain degree of noise isolation performance by a single negative feedback network. When the load current changes, the voltage provided to the load circuit will change slightly, but the power tube current inside the regulator will not be drawn, so that the negative feedback loop state is stable.

[0135] The first aspect of the present embodiment also provides a circuit schematic diagram of a load circuit in a charge pump voltage stabilization circuit. Fig.10 .

[0136] In one embodiment, the load circuit 2012 includes an adjustment module 2012a and a load module 2012b;

[0137] The input end of the adjustment module 2012a is connected to the output end of the filter circuit 2011, and the output end of the adjustment module 2012a is connected to the load module 2012b. The adjustment module 2012a is configured to adjust the bias voltage to obtain a load voltage and output the load voltage to the load module 2012b.

[0138] It can be understood that the adjustment module generates a corresponding load voltage based on the bias voltage according to the actual load module's demand for the load voltage, and supplies power to the load module.

[0139] This embodiment also provides a detailed circuit schematic diagram of a load circuit in a charge pump voltage stabilization circuit; for details, see Fig.11 .

[0140] In one embodiment, the adjustment module 2012a includes a first transistor MN1 and a second transistor MN2, and the load module 2012b includes a load capacitor CF and a load unit Load1;

[0141] The control end of the first transistor MN1 is connected to the output end of the filter circuit 2011, the input end of the first transistor MN1 is connected to the power supply, and the output end of the first transistor MN1 is connected to the input end of the second transistor MN2;

[0142] The output end of the second transistor MN2 is respectively connected to the first end of the load capacitor CF and the first end of the load unit Load1, and the control end of the second transistor MN2 is respectively connected to the second end of the load capacitor CF and the second end of the load unit Load1, and is configured to generate and output a load voltage Vo1 based on a bias voltage to power the load unit Load1.

[0143] It can be understood that the transistor in the embodiment is an NMOS tube, and the voltage adjustment is mainly performed by the second transistor. Assuming that the gate-source voltage of the second transistor in the first load level is vgs1, the voltage Vo1 received by the corresponding load unit Load1 is Vg-vgs1. Correspondingly, if the gate-source voltage of the corresponding second transistor in the second load level is Vgs2, the voltage Vo2 received by the corresponding load unit Load2 is Vg-vgs2. By analogy, different load levels can obtain different isolated load voltages through separate settings.

[0144] In summary, the charge pump voltage stabilization circuit in the embodiment of the present application includes a negative feedback loop and a load stage circuit, the negative feedback loop includes a charge pump circuit and a voltage stabilization circuit, the load stage circuit includes at least one load stage, each of the load stages includes a corresponding filter circuit and a load circuit, the voltage stabilization circuit provides a bias voltage under the action of the charge pump, and the corresponding filter circuit in each load stage filters the bias voltage to ensure the noise isolation function between different load stages, and the corresponding load circuit generates and outputs a load voltage based on the filtered bias voltage, which is used to provide a load voltage for subsequent circuits. In summary, the present application provides a bias voltage to the load stage circuit through a single negative feedback loop, and generates multiple isolated load voltages on multiple load stages, which can effectively simplify the voltage stabilization circuit structure in the relevant analog circuit system.

[0145] Fig.12 A schematic diagram of a chip provided in the second aspect of an embodiment of the present application is shown, wherein the chip A includes a charge pump voltage stabilizing circuit 01 as described in any one of the above items.

[0146] Fig.13 A schematic diagram of an electronic device provided in the third aspect of an embodiment of the present application is shown, wherein the electronic device B includes a charge pump voltage stabilizing circuit 01 as described in any one of the above items.

[0147] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0148] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0149] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A charge pump voltage stabilizing circuit, characterized in that: It includes a negative feedback loop and a load stage circuit, wherein the negative feedback loop includes a charge pump circuit and a voltage stabilizing circuit, the load stage circuit includes at least one load stage, and each load stage includes a corresponding filter circuit and a load circuit; The negative feedback loop is configured to generate and output a bias voltage based on the charge pump circuit and the voltage regulator circuit; The filter circuit is connected to the negative feedback loop and is configured to filter the bias voltage and output it to the load circuit in the same load stage; The load circuit is connected to the filter circuit in the same load stage, and is configured to generate and output a load voltage according to the filtered bias voltage.

2. The charge pump voltage stabilizing circuit according to claim 1, characterized in that: The voltage stabilizing circuit includes an operational amplifier and a negative feedback network; The charge pump circuit is configured to generate a driving voltage based on an externally input clock signal and output the driving voltage to the operational amplifier; The negative feedback network is configured to generate a feedback voltage based on the bias voltage and output the feedback voltage to the operational amplifier; The non-inverting input terminal of the operational amplifier receives an input voltage, the inverting input terminal of the operational amplifier is connected to the output terminal of the negative feedback network, the output terminal of the operational amplifier is connected to the input terminal of the negative feedback network, and the operational amplifier is configured to generate and output the bias voltage based on the input voltage and the feedback voltage under the drive of the driving voltage.

3. The charge pump voltage stabilizing circuit according to claim 2, characterized in that: The negative feedback network includes an electronic switch tube, a first negative feedback resistor and a second negative feedback resistor; The control end of the electronic switch tube is connected to the output end of the operational amplifier, the input end of the electronic switch tube is connected to the power supply, and the output end of the electronic switch tube is connected to the first end of the first negative feedback resistor; wherein the control end of the electronic switch tube constitutes the input end of the negative feedback network; The second end of the first negative feedback resistor is connected to the first end of the second negative feedback resistor, and the second end of the second resistor is grounded; The second end of the first negative feedback resistor is connected to the first end of the second negative feedback resistor; wherein the common connection end of the first negative feedback resistor and the second negative feedback resistor constitutes the output end of the negative feedback network.

4. The charge pump voltage stabilizing circuit according to claim 2, characterized in that: The charge pump circuit comprises a first-stage charge pump, a second-stage charge pump and a switch circuit; The first-stage charge pump is configured to generate and output a first voltage signal based on a power supply voltage and the clock signal; The second-stage charge pump is configured to generate and output a second voltage signal based on a power supply voltage, the clock signal and the first voltage signal; The switch circuit is configured to generate the driving voltage based on the second voltage signal and output the driving voltage to the operational amplifier.

5. The charge pump voltage stabilizing circuit according to claim 4, characterized in that: The first-stage charge pump includes a clock signal processing unit, a first controllable switch, a second controllable switch, a resistance unit, a first capacitance unit, a second capacitance unit, a first diode and a second diode, and the first voltage signal includes a third voltage signal and a fourth voltage signal; The clock signal processing unit is configured to generate and output a first clock signal and a second clock signal based on the clock signal; wherein the first clock signal is inversely proportional to the second clock signal; The moving end of the first controllable switch is connected to the first end of the first capacitor unit, the first fixed end of the first controllable switch is connected to the power supply, the second fixed end of the first controllable switch is grounded, and the control end of the first controllable switch is connected to the first output end of the clock signal processing unit, and is configured to control its own moving end to be connected to its own first fixed end or its own second fixed end according to the level state of the first clock signal; wherein, when the first clock signal is in a high level state, its own moving end is connected to its own first fixed end, and when the first clock signal is in a low level state, its own moving end is connected to its own second fixed end; The moving end of the second controllable switch is connected to the first end of the second capacitor unit, the first fixed end of the second controllable switch is connected to the power supply, the second fixed end of the second controllable switch is grounded, and the control end of the second controllable switch is connected to the second output end of the clock signal processing unit, and is configured to control its own moving end to be connected to its own first fixed end or its own second fixed end according to the level state of the second clock signal; wherein, when the second clock signal is in a high level state, its own moving end is connected to its own first fixed end, and when the second clock signal is in a low level state, its own moving end is connected to its own second fixed end; A first end of the resistance unit is connected to the power supply, and a second end of the resistance unit is connected to a first end of the first diode and a second end of the second diode respectively; The second end of the first diode is connected to the second end of the first capacitor unit; wherein the common connection end of the first diode and the first capacitor unit constitutes the first output end of the first-stage charge pump, and is configured to output the third voltage signal; The second end of the second diode is connected to the second end of the second capacitor unit; wherein the common connection end of the second diode and the second capacitor unit constitutes the second output end of the first-stage charge pump, which is configured to output the fourth voltage signal.

6. The charge pump voltage stabilizing circuit according to claim 5, characterized in that: The second-stage charge pump includes a first inverter, a second inverter, a third controllable switch, a fourth controllable switch, a fifth controllable switch, a sixth controllable switch, a seventh controllable switch, an eighth controllable switch, a third capacitor unit, a fourth capacitor unit, a fifth capacitor unit and a sixth capacitor unit, and the second voltage signal includes a fifth voltage signal, a sixth voltage signal, a seventh voltage signal and an eighth voltage signal; The input terminal of the first inverter is connected to the first output terminal of the clock signal processing unit, and is configured to generate and output a third clock signal based on the first clock signal; The input terminal of the second inverter is connected to the second output terminal of the clock signal processing unit, and is configured to generate and output a fourth clock signal based on the second clock signal; The moving end of the third controllable switch is connected to the first end of the third capacitor unit and the first end of the fourth capacitor unit respectively, the first fixed end of the third controllable switch is connected to the power supply, the second fixed end of the third controllable switch is grounded, and the control end of the third controllable switch is connected to the output end of the first inverter, and is configured to control its own moving end to be connected to its own first fixed end or its own second fixed end according to the level state of the third clock signal; wherein, when the third clock signal is in a high level state, its own moving end is connected to its own first fixed end, and when the third clock signal is in a low level state, its own moving end is connected to its own second fixed end; The moving end of the fourth controllable switch is respectively connected to the first end of the fifth capacitor unit and the first end of the sixth capacitor unit, the first fixed end of the fourth controllable switch is connected to the power supply, the second fixed end of the fourth controllable switch is grounded, and the control end of the fourth controllable switch is connected to the output end of the second inverter, and is configured to control its own moving end to be connected to its own first fixed end or its own second fixed end according to the level state of the fourth clock signal; wherein, when the fourth clock signal is in a high level state, its own moving end is connected to its own first fixed end, and when the fourth clock signal is in a low level state, its own moving end is connected to its own second fixed end; The first end of the fifth controllable switch is connected to the second end of the resistor unit, the second end of the fifth controllable switch is connected to the second end of the fourth capacitor unit, and the control end of the fifth controllable switch is connected to the first output end of the first-stage charge pump, and is configured to enter a corresponding switch state according to the level state of the third voltage signal; wherein, when the third voltage signal is in a high level state, it enters a conducting state, and when the third voltage signal is in a low level state, it enters an off state; The first end of the sixth controllable switch is connected to the second end of the resistor unit, the second end of the sixth controllable switch is connected to the second end of the third capacitor unit, and the control end of the sixth controllable switch is connected to the first output end of the first-stage charge pump, and is configured to enter a corresponding switch state according to the level state of the third voltage signal; wherein, when the third voltage signal is in a high level state, it enters a conducting state, and when the third voltage signal is in a low level state, it enters an off state; The first end of the seventh controllable switch is connected to the second end of the resistor unit, the second end of the seventh controllable switch is connected to the second end of the sixth capacitor unit, and the control end of the seventh controllable switch is connected to the second output end of the first-stage charge pump, and is configured to enter a corresponding switch state according to the level state of the fourth voltage signal; wherein, when the fourth voltage signal is in a high level state, it enters a conducting state, and when the fourth voltage signal is in a low level state, it enters an off state; The first end of the eighth controllable switch is connected to the second end of the resistor unit, the second end of the eighth controllable switch is connected to the second end of the fifth capacitor unit, and the control end of the eighth controllable switch is connected to the second output end of the first-stage charge pump, and is configured to enter a corresponding switch state according to the level state of the fourth voltage signal; wherein, when the fourth voltage signal is in a high level state, it enters a conducting state, and when the fourth voltage signal is in a low level state, it enters an off state; The common connection terminal of the fifth controllable switch and the fourth capacitor unit constitutes a first output terminal of the second-stage charge pump, and is configured to output the fifth voltage signal; The common connection terminal of the sixth controllable switch and the third capacitor unit constitutes a second output terminal of the second-stage charge pump, and is configured to output the sixth voltage signal; A common connection terminal of the seventh controllable switch and the sixth capacitor unit constitutes a third output terminal of the second-stage charge pump, and is configured to output the seventh voltage signal; A common connection terminal of the eighth controllable switch and the fifth capacitor unit constitutes a fourth output terminal of the second-stage charge pump, and is configured to output the eighth voltage signal.

7. The charge pump voltage stabilizing circuit according to claim 6, characterized in that: The switch circuit includes a first transmission gate and a second transmission gate; The input end of the first transmission gate is connected to the first output end of the second-stage charge pump, the first control end of the first transmission gate is connected to the second output end of the second-stage charge pump, the second control end of the first transmission gate is connected to the fourth output end of the second-stage charge pump, and the first transmission gate is configured to enter a corresponding transmission state according to the level state of the sixth voltage signal and the level state of the eighth voltage signal; wherein, when the sixth voltage signal is in a high level state and the eighth voltage signal is in a low level state, the first transmission gate is turned on and outputs the fifth voltage signal; The input terminal of the second transmission gate is connected to the third output terminal of the second-stage charge pump, the first control terminal of the second transmission gate is connected to the second output terminal of the second-stage charge pump, the second control terminal of the second transmission gate is connected to the fourth output terminal of the second-stage charge pump, and the second transmission gate is configured to enter a corresponding transmission state according to the level state of the sixth voltage signal and the level state of the eighth voltage signal; wherein, when the sixth voltage signal is in a low level state and the eighth voltage signal is in a high level state, the second transmission gate is turned on and outputs the seventh voltage signal; The output end of the first transmission gate is connected to the output end of the second transmission gate, and together constitutes the output end of the charge pump circuit, which is configured to output the driving voltage according to the fifth voltage signal and the seventh voltage signal.

8. The charge pump voltage stabilizing circuit according to claim 1, characterized in that: The filter circuit includes a filter resistor and a filter capacitor; The first end of the filter resistor is connected to the output end of the negative feedback loop, the second end of the filter resistor is connected to the first end of the filter capacitor, and the second end of the filter capacitor is grounded; wherein the common connection end of the filter resistor and the filter capacitor constitutes the output end of the filter circuit, and is configured to output the bias voltage after filtering.

9. The charge pump voltage stabilizing circuit according to claim 8, characterized in that: The load circuit includes an adjustment module and a load module; The input end of the adjustment module is connected to the output end of the filter circuit, and the output end of the adjustment module is connected to the load module. The adjustment module is configured to adjust the bias voltage to obtain a load voltage and output the load voltage to the load module.

10. The charge pump voltage stabilizing circuit according to claim 9, characterized in that: The adjustment module includes a first transistor and a second transistor, and the load module includes a load capacitor and a load unit; The control end of the first transistor is connected to the output end of the filter circuit, the input end of the first transistor is connected to the power supply, and the output end of the first transistor is connected to the input end of the second transistor; The output end of the second transistor is respectively connected to the first end of the load capacitor and the first end of the load unit, and the control end of the second transistor is respectively connected to the second end of the load capacitor and the second end of the load unit, and is configured to generate and output the load voltage based on the bias voltage to power the load unit.

11. A chip, characterized in that: The chip includes the charge pump voltage stabilization circuit as claimed in any one of claims 1 to 10.

12. An electronic device, characterized in that: The electronic device comprises the charge pump voltage stabilizing circuit as claimed in any one of claims 1 to 10.

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