Impedance calibration circuit of multi-path 1T1R resistance network and impedance calibration method thereof

Abstract

The invention relates to the technical field of integrated circuits, and provides an impedance calibration circuit of a multi-path 1T1R resistance network and an impedance calibration method thereof, the impedance calibration circuit of the multi-path 1T1R resistance network comprises a positive electrode impedance calibration module, a negative electrode impedance calibration module, a user impedance calibration module and a DCI adjusting module, and is characterized in that the positive electrode impedance calibration module, the negative electrode impedance calibration module, the user impedance calibration module and the DCI adjusting module are connected in series. Each of the positive impedance calibration module, the negative impedance calibration module and the user impedance calibration module comprises a multi-path RRAM network structure; the RRAM network structure is composed of a plurality of branch RRAM structures; the branch RRAM structure is composed of a plurality of improved RRAM units, and each improved RRAM unit is composed of a transistor and an RRAM unit which are connected in series. In the impedance calibration circuit, the complexity of resistance distribution can be reduced, and the adaptability of the circuit to various impedance calibration algorithms is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to an impedance calibration circuit of a multi-channel 1T1R resistor network and an impedance calibration method thereof. Background Art

[0002] Nowadays, the output transmission rate of integrated circuits is getting higher and higher, and the data throughput is getting larger and larger. The IO interface circuit serves as a bridge for data interaction between FPGA chips and peripheral circuits. Its circuit performance and the quality of transmitted signals are one of the important indicators of the chip. During the high-speed transmission of signals, in order to reduce signal reflections in different transmission media, impedance matching technology is performed at the signal output end or receiving end to ensure that the signal can be transmitted to the load without distortion.

[0003] Nowadays, most of the related technical fields use digitally controlled impedance (DCI) technology to adjust the IO impedance by selectively turning on or off the transistors in the IO to adjust the impedance to match the external reference resistor. The general implementation method of the resistor network in DCI is to distribute the resistor width-to-length ratio or the number of resistors in parallel to 1, 2, 4, ..., 2n-1, 2n. This resistor network not only occupies a large area in the integrated circuit, but also has a high complexity in resistor distribution, and it is difficult to improve the circuit structure to adapt to various matching algorithms. Summary of the invention

[0004] The present invention provides an impedance calibration circuit of a multi-channel 1T1R resistor network, the main purpose of which is to reduce the complexity of resistor distribution in the impedance calibration circuit and improve the adaptability of the circuit to various impedance calibration algorithms.

[0005] To achieve the above object, the present invention provides an impedance calibration circuit of a multi-channel 1T1R resistor network, comprising a positive impedance calibration module, a negative impedance calibration module, a user impedance calibration module and a DCI adjustment module, characterized in that the positive impedance calibration module, the negative impedance calibration module and the user impedance calibration module all contain a multi-channel RRAM network structure; The RRAM network structure comprises a plurality of branch RRAM structures; The branch RRAM structure is composed of a plurality of improved RRAM cells, wherein the improved RRAM cell is composed of a transistor and a RRAM cell connected in series.

[0006] In addition, the DCI adjustment module includes a preset rule and a preset calibration algorithm.

[0007] In addition, the RRAM network structure includes: Using the preset rule, adjusting the resistance value of each branch RRAM structure in the RRAM network structure; According to the preset calibration algorithm, an update rule of each of the RRAM network structures is configured, wherein the update rule represents a switching rule of each transistor of each branch RRAM structure in each RRAM network structure.

[0008] In addition, the positive electrode impedance calibration module includes: The positive impedance calibration module is composed of a default voltage source, a ground line, a reference potential interface, a transistor, a multi-channel RRAM network structure, a PAD connector, a post-stage comparator and a precise matching resistor connection; The RRAM network structure of each path is pulled up and connected to the default voltage source, and the other end of the RRAM network structure is connected to the PAD connector; One end of the precise matching resistor is connected to the ground wire, and the other end of the precise matching resistor is connected to the PAD connector; The first input interface of the post-stage comparator is connected to the PAD connector, the second input interface of the post-stage comparator is connected to the reference potential interface, and the output interface of the post-stage comparator is connected to the DCI adjustment module; The transistors are distributed at both ends of the RRAM network structure, and are used to control the on-off state of the RRAM network structure in the positive electrode impedance calibration module; The positive electrode impedance calibration module is used to adjust the connection state of the resistors in the RRAM network structure to obtain a positive electrode impedance adjustment signal, wherein the positive electrode impedance adjustment signal is the switch state of each transistor in the multi-channel RRAM network structure.

[0009] In addition, the negative electrode impedance calibration module includes: The negative electrode impedance calibration module is composed of the default voltage source, the ground line, the reference potential interface, the PAD connector, a second transistor, a multi-channel second RRAM network structure, a second post-stage comparator and a second precise matching resistor connection; The second RRAM network structure of each path is pulled down and connected to the ground line, and the other end of the RRAM network structure is connected to the PAD connector; One end of the second precise matching resistor is connected to the default voltage source, and the other end of the second precise matching resistor is connected to the PAD connector; The first input interface of the second post-stage comparator is connected to the PAD connector, the second input interface of the post-stage comparator is connected to the reference potential interface, and the output interface of the second post-stage comparator is connected to the DCI adjustment module; The second transistor is distributed to both ends of the second RRAM network structure, and is used to control the on-off state of the second RRAM network structure in the negative electrode impedance calibration module; The negative electrode impedance calibration module is used to adjust the connection state of the resistors in the RRAM network structure to obtain a negative electrode impedance adjustment signal, wherein the negative electrode impedance adjustment signal is the switch state of each second transistor in the multi-channel second RRAM network structure.

[0010] In addition, the DCI adjustment module includes: The DCI adjustment module is used to determine whether the positive impedance calibration module needs to perform an adjustment operation on the resistance connection state according to the output result of the post-stage comparator; The DCI adjustment module is further used to determine whether the negative electrode impedance calibration module needs to perform an adjustment operation on the resistance connection state according to the output result of the second post-stage comparator.

[0011] In addition, the user impedance calibration module includes: Each route in the user impedance calibration module is obtained by sequentially connecting the default voltage source, the transistor, the RRAM network structure, the transistor, the second transistor, the second RRAM network structure, the second transistor and the ground line; The user impedance calibration module is used to obtain the positive impedance adjustment signal of the positive impedance calibration module and the negative impedance adjustment signal of the negative impedance calibration module when the DCI adjustment module determines that the positive impedance calibration module and the negative impedance calibration module do not need to perform an adjustment operation of the resistance connection state; According to the positive impedance adjustment signal and the negative impedance adjustment signal, a circuit network obtained by connecting the RRAM network structure and the second RRAM network structure in parallel is assigned a value based on a resistor connection state to obtain a matching external resistance value.

[0012] In addition, the preset rule is a binary arrangement, and the preset calibration algorithm is a dichotomy method.

[0013] To achieve the above object, the present invention further provides an impedance calibration method for a multi-channel 1T1R resistor network, characterized in that the method comprises: According to a pre-constructed DCI calibration rule, adjusting the connection state of the resistors in the pre-constructed RRAM network structure to obtain a positive impedance adjustment signal, and adjusting the connection state of the resistors in the pre-constructed second RRAM network structure to obtain a negative impedance adjustment signal, wherein the DCI calibration rule includes a preset calibration algorithm and a preset rule; According to the positive impedance adjustment signal and the negative impedance adjustment signal, a circuit network obtained by connecting the RRAM network structure and the second RRAM network structure in parallel is assigned a value based on a resistor connection state to obtain a matching external resistance value.

[0014] In addition, the method of adjusting the connection state of the resistors in the pre-constructed RRAM network structure according to the pre-constructed DCI calibration rule to obtain a positive impedance adjustment signal, and adjusting the connection state of the resistors in the pre-constructed second RRAM network structure to obtain a negative impedance adjustment signal, includes: Using a preset rule in a pre-built DCI calibration rule, the resistance value of each branch RRAM structure in the RRAM network structure in the positive impedance calibration module is adjusted to obtain an initialization positive impedance adjustment signal; According to a preset calibration algorithm in a pre-built DCI calibration rule, an update rule of the RRAM network structure is configured to obtain a positive electrode update rule; According to the positive electrode update rule, the initialized positive electrode impedance adjustment signal is iteratively updated to obtain a positive electrode impedance adjustment signal; Using the preset rules in the DCI calibration rules, the resistance value of each branch RRAM structure in the RRAM network structure in the negative electrode impedance calibration module is adjusted to obtain an initialization negative electrode impedance adjustment signal; According to the preset calibration algorithm in the DCI calibration rule, the update rule of the RRAM network structure in the negative electrode impedance calibration module is configured to obtain the negative electrode update rule, wherein the positive electrode update rule and the negative electrode update rule both represent the switching rule of each transistor of each branch RRAM structure; According to the negative electrode update rule, the initialized negative electrode impedance adjustment signal is iteratively updated to obtain a negative electrode impedance adjustment signal.

[0015] The present invention solves the problem described in the background technology. The present invention proposes to replace the resistor parallel structure in the traditional impedance calibration circuit with an RRAM network structure, wherein the RRAM network structure is composed of multiple branch RRAM structures. By configuring the transistor switch state in the branch, different branch RRAM structures can have different resistance values. However, the transistor switch state between each branch can be configured by different update algorithms, such as binary division, so as to better coordinate the access of each branch RRAM structure, so that the impedance calibration circuit has the advantage of flexible resistance update through different algorithms. In addition, replacing the traditional resistor parallel structure with the RRAM network structure can also optimize the occupied area of ​​the resistance adjustment part in the integrated circuit. Therefore, the present invention can reduce the complexity of the resistance distribution in the impedance calibration circuit and improve the adaptability of the circuit to various impedance calibration algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic diagram of the structure of an RRAM network structure in an impedance calibration circuit of a multi-channel 1T1R resistor network provided by an embodiment of the present invention; Figure 2A A schematic diagram of the structure of impedance calibration of a multi-channel 1T1R resistor network with reference to IO on the P side in an impedance calibration circuit of a multi-channel 1T1R resistor network provided by an embodiment of the present invention; Figure 2B A schematic diagram of the structure of impedance calibration of a multi-channel 1T1R resistor network with reference to IO on the N side in an impedance calibration circuit of a multi-channel 1T1R resistor network provided by an embodiment of the present invention; Figure 2C A schematic diagram of the structure of impedance calibration of a multi-channel 1T1R resistor network with reference to IO on the user side in an impedance calibration circuit of a multi-channel 1T1R resistor network provided by an embodiment of the present invention; Figure 3A A waveform diagram of a binary matching algorithm of a multi-channel 1T1R impedance matching network with reference to IO on the N side in an impedance calibration circuit of a multi-channel 1T1R resistor network provided by an embodiment of the present invention; Figure 3B A waveform diagram of a binary matching algorithm of a multi-channel 1T1R impedance matching network with reference to IO on the P side in an impedance calibration circuit of a multi-channel 1T1R resistor network provided by an embodiment of the present invention; Figure 4 A schematic flow chart of an impedance calibration method for a multi-channel 1T1R resistor network provided in accordance with an embodiment of the present invention.

[0017] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present application more obvious, the exemplary embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the exemplary embodiments described here.

[0019] In this article, 1T1R refers to a series structure of 1 transistor and 1 RRAM cell.

[0020] An embodiment of the present application relates to an impedance calibration circuit of a multi-channel 1T1R resistor network, which mainly includes a positive impedance calibration module, a negative impedance calibration module, a user impedance calibration module and a DCI adjustment module, characterized in that the positive impedance calibration module, the negative impedance calibration module and the user impedance calibration module all include a multi-channel RRAM network structure; The RRAM network structure comprises a plurality of branch RRAM structures; The branch RRAM structure is composed of a plurality of improved RRAM cells, wherein the improved RRAM cell is composed of a transistor and a RRAM cell connected in series.

[0021] Among them, the RRAM is a new type of non-volatile memory. The more mature structure is the metal / semiconductor / metal MIM structure, which has a simple structure, low write voltage, fast read and write speed, and its biggest advantage is that it can store multiple resistance states and the states can be maintained for a long time.

[0022] Therefore, the RRAM network structure can be used as a dynamically adjustable resistor.

[0023] The DCI adjustment module refers to a functional block in the FPGA that adjusts the impedance to match the external reference resistor.

[0024] The FPGA is a programmable integrated circuit whose internal logic structure and connection relationship can be configured by programming according to user needs to realize various digital functions.

[0025] Since the matching resistor network in the existing technology is generally constructed using multiple parallel resistors or resistors with different width-to-length ratios, for example, the resistors are distributed according to the width-to-length ratios of 2nR, 2n-1R, ..., 4R, 2R, R or the parallel resistors are distributed as 1, 2, 4, ..., 2n-1, 2n. This type of resistor network is not only used in large numbers in integrated circuits and occupies a large area, but also this binary resistor network will limit the algorithm and is not flexible enough.

[0026] Therefore, the present invention replaces the matching resistor network with an RRAM network structure.

[0027] In detail, in an embodiment of the present invention, the RRAM network structure includes: Using the preset rule, adjusting the resistance value of each branch RRAM structure in the RRAM network structure; According to the preset calibration algorithm, an update rule of the RRAM network structure is configured, wherein the update rule represents a switching rule of each transistor of each branch RRAM structure.

[0028] In detail, in the embodiment of the present invention, the DCI adjustment module includes a preset rule and a preset calibration algorithm.

[0029] Specifically, in the embodiment of the present invention, the resistance of the matching resistor network is generally distributed according to the resistance width-to-length ratio of 2nR, 2n-1R, ..., 4R, 2R, R or the parallel resistance of 1, 2, 4, ..., 2^n-1, 2^n, and the present invention can complete the adjustment through a preset rule, for example, changing to 1, 4, 16, 64, ..., 4^n-1, 4^n. The modification can be completed by configuring the preset rule, which improves the flexibility of the resistance distribution.

[0030] Furthermore, by controlling the switches of the multi-channel RRAM network structure through transistors, the resistance can be updated not only by binary search but also by other algorithms during the calibration process.

[0031] Specifically, Figure 1 As shown, on the left is a pull-up network (RRAM_PU) of an RRAM network structure, and on the right is a pull-down network (RRAM_PD) of an RRAM network structure. This multi-branch 1T1R array combined in series and parallel can not only achieve precise resistance control, but also avoid read disturbance and ensure process consistency. The multi-branch 1T1RRAM resistor network structure can include (n+1)*(m+1) RRAMs, and the values ​​of n and m can be selected according to actual needs. The RRAM adjustment process is to cyclically send BL <0> and BLN <0> Between, BL <1> and BLN <1> Between, BL <2> and BLN <2> Between, BL <n>and BLN <n>The RRAM write signal between them (the updated column can be controlled by WL) until the multiple branch RRAM structures meet the matching requirements.

[0032] refer to Figure 2A , Figure 2B and Figure 2C It can be seen that the impedance calibration circuit of the present invention has a multi-channel structure.

[0033] Among them, VRP represents the P-side reference IO, VCCO represents the default voltage source, PMOS represents the transistor, RRAM-PU represents the pull-up RRAM network structure, Rref represents the precise matching resistor, PAD represents the PAD voltage on the PAD connector, and DCI_COMP represents the post-stage comparator.

[0034] Among them, RRAM-PD represents the second RRAM network structure pulled down, VRN represents the N-side reference IO, NMOS represents the second transistor on the N side, and the difference from VRP is that the second RRAM resistor network structure is connected to the ground line.

[0035] In detail, in the embodiment of the present invention, the positive electrode impedance calibration module includes: The positive impedance calibration module is composed of a default voltage source, a ground line, a reference potential interface, a transistor, a multi-channel RRAM network structure, a PAD connector, a post-stage comparator and a precise matching resistor connection; The RRAM network structure of each path is pulled up and connected to the default voltage source, and the other end of the RRAM network structure is connected to the PAD connector; One end of the precise matching resistor is connected to the ground wire, and the other end of the precise matching resistor is connected to the PAD connector; The first input interface of the post-stage comparator is connected to the PAD connector, the second input interface of the post-stage comparator is connected to the reference potential interface, and the output interface of the post-stage comparator is connected to the DCI adjustment module; The transistors are distributed at both ends of the RRAM network structure, and are used to control the on-off state of the RRAM network structure in the positive electrode impedance calibration module; The positive electrode impedance calibration module is used to adjust the connection state of the resistors in the RRAM network structure to obtain a positive electrode impedance adjustment signal, wherein the positive electrode impedance adjustment signal is the switch state of each transistor in the multi-channel RRAM network structure.

[0036] The precise matching resistor is used to provide a component with a fixed or adjustable precise resistance value.

[0037] The transistor is a component used to control the on and off of current in an electronic circuit. By changing the input signal, the transistor can switch between the two states of "on" (equivalent to a closed switch) and "off" (equivalent to an open switch).

[0038] The post-stage comparator refers to a component that receives a signal processed by a previous-stage circuit (such as a PAD voltage), compares the signal with a reference value or other input signal (such as a reference voltage VREF), and then outputs a high level or a low level (digital logic, 0 or 1) as a result.

[0039] Among them, the PAD connector refers to the input / output pin interface module on the FPGA chip, which is a direct interface between external signals and the internal logic of the FPGA. It can be understood that the PAD connector corresponds to the actual I / O pin (or solder ball).

[0040] In detail, in the embodiment of the present invention, the negative electrode impedance calibration module includes: The negative electrode impedance calibration module is composed of the default voltage source, the ground line, the reference potential interface, the PAD connector, a second transistor, a multi-channel second RRAM network structure, a second post-stage comparator and a second precise matching resistor connection; The second RRAM network structure of each path is pulled down and connected to the ground line, and the other end of the RRAM network structure is connected to the PAD connector; One end of the second precise matching resistor is connected to the default voltage source, and the other end of the second precise matching resistor is connected to the PAD connector; The first input interface of the second post-stage comparator is connected to the PAD connector, the second input interface of the post-stage comparator is connected to the reference potential interface, and the output interface of the second post-stage comparator is connected to the DCI adjustment module; The second transistor is distributed to both ends of the second RRAM network structure, and is used to control the on-off state of the second RRAM network structure in the negative electrode impedance calibration module; The negative electrode impedance calibration module is used to adjust the connection state of the resistors in the RRAM network structure to obtain a negative electrode impedance adjustment signal, wherein the negative electrode impedance adjustment signal is the switch state of each second transistor in the multi-channel second RRAM network structure.

[0041] In detail, in the embodiment of the present invention, the DCI adjustment module includes: The DCI adjustment module is used to determine whether the positive impedance calibration module needs to perform an adjustment operation on the resistance connection state according to the output result of the post-stage comparator; The DCI adjustment module is further used to determine whether the negative electrode impedance calibration module needs to perform an adjustment operation on the resistance connection state according to the output result of the second post-stage comparator.

[0042] In detail, in an embodiment of the present invention, the user impedance calibration module includes: Each route in the user impedance calibration module is obtained by sequentially connecting the default voltage source, the transistor, the RRAM network structure, the transistor, the second transistor, the second RRAM network structure, the second transistor and the ground line; The user impedance calibration module is used to obtain the positive impedance adjustment signal of the positive impedance calibration module and the negative impedance adjustment signal of the negative impedance calibration module when the DCI adjustment module determines that the positive impedance calibration module and the negative impedance calibration module do not need to perform an adjustment operation of the resistance connection state; According to the positive impedance adjustment signal and the negative impedance adjustment signal, a circuit network obtained by connecting the RRAM network structure and the second RRAM network structure in parallel is assigned a value based on a resistor connection state to obtain a matching external resistance value.

[0043] Specifically, in the embodiment of the present invention, the functions of the positive impedance calibration module, the negative impedance calibration module, the user impedance calibration module and the DCI adjustment module in the impedance calibration circuit are the same as those in the traditional impedance calibration circuit, and are not elaborated here.

[0044] However, in the embodiment of the present invention, the technical means of implementation are different. By designing a multi-channel RRAM network structure to replace the traditional parallel resistor network, a smaller footprint in the integrated circuit and a more flexible configuration means of the resistor distribution law and the resistor calibration algorithm can be achieved.

[0045] In detail, in the embodiment of the present invention, the preset rule is a binary arrangement, and the preset calibration algorithm is a dichotomy method.

[0046] refer to Figure 3A and 3B In the embodiment of the present invention, the preset rule of the traditional binary arrangement and the calibration algorithm of the dichotomy method are used to experiment with the impedance calibration circuit of the multi-channel 1T1R resistor network. The results show that by combining the digital signals of high and low levels with RRAM, the traditional impedance calibration circuit can be directly replaced with a smaller circuit footprint.

[0047] Specifically, in the embodiment of the present invention, the resistance adjustment of the multi-channel 1T1R resistor network is expressed as: Step 1: Taking n=6 as an example, you can Figure 2B During the calibration process, an external 64ohm (this value is only an example and has no limiting effect) reference resistor is used, VREF=1 / 2*VCCO; NMOS is turned off. <6> , to RRAM_PD <6> Tube input regulation signal; turn on NMOS <6> , compare the PAD voltage division with VREF in the comparator DCI_COMP; <6> Adjust the resistance to 64ohm and record the input RRAM_PD at this time <6> Then Figure 2C Turn off NMOS <6> ,Will Figure 2B Input RRAM_PD recorded in <6> The regulation signal of the tube is input to Figure 2C RRAM_PD in <6> tube, realize RRAM PD <6> Resistance adjustment; Step 2: Follow the above step 1 to update RRAM_PD<5:0> one by one, and adjust the resistance value of RRAM_PD<5:0> to 32ohm, 16ohm, 8ohm, 4ohm, 2ohm, and 1ohm respectively, and record Figure 2B The corresponding input RRAM_PD<5:0> tube adjustment signal is Figure 2C The corresponding NMOS<5:0> tube is turned off, and the corresponding adjustment signal is input into the RRAM_PD<5:0> of USERIO to adjust the resistance value of each RRAM_PD<5:0>.

[0048] Step 3: Figure 2A According to the above steps 1-2, gradually turn off the PMOS<6:0> tube, adjust the resistance value of RRAM_PU<6:0> to 64ohm, 32ohm, 16ohm, 8ohm, 4ohm, 2ohm, 1ohm respectively, and record Figure 2B The corresponding input RRAM_PU<6:0> tube adjustment signal is Figure 2C In the example, RRAM_PU<6:0> is updated in sequence, and the corresponding adjustment signal is input into RRAM_PU<6:0> of USERIO to adjust the resistance value of each RRAM_PU<6:0>.

[0049] After the resistance adjustment of each RRAM is completed, the resistance is determined, and the NMOS<6:0> tube and PMOS<6:0> tube switch can be used for impedance matching.

[0050] Specifically, in the embodiment of the present invention, the impedance matching process of the multi-channel RRAM network structure is expressed as: The embodiment here proposes a fast impedance calibration algorithm: binary method. The above binary RRAM network structure is used for impedance matching.

[0051] Figure 3A This is the waveform of the binary matching algorithm of the multi-channel 1T1R impedance matching network of the N-side reference IO. The matching starts from turning off all NMOS<6:0> tubes, detecting the PAD voltage through the comparator, and setting VREF=240mV (this value is only an experimental example and has no limiting effect): The first clock PAD voltage is equal to VCCO, and the DCI comparison result is 1, so it is fed back to the resistor network NMOS <6> =1; The next clock PAD voltage is equal to 630mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS <5> =1; The next clock PAD voltage is equal to 310mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS <4> =1; The next clock PAD voltage is equal to 150mV, and the DCI comparison result is still 0, so it is fed back to the resistor network NMOS <3> =0; The next clock PAD voltage is equal to 230mV, and the DCI comparison result is still 0, so it is fed back to the resistor network NMOS <2> =0; The next clock PAD voltage is equal to 270mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS <1> =1; The next clock PAD voltage is equal to 250mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS <0> =1; The next clock PAD voltage is equal to 240mV, and the matching is completed at this time.

[0052] The impedance can be accurately calibrated by using the binary method in only 7 clocks. In the embodiment, the 7 DCI comparison results are 1110011 respectively, and the result is fed back to the N-side NMOS<6:0> of USERIO.

[0053] Figure 3B The following is the waveform of the binary matching algorithm of the multi-channel 1T1R impedance matching network of the P-side reference IO. The matching starts from turning off all PMOS<6:0>, detecting the PAD voltage through the comparator, and setting VREF=1090mV (this value is only an experimental example and has no limiting effect): The first clock PAD voltage is equal to GND, and the DCI comparison result is 0, so it is fed back to the resistor network PMOS <6> =0; The next clock PAD voltage is equal to 640mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS <5> =0; The next clock PAD voltage is equal to 960mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS <4> =0; The next clock PAD voltage is equal to 1120mV, and the DCI comparison result is still 1, so it is fed back to the resistor network PMOS <3> =1; The next clock PAD voltage is equal to 1040mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS <2> =0; The next clock PAD voltage is equal to 1080mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS <1> =0; The next clock PAD voltage is equal to 1100mV, and the DCI comparison result is still 1, so it is fed back to the resistor network PMOS <0> =1; The next clock PAD voltage is equal to 1090mV, and the matching is completed at this time.

[0054] The impedance can be accurately calibrated by using the binary method in only 7 clocks. In the embodiment, the 7 DCI comparison results are 0001001 respectively, and the result is fed back to the P-side PMOS<6:0> of USERIO.

[0055] In completion Figure 3A and Figure 3B After the steps, at this time, the resistance values ​​of all RRAMs in USERIO have been adjusted, and the on and off states of the switches corresponding to each RRAM are also configured through the N-side NMOS<6:0> tube and the P-side PMOS<6:0> tube. At this time, the circuit completes impedance calibration.

[0056] The present invention solves the problem described in the background technology. The present invention proposes to replace the resistor parallel structure in the traditional impedance calibration circuit with an RRAM network structure, wherein the RRAM network structure is composed of multiple branch RRAM structures. By configuring the transistor switch state in the branch, different branch RRAM structures can have different resistance values. However, the transistor switch state between each branch can be configured by different update algorithms, such as binary division, so as to better coordinate the access of each branch RRAM structure, so that the impedance calibration circuit has the advantage of flexible resistance update through different algorithms. In addition, replacing the traditional resistor parallel structure with the RRAM network structure can also optimize the occupied area of ​​the resistance adjustment part in the integrated circuit. Therefore, the present invention can reduce the complexity of the resistance distribution in the impedance calibration circuit and improve the adaptability of the circuit to various impedance calibration algorithms.

[0057] Further, see Figure 4 As shown, the embodiment of the present invention also provides a method for utilizing Figure 1 The control method performed by the impedance calibration circuit of the multi-channel 1T1R resistor network shown includes: S1. According to a pre-constructed DCI calibration rule, adjusting the connection state of the resistors in the pre-constructed RRAM network structure to obtain a positive impedance adjustment signal, and adjusting the connection state of the resistors in the pre-constructed second RRAM network structure to obtain a negative impedance adjustment signal, wherein the DCI calibration rule includes a preset calibration algorithm and a preset rule; S2. According to the positive impedance adjustment signal and the negative impedance adjustment signal, an assignment operation based on a resistor connection state is performed on a circuit network obtained by connecting the RRAM network structure and the second RRAM network structure in parallel to obtain a matching external resistance value.

[0058] The DCI adjustment module refers to a functional block in the FPGA that adjusts the impedance to match the external reference resistor.

[0059] The FPGA is a programmable integrated circuit whose internal logic structure and connection relationship can be configured by programming according to user needs to realize various digital functions.

[0060] Among them, the RRAM is a new type of non-volatile memory. The more mature structure is the metal / semiconductor / metal MIM structure, which has a simple structure, low write voltage, fast read and write speed, and its biggest advantage is that it can store multiple resistance states and the states can be maintained for a long time.

[0061] Therefore, the RRAM network structure can be used as a dynamically adjustable resistor.

[0062] The DCI calibration rule includes a preset calibration algorithm and a preset rule.

[0063] Specifically, in the embodiment of the present invention, the resistance of the matching resistor network is generally distributed according to the resistance width-to-length ratio of 2nR, 2n-1R, ..., 4R, 2R, R or the parallel resistance of 1, 2, 4, ..., 2^n-1, 2^n, and the present invention can complete the adjustment through a preset rule, for example, changing to 1, 4, 16, 64, ..., 4^n-1, 4^n. The modification can be completed by configuring the preset rule, which improves the flexibility of the resistance distribution.

[0064] Furthermore, by controlling the switches of the multi-channel RRAM network structure through transistors, the resistance can be updated not only by binary search but also by other algorithms during the calibration process.

[0065] In detail, in an embodiment of the present invention, adjusting the connection state of the resistors in the pre-constructed RRAM network structure according to the pre-constructed DCI calibration rule to obtain a positive impedance adjustment signal, and adjusting the connection state of the resistors in the pre-constructed second RRAM network structure to obtain a negative impedance adjustment signal, includes: Using a preset rule in a pre-built DCI calibration rule, the resistance value of each branch RRAM structure in the RRAM network structure in the positive impedance calibration module is adjusted to obtain an initialization positive impedance adjustment signal; According to a preset calibration algorithm in a pre-built DCI calibration rule, an update rule of the RRAM network structure is configured to obtain a positive electrode update rule; According to the positive electrode update rule, the initialized positive electrode impedance adjustment signal is iteratively updated to obtain a positive electrode impedance adjustment signal; Using the preset rules in the DCI calibration rules, the resistance value of each branch RRAM structure in the RRAM network structure in the negative electrode impedance calibration module is adjusted to obtain an initialization negative electrode impedance adjustment signal; According to the preset calibration algorithm in the DCI calibration rule, the update rule of the RRAM network structure in the negative electrode impedance calibration module is configured to obtain the negative electrode update rule, wherein the positive electrode update rule and the negative electrode update rule both represent the switching rule of each transistor of each branch RRAM structure; According to the negative electrode update rule, the initialized negative electrode impedance adjustment signal is iteratively updated to obtain a negative electrode impedance adjustment signal.

[0066] Specifically, in the embodiment of the present invention, the step of adjusting the resistor connection state in the pre-constructed RRAM network structure according to the pre-constructed DCI calibration rule to obtain the positive impedance adjustment signal includes two parts: resistance adjustment and impedance matching.

[0067] Specifically, in the embodiment of the present invention, the resistance adjustment of the multi-channel 1T1R resistor network is expressed as: Step 1: Taking n=6 as an example, you can Figure 2B During the calibration process, an external 64ohm (this value is only an example and has no limiting effect) reference resistor is used, VREF=1 / 2*VCCO; NMOS is turned off. <6> , to RRAM_PD <6> Tube input regulation signal; turn on NMOS <6> , compare the PAD voltage division with VREF in the comparator DCI_COMP; <6> Adjust the resistance to 64ohm and record the input RRAM_PD at this time <6> Then Figure 2C Turn off NMOS <6> ,Will Figure 2B Input RRAM_PD recorded in <6> The regulation signal of the tube is input to Figure 2C RRAM_PD in <6> tube, realize RRAM PD <6> Resistance adjustment; Step 2: Follow the above step 1 to update RRAM_PD<5:0> one by one, and adjust the resistance value of RRAM_PD<5:0> to 32ohm, 16ohm, 8ohm, 4ohm, 2ohm, and 1ohm respectively, and record Figure 2B The corresponding input RRAM_PD<5:0> tube adjustment signal is Figure 2C The corresponding NMOS<5:0> tube is turned off, and the corresponding adjustment signal is input into the RRAM_PD<5:0> of USERIO to adjust the resistance value of each RRAM_PD<5:0>.

[0068] Step 3: Figure 2A According to the above steps 1-2, gradually turn off the PMOS<6:0> tube, adjust the resistance value of RRAM_PU<6:0> to 64ohm, 32ohm, 16ohm, 8ohm, 4ohm, 2ohm, 1ohm respectively, and record Figure 2B The corresponding input RRAM_PU<6:0> tube adjustment signal is Figure 2C In the example, RRAM_PU<6:0> is updated in sequence, and the corresponding adjustment signal is input into RRAM_PU<6:0> of USERIO to adjust the resistance value of each RRAM_PU<6:0>.

[0069] After the resistance adjustment of each RRAM is completed, the resistance is determined, and the NMOS<6:0> tube and PMOS<6:0> tube switch can be used for impedance matching.

[0070] Specifically, in the embodiment of the present invention, the impedance matching process of the multi-channel RRAM network structure is expressed as: The embodiment here proposes a fast impedance calibration algorithm: binary method. The above binary RRAM network structure is used for impedance matching.

[0071] Figure 3A This is the waveform of the binary matching algorithm of the multi-channel 1T1R impedance matching network of the N-side reference IO. The matching starts from turning off all NMOS<6:0> tubes, detecting the PAD voltage through the comparator, and setting VREF=240mV (this value is only an experimental example and has no limiting effect): The first clock PAD voltage is equal to VCCO, and the DCI comparison result is 1, so it is fed back to the resistor network NMOS <6> =1; The next clock PAD voltage is equal to 630mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS <5> =1; The next clock PAD voltage is equal to 310mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS <4> =1; The next clock PAD voltage is equal to 150mV, and the DCI comparison result is still 0, so it is fed back to the resistor network NMOS <3> =0; The next clock PAD voltage is equal to 230mV, and the DCI comparison result is still 0, so it is fed back to the resistor network NMOS <2> =0; The next clock PAD voltage is equal to 270mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS <1> =1; The next clock PAD voltage is equal to 250mV, and the DCI comparison result is still 1, so it is fed back to the resistor network NMOS <0> =1; The next clock PAD voltage is equal to 240mV, and the matching is completed at this time.

[0072] The impedance can be accurately calibrated by using the binary method in only 7 clocks. In the embodiment, the 7 DCI comparison results are 1110011 respectively, and the result is fed back to the N-side NMOS<6:0> of USERIO.

[0073] Figure 3B The following is the waveform of the binary matching algorithm of the multi-channel 1T1R impedance matching network of the P-side reference IO. The matching starts from turning off all PMOS<6:0>, detecting the PAD voltage through the comparator, and setting VREF=1090mV (this value is only an experimental example and has no limiting effect): The first clock PAD voltage is equal to GND, and the DCI comparison result is 0, so it is fed back to the resistor network PMOS <6> =0; The next clock PAD voltage is equal to 640mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS <5> =0; The next clock PAD voltage is equal to 960mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS <4> =0; The next clock PAD voltage is equal to 1120mV, and the DCI comparison result is still 1, so it is fed back to the resistor network PMOS <3> =1; The next clock PAD voltage is equal to 1040mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS <2> =0; The next clock PAD voltage is equal to 1080mV, and the DCI comparison result is still 0, so it is fed back to the resistor network PMOS <1> =0; The next clock PAD voltage is equal to 1100mV, and the DCI comparison result is still 1, so it is fed back to the resistor network PMOS <0> =1; The next clock PAD voltage is equal to 1090mV, and the matching is completed at this time.

[0074] The impedance can be accurately calibrated by using the binary method in only 7 clocks. In the embodiment, the 7 DCI comparison results are 0001001 respectively, and the result is fed back to the P-side PMOS<6:0> of USERIO.

[0075] In completion Figure 3A and Figure 3B After the steps, at this time, the resistance values ​​of all RRAMs in USERIO have been adjusted, and the on and off states of the switches corresponding to each RRAM are also configured through the N-side NMOS<6:0> tube and the P-side PMOS<6:0> tube. At this time, the circuit completes impedance calibration.

[0076] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.< / n> < / n>

Claims

1. An impedance calibration circuit for a multi-channel 1T1R resistor network, comprising a positive impedance calibration module, a negative impedance calibration module, a user impedance calibration module and a DCI adjustment module, characterized in that: The positive electrode impedance calibration module, the negative electrode impedance calibration module and the user impedance calibration module all include a multi-channel RRAM network structure; The RRAM network structure comprises a plurality of branch RRAM structures; The branch RRAM structure is composed of a plurality of improved RRAM cells, wherein the improved RRAM cell is composed of a transistor and a RRAM cell connected in series.

2. The impedance calibration circuit of a multi-channel 1T1R resistor network as claimed in claim 1, characterized in that: The DCI adjustment module includes a preset rule and a preset calibration algorithm.

3. The impedance calibration circuit of a multi-channel 1T1R resistor network as claimed in claim 2, characterized in that: The RRAM network structure comprises: Using the preset rule, adjusting the resistance value of each branch RRAM structure in the RRAM network structure; According to the preset calibration algorithm, an update rule of each of the RRAM network structures is configured, wherein the update rule represents a switching rule of each transistor of each branch RRAM structure in each RRAM network structure.

4. The impedance calibration circuit of a multi-channel 1T1R resistor network as claimed in claim 3, characterized in that: The positive electrode impedance calibration module includes: The positive impedance calibration module is composed of a default voltage source, a ground line, a reference potential interface, a transistor, a multi-channel RRAM network structure, a PAD connector, a post-stage comparator and a precise matching resistor connection; The RRAM network structure of each path is pulled up and connected to the default voltage source, and the other end of the RRAM network structure is connected to the PAD connector; One end of the precise matching resistor is connected to the ground wire, and the other end of the precise matching resistor is connected to the PAD connector; The first input interface of the post-stage comparator is connected to the PAD connector, the second input interface of the post-stage comparator is connected to the reference potential interface, and the output interface of the post-stage comparator is connected to the DCI adjustment module; The transistors are distributed at both ends of the RRAM network structure, and are used to control the on-off state of the RRAM network structure in the positive electrode impedance calibration module; The positive electrode impedance calibration module is used to adjust the connection state of the resistors in the RRAM network structure to obtain a positive electrode impedance adjustment signal, wherein the positive electrode impedance adjustment signal is the switch state of each transistor in the multi-channel RRAM network structure.

5. The impedance calibration circuit of a multi-channel 1T1R resistor network as claimed in claim 4, characterized in that: The negative electrode impedance calibration module includes: The negative electrode impedance calibration module is composed of the default voltage source, the ground line, the reference potential interface, the PAD connector, a second transistor, a multi-channel second RRAM network structure, a second post-stage comparator and a second precise matching resistor connection; The second RRAM network structure of each path is pulled down and connected to the ground line, and the other end of the RRAM network structure is connected to the PAD connector; One end of the second precise matching resistor is connected to the default voltage source, and the other end of the second precise matching resistor is connected to the PAD connector; The first input interface of the second post-stage comparator is connected to the PAD connector, the second input interface of the post-stage comparator is connected to the reference potential interface, and the output interface of the second post-stage comparator is connected to the DCI adjustment module; The second transistor is distributed to both ends of the second RRAM network structure, and is used to control the on-off state of the second RRAM network structure in the negative electrode impedance calibration module; The negative electrode impedance calibration module is used to adjust the connection state of the resistors in the RRAM network structure to obtain a negative electrode impedance adjustment signal, wherein the negative electrode impedance adjustment signal is the switch state of each second transistor in the multi-channel second RRAM network structure.

6. The impedance calibration circuit of a multi-channel 1T1R resistor network as claimed in claim 5, characterized in that: The DCI adjustment module includes: The DCI adjustment module is used to determine whether the positive impedance calibration module needs to perform an adjustment operation on the resistance connection state according to the output result of the post-stage comparator; The DCI adjustment module is further used to determine whether the negative electrode impedance calibration module needs to perform an adjustment operation on the resistance connection state according to the output result of the second post-stage comparator.

7. The impedance calibration circuit of a multi-channel 1T1R resistor network as claimed in claim 6, characterized in that: The user impedance calibration module comprises: Each route in the user impedance calibration module is obtained by sequentially connecting the default voltage source, the transistor, the RRAM network structure, the transistor, the second transistor, the second RRAM network structure, the second transistor and the ground line; The user impedance calibration module is used to obtain the positive impedance adjustment signal of the positive impedance calibration module and the negative impedance adjustment signal of the negative impedance calibration module when the DCI adjustment module determines that the positive impedance calibration module and the negative impedance calibration module do not need to perform an adjustment operation of the resistance connection state; According to the positive impedance adjustment signal and the negative impedance adjustment signal, a circuit network obtained by connecting the RRAM network structure and the second RRAM network structure in parallel is assigned a value based on a resistor connection state to obtain a matching external resistance value.

8. The impedance calibration circuit of a multi-channel 1T1R resistor network as claimed in claim 7, characterized in that: The preset rule is a binary arrangement, and the preset calibration algorithm is a dichotomy method.

9. An impedance calibration method for a multi-channel 1T1R resistor network, characterized in that: The method comprises: According to a pre-constructed DCI calibration rule, adjusting the connection state of the resistors in the pre-constructed RRAM network structure to obtain a positive impedance adjustment signal, and adjusting the connection state of the resistors in the pre-constructed second RRAM network structure to obtain a negative impedance adjustment signal, wherein the DCI calibration rule includes a preset calibration algorithm and a preset rule; According to the positive impedance adjustment signal and the negative impedance adjustment signal, a circuit network obtained by connecting the RRAM network structure and the second RRAM network structure in parallel is assigned a value based on a resistor connection state to obtain a matching external resistance value.

10. The impedance calibration method of a multi-channel 1T1R resistor network as claimed in claim 9, characterized in that: The method of adjusting the connection state of the resistors in the pre-constructed RRAM network structure according to the pre-constructed DCI calibration rule to obtain a positive impedance adjustment signal, and adjusting the connection state of the resistors in the pre-constructed second RRAM network structure to obtain a negative impedance adjustment signal, includes: Using a preset rule in a pre-built DCI calibration rule, the resistance value of each branch RRAM structure in the RRAM network structure in the positive impedance calibration module is adjusted to obtain an initialization positive impedance adjustment signal; According to a preset calibration algorithm in a pre-built DCI calibration rule, an update rule of the RRAM network structure is configured to obtain a positive electrode update rule; According to the positive electrode update rule, the initialized positive electrode impedance adjustment signal is iteratively updated to obtain a positive electrode impedance adjustment signal; Using the preset rules in the DCI calibration rules, the resistance value of each branch RRAM structure in the RRAM network structure in the negative electrode impedance calibration module is adjusted to obtain an initialization negative electrode impedance adjustment signal; According to the preset calibration algorithm in the DCI calibration rule, the update rule of the RRAM network structure in the negative electrode impedance calibration module is configured to obtain the negative electrode update rule, wherein the positive electrode update rule and the negative electrode update rule both represent the switching rule of each transistor of each branch RRAM structure; According to the negative electrode update rule, the initialized negative electrode impedance adjustment signal is iteratively updated to obtain a negative electrode impedance adjustment signal.

Images