Analog-to-digital converter based on dynamic floating inverse transformation pre-amplification comparator
By adopting a dynamic floating inverse conversion preamplifier structure and large capacitor power supply in the analog-to-digital converter, the problems of low detector accuracy and excessive power consumption are solved, and the analog-to-digital conversion effect with high precision and low power consumption is achieved.
Patent Information
- Application Number
- CN202411700342.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-26
- Publication Date
- 2025-03-18
AI Technical Summary
In the prior art, the detector has low accuracy and high power consumption, making it difficult to meet the design needs of CMOS image sensors.
An analog-to-digital converter based on a dynamic floating inverse transform preamplifier is adopted, including a sampling and holding module, a digital-to-analog conversion array module, an amplification comparison module and a successive approximation logic control module. Through the use of a dynamic floating inverse transform structure and large capacitors, high-precision amplification and comparison of error signals are achieved.
Improves the accuracy and stability of the analog-to-digital converter, reduces power consumption and noise, and is suitable for low-power scenarios.
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Figure CN119652318A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of analog-to-digital conversion, in particular to an analog-to-digital converter based on a dynamic floating inverse conversion preamplifier comparator. Background Art
[0002] Successive approximation analog-to-digital converters are favored for their low power consumption, high precision, and high resolution, and are widely used in various scenarios. For example, they are widely used in battery-powered portable devices such as smartphones, tablets, wearable devices, etc.; in medical equipment such as electrocardiographs, electroencephalographs, etc.; and in industrial control fields such as sensors and instruments. In these applications, low power consumption, high precision, and high speed are some of the key requirements. From the perspective of current academic research and engineering applications, successive approximation analog-to-digital converters can meet the requirements of different application scenarios mentioned above.
[0003] Improving the process is one way to improve accuracy and energy efficiency, but many key technologies need further research, and the accuracy of the detector is not ideal. Improving the design of the detector analog-to-digital conversion is another way to solve problems such as accuracy and power consumption limitations. For example, the use of dynamic latch comparators has the advantages of fast speed and low power consumption, but general latches have large input offset voltage and kickback noise. The input offset voltage can be reduced by input offset calibration, but that comes at the cost of additional power consumption and area, and is not suitable for low-power scenarios. Summary of the invention
[0004] The purpose of the present invention is to provide an analog-to-digital converter based on a dynamic floating inverse transform preamplifier comparator, which mainly solves the problems existing in the above-mentioned prior art, helps to solve the problems of low detector accuracy and excessive power consumption, and improves the design level of CMOS image sensors.
[0005] In order to achieve the above-mentioned purpose, the technical solution adopted by the present invention is to provide an analog-to-digital converter based on a dynamic floating inverse transform preamplifier comparator, characterized in that it includes a sampling and holding module, a digital-to-analog conversion array module, an amplification and comparison module and a successive approximation logic control module; the successive approximation logic module provides a reference clock beat to the digital-to-analog conversion array module, the amplification and comparison module and itself; the sampling and holding module is used to sample and hold the input signal, and transmit it to the digital-to-analog conversion array module connected thereto; the digital-to-analog conversion array module combines the input signal and the control signal output by the successive approximation logic control module to generate an error signal and transmit it to the amplification and comparison module; the amplification and comparison module is used to generate a comparison result signal after comparing the error signal; the amplification and comparison module includes a preamplifier using a dynamic floating inverse transform structure, which is used to pre-amplify the error signal; the successive approximation logic control module generates the control signal according to the comparison result signal, and feeds it back to the digital-to-analog conversion array module to generate the error signal of the next round until the successive approximation is completed to obtain the analog-to-digital conversion result.
[0006] Furthermore, the sampling and holding module includes a voltage stabilizing unit, a first clock control unit and a sampling unit; the first clock control unit controls the electrical connection relationship between the voltage stabilizing unit and the sampling unit based on an external clock beat; when the external clock beat is low, the voltage stabilizing unit is isolated from the sampling unit and is only connected to a power supply, and the power supply charges the voltage stabilizing unit to an operating voltage; when the external clock beat is high, the voltage stabilizing unit is disconnected from the power supply and connected to the sampling unit, and the input signal is superimposed on the operating voltage to ensure that the input signals of different amplitudes can be processed by the sampling unit.
[0007] Furthermore, the sampling and holding module further includes an isolation unit; the isolation unit is located between the voltage stabilizing unit, the power supply and the sampling unit, and is used to isolate noise and improve reliability.
[0008] Furthermore, the digital-to-analog conversion array module uses a common-mode level capacitor switch switching algorithm to complete digital-to-analog conversion, and includes multiple capacitors to form a group of capacitor pairs with binary weights; under the control of the successive approximation logic control module, the capacitors are successively connected to a reference voltage or one of the common-mode voltages, so as to generate the error signal in combination with the input signal during each round of approximation.
[0009] Furthermore, the amplification and comparison module includes the preamplifier and the comparator; the preamplifier is an amplifier with a dynamic floating inverse transformation structure, which is used to amplify the error signal and use it as the input of the comparator; the comparator compares the error signal, generates the comparison result signal, and transmits it to the successive approximation logic control module.
[0010] Furthermore, the preamplifier includes a charging unit, an integration unit and a first differential input unit; the first differential input unit is connected to the integration unit; the electrical connection between the charging unit and the integration unit is controlled by the reference clock beat; when the reference clock beat is low, the power supply and the common-mode voltage are simultaneously connected to the charging unit and the integration unit, respectively, to charge the charging unit and the integration unit respectively; when the reference clock beat is high, the power supply and the common-mode voltage are disconnected from the charging unit and the integration unit, and the charging unit and the integration unit are connected to each other; the charging unit supplies power to the integration unit and suppresses common-mode current; wherein the error signal from the first differential input unit completes the integration operation through the integration unit.
[0011] Furthermore, the comparator includes a second clock control unit, a second differential input unit and an amplifying unit; the second differential unit is connected to the output of the preamplifier; the second clock control unit is connected to the amplifying unit, and controls the operation of the amplifying unit based on the reference clock beat; when the reference clock beat is high, the differential signal from the preamplifier enters the amplifying unit from the second differential input unit, is processed by the amplifying unit and output to form the comparison result signal; when the reference clock beat is low, the signal of the second differential input unit is grounded, and at this time the amplifying unit maintains the comparison result signal of the previous round.
[0012] Furthermore, the successive approximation logic module includes a clock unit and a logic unit; the clock unit is connected to the digital-to-analog conversion array module, the amplification and comparison module and the logic unit, and is used to provide the reference clock beat; the logic unit is a digital circuit, which, driven by the reference clock beat, generates the control signal based on the comparison result signal, feeds it back to the digital-to-analog conversion array module, and generates the digital result signal.
[0013] Furthermore, the logic unit includes a shift register, a data latch and a switch controller; the shift register shifts the previously saved historical comparison result signal, then receives the comparison result signal, splices it to form a combination signal, and sends it to the data latch; the data latch is used to maintain the combination signal from the shift register, on the one hand as the analog-to-digital conversion result output, and on the other hand to send it to the switch controller; the switch controller forms a new control signal based on the combination signal, and feeds it back to the digital-to-analog conversion array module.
[0014] Furthermore, the switch controller uses synchronous successive approximation logic timing.
[0015] In view of the above technical features, the analog-to-digital converter based on the dynamic floating inverse conversion preamplifier comparator of the present invention has the following advantages:
[0016] 1. The sampling and holding module of the present invention utilizes a large capacitor C to realize current reuse and reduce power consumption, and the gate-source voltage is increased in the integration stage, which is more conducive to reducing noise during latching.
[0017] 2. The amplification comparison module of the present invention adopts a dynamic floating inverse conversion pre-comparator structure and uses a large capacitor for power supply. During the integration period, the integration capacitor is isolated from the external power supply, providing a good isolation voltage domain for the dynamic integration stage.
[0018] 3. The amplification comparison module of the present invention is not affected by the input common mode, and the pre-amplifier only amplifies the information of the differential input, thereby improving the accuracy and stability of the comparator. The amplification comparison module greatly reduces the influence of the process angle and the input common mode voltage on the noise, delay, offset and other performance of the comparator. Figure 6 and Figure 7 The comparison between the amplification comparison module of the present invention and the classic traditional dynamic comparator is respectively shown, and the noise and power consumption thereof are both reduced by about 50%. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a system block diagram of a preferred embodiment of an analog-to-digital converter based on a dynamic floating inverse conversion preamplifier comparator of the present invention;
[0020] Figure 2 It is a circuit diagram of a sampling and holding module in a preferred embodiment of an analog-to-digital converter based on a dynamic floating inverse conversion preamplifier comparator of the present invention;
[0021] Figure 3 It is a circuit connection diagram of a digital-to-analog conversion array module, an amplification comparison module and a successive approximation logic control module in a preferred embodiment of an analog-to-digital converter based on a dynamic floating inverse conversion preamplifier comparator of the present invention;
[0022] Figure 4 It is a circuit diagram of a preamplifier of an amplifying and comparing module in a preferred embodiment of an analog-to-digital converter based on a dynamic floating inverse transform preamplifying and comparator of the present invention;
[0023] Figure 5 It is a circuit diagram of a comparator of an amplifying comparison module in a preferred embodiment of an analog-to-digital converter based on a dynamic floating inverse conversion preamplifying comparator of the present invention;
[0024] Figure 6 It is a power consumption comparison diagram of an amplifying and comparing module and a traditional amplifying and comparing module in a preferred embodiment of an analog-to-digital converter based on a dynamic floating inverse conversion preamplifying and comparing device of the present invention;
[0025] Figure 7 It is a noise comparison diagram of an amplifying comparison module and a traditional amplifying comparator in a preferred embodiment of an analog-to-digital converter based on a dynamic floating inverse conversion preamplifying comparator of the present invention.
[0026] In the figure: 100-sampling and holding module, 200-digital-to-analog conversion array module, 300-amplification and comparison module, 400-successive approximation logic control module;
[0027] 101 - voltage stabilizing unit, 102 - first clock control unit, 103 - sampling unit, 104 - isolation unit;
[0028] 310-preamplifier, 320-comparator;
[0029] 311 - charging unit, 312 - integration unit, 313 - first differential input unit;
[0030] 321 - a second clock control unit, 322 - a second differential input unit, 323 - an amplification unit;
[0031] 410-clock unit, 420-logic unit;
[0032] 421 - shift register, 422 - data latch, 423 - switch controller. DETAILED DESCRIPTION
[0033] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.
[0034] See also Figure 1 The present invention discloses an analog-to-digital converter based on a dynamic floating inverse conversion preamplifier comparator. As shown in the figure: it includes a sampling and holding module 100, a digital-to-analog conversion array module 200, an amplification and comparison module 300 and a successive approximation logic control module 400.
[0035] Among them, the sampling and holding module 100 has an independent clock control, while the digital-to-analog conversion array module 200, the amplification and comparison module 300 and the successive approximation logic control module 400 work in the same clock domain. Specifically, the successive approximation logic module 400 is responsible for providing a reference clock beat for the digital-to-analog conversion array module 200, the amplification and comparison module 300 and itself (the successive approximation logic control module 400), so that the three modules can synchronize their working rhythms using the same reference clock beat. The sampling and holding module 100 is used to sample and hold the input analog signal to ensure that the converted analog signal does not change during the analog-to-digital conversion process, thereby ensuring that the digital signal of the final analog-to-digital conversion result is stable. The sampling and holding module 100 is connected to the digital-to-analog conversion array module 200 to transmit the sampled input analog signal to the digital-to-analog conversion array module 200. In this embodiment, there are two sampling and holding modules 100, which are combined to provide a differential signal as the input of the digital-to-analog conversion module 200, thereby improving the common-mode noise suppression capability and conversion accuracy. The digital-to-analog conversion array module 200 is controlled by the successive approximation logic control module 400. It reconverts the intermediate digital signal of each round in the successive approximation process into an analog signal, and then forms an error signal together with the sampled input analog signal, and sends it to the amplification and comparison module 300 for the next round of comparison. The amplification and comparison module 300 compares the error signal and transmits the result as a comparison result signal in digital form to the successive approximation logic control module 400. The successive approximation logic control module 400 records the comparison result signal of each round in this analog-to-digital conversion process to form a new digital signal, and generates a control signal based on the newly generated digital signal, which is fed back to the digital-to-analog conversion array module, thereby controlling the behavior of the digital-to-analog conversion array module 200 to generate the next round of error signals until the successive approximation is completed. After the successive approximation is completed, the successive approximation logic control module 400 outputs the digital signal as the final analog-to-digital conversion result.
[0036] See also Figure 1 and Figure 2 The sampling and holding module 100 includes a voltage stabilizing unit 101, a first clock control unit 102, a sampling unit 103 and an isolation unit 104. The voltage stabilizing unit 101 is composed of MOS tubes M1, M2 and a capacitor C. The first clock control unit 102 is composed of MOS tubes M3, M4 and M8. The sampling unit 103 is composed of MOS tubes M5, M9 and M10. The isolation unit 104 is composed of MOS tubes M6 and M7, which is used to isolate clutter and improve reliability. The two sampling and holding modules 100 respectively output their respective sampled input signals Vout to the digital-to-analog conversion array module 200.
[0037] The first clock control unit 102 is connected to an external clock source CLK, so as to control the operation of the voltage stabilizing unit 101 and the sampling unit 103 by using the rhythm of the external clock beat provided by the external clock source. When the external clock beat is at a low level, in the first clock control unit 102, M4 is disconnected, and M3 and M8 are turned on. At this time, M5, M9 and M10 in the sampling unit 103 are all disconnected, so that the analog input signal Vin and the sampled input signal Vout are isolated. At this time, the sampling unit 103 is divided by the holding state and does not sample the analog input signal Vin. At the same time, the voltage stabilizing unit 101 is also isolated from the sampling unit 103. At this time, in the voltage stabilizing unit 101, the capacitor C is connected to the power supply VDD through M1 and M2, and the two ends of the capacitor C are charged to VDD by the power supply. When the external clock beat is at a high level, in the first clock control unit 102, M4 is turned on, and M3 and M8 are disconnected. After M4 is turned on, M5, M9, and M10 in the sampling unit 103 are all turned on, so the analog input signal Vin is connected to the sampling input signal Vout through M10, that is, the sampling input signal Vout changes with the analog input signal Vin. In particular, at this time, the voltage across the gate and source of M10 is the voltage across the capacitor C, that is, the voltage charged to VDD in the previous stage, which has nothing to do with the analog input signal Vin, thereby ensuring that the conductivity of M10 is not affected in the case of analog input signals Vin of different amplitudes, and ensuring the stability of the sampling input signal Vout.
[0038] In this embodiment, the value of capacitor C should be large enough and should be much larger than the parasitic capacitance. Here, it is 555fF. At the same time, in order to reduce power consumption and parasitic capacitance, the size of all MOS tubes is kept as small as possible. The circuit has an ENOB of 9.65 bits under a 10MHz clock and a 1.65V input amplitude sinusoidal input.
[0039] The reference dimensions of the tubes in the current mirror part are shown in the following table (in microns).
[0040] tube M1 / M2 M3 M4 M5 / M9 M6 M7 M8 M10 W / L 14 / 0.35 3 / 0.35 1 / 0.35 14 / 0.35 1 / 0.35 3.5 / 0.35 7 / 0.35 4 / 0.35
[0041] See also Figure 1 and Figure 3, the digital-to-analog conversion array module 200 includes a plurality of capacitors, forming a set of binary weighted capacitor pairs (whose weights are 1 to 256, corresponding to a conversion accuracy of 10 bits), thereby improving the matching between bit capacitors and reducing the impact of parasitic effects. In addition, the capacitive analog-to-digital conversion itself also integrates the function of sampling and holding. The digital-to-analog conversion array module 200 uses a common-mode level capacitor switch switching algorithm to complete the digital-to-analog conversion. Wherein VI NP and VI NN are respectively from two sampling and holding modules 100 that are differentially related to each other, and they form a differential analog input signal. Under the control of the successive approximation logic control module 400, the two groups of capacitor pairs are successively connected to one of the reference voltage Vref or the common-mode voltage Vcm, and the corresponding switches S1 to S9 are switched, and the sampling switches are turned on at the same time, so that the input signal is superimposed on the existing voltage in the capacitor pair, and the error signal is formed together, and finally connected to the two input ends of the amplification comparison module 300. In different rounds of successive approximation, the number of charges stored in the capacitor pair is related to the comparison result of the previous round, so that the voltage reflected is also different. After the successive approximation is completed, the voltage across the capacitor pair can actually reflect the size of the input signal.
[0042] See also Figure 1 , Figure 4 and Figure 5 The amplification and comparison module 300 includes a preamplifier 310 and a comparator 320. The preamplifier 310 is an amplifier with a dynamic floating inverse conversion structure, which is used to amplify the error signal from the digital-to-analog conversion array module 200 and then send it to the comparator 320 for comparison, thereby ensuring that the comparison result is accurate. The comparator 320 compares the amplified error signal and outputs a comparison result signal.
[0043] exist Figure 4 In the embodiment, the preamplifier 310 includes a charging unit 311, an integrating unit 312 and a first differential input unit 313. Further, the charging unit 311 is a capacitor CRES. The integrating unit 312 is composed of two symmetrical capacitors CX. The first differential input unit 313 is composed of MOS tubes M1, M2, M3 and M4.
[0044] The first differential input unit 313 receives a set of differential signals Vi+ and Vi-, which correspond to two components in the error signal from the digital-to-analog conversion array module 200. The differential signals Vi+ and Vi- control the conduction or disconnection of the MOS tubes M1, M2, M3 and M4, thereby controlling the direction of the current in the integration unit 312 connected thereto, and finally forming a set of amplified differential signals Vx+ and Vx-. The power supply of the integration unit 312 when working does not come directly from the external voltage VDD, but is provided by the charging unit 311. Under the control of the reference clock beat from the successive approximation logic control module 400, the amplification comparison module 300 has two working states. When the reference clock beat is low, the external power supply VDD is connected to the two ends of the capacitor CRES of the charging unit 311, and its voltage is increased and maintained at VDD. At the same time, the common mode voltage Vcm is connected to the two ends of the capacitor CX in the integration unit 312, and the voltage of the capacitor CX is increased and maintained at Vcm.
[0045] When the reference clock beat is high, the external power supply VDD is disconnected from the capacitor CRES. At this time, the capacitor CRES is connected to the integration unit 312 controlled by the first differential input unit 313. At the same time, the capacitor CX in the integration unit 312 is also disconnected from the common mode voltage Vcm and is controlled by the first differential input unit 313. The capacitor CRES in the charging unit 311 determines the direction of the current according to the error signal, supplies power to the integration unit 312 to start integration, and suppresses the common mode current. When the integration unit 312 completes the integration, the voltages across the two capacitors CX are combined to form the amplified differential signals Vx+ and Vx-.
[0046] For the large capacitor CRES, the input and output currents must be equal. From the perspective of the entire circuit, the current flowing into the integral capacitor CX and the current flowing out of the integral capacitor CX are equal as a whole, that is, the common-mode current flowing into the integral capacitor CX is forced to be 0, thereby achieving a constant output common-mode voltage, and no special CMFB circuit is required to achieve a constant output common-mode voltage. In addition, in the integration stage, only the differential charge is loaded onto the capacitor to be integrated, and the common-mode voltage remains constant. Since the overall current flowing into and out of the integral capacitor CX is 0, that is, the overall charge does not change, the limitation of the bounded common-mode voltage drop on the preamplifier gain is eliminated. In this embodiment, the reference size of each MOS tube is shown in the following table (in microns).
[0047] tube M1 / M2 M3 / M4 W / L 60 / 0.35 30 / 0.35
[0048] exist Figure 5In the embodiment, the comparator 320 includes a second clock control unit 321, a second differential input unit 322 and an amplifier unit 323. The second differential unit 322 is composed of MOS tubes M5 and M6, and has two input terminals, which are respectively connected to the amplified differential signals Vx+ and Vx-. The second clock control unit 321 is composed of MOS tubes M7, M8, M9, M10 and M11, which are connected to the amplifier unit 323, and the amplifier unit 323 is turned on or off under the control of the second clock control unit 321 of the reference clock beat, so that the amplifier unit 323 works. The amplifier unit 323 includes MOS tubes M12, M13, M14 and M15, which constitute a differential amplifier circuit.
[0049] When the reference clock beat is high, the amplified differential signals Vx+ and Vx- from the MOS transistors M5 and M6 in the second differential input unit 322 enter the amplifier unit 323, and are amplified by the MOS transistors M12, M13, M14 and M15 to output Vo+ and Vo-, i.e., the comparison result signals in differential form. When the reference clock beat is low, the connection between the input of the MOS transistors M5 and M6 in the second differential input unit 322 and the power supply VDD is disconnected by M11 in the second clock control unit 321, and the output is grounded by M7 and M9 in the second clock control unit 321. At this time, the configuration of the amplifier unit 323 itself is also changed by M8 and M10 in the second clock control unit 321, and its output remains the comparison result signal of the previous round.
[0050] See also Figure 1 and Figure 3 The successive approximation logic module 400 includes a clock unit 410 and a logic unit 420. The clock unit 410 is a clock source, which is connected to the digital-to-analog conversion array module 200, the amplification and comparison module 300 and the logic unit 420 to provide a reference clock beat. In the digital-to-analog conversion array module 200, the reference clock beat controls the timing of the sampling switch and the two sets of switching switches S1 to S9 for controlling the capacitor pairs.
[0051] The logic unit 420 is a digital circuit, including a shift register 421, a data latch 422 and a switch controller 423. Driven by the reference clock beat provided by the clock unit 410, the shift register 421 shifts the previously saved historical comparison result signal, and then receives and fills the comparison result signal from the amplification comparison module 300 into the idle position after the shift, splices it with the shifted historical comparison result signal, forms a combination signal, and sends it to the data latch 422. When the shift register 421 is performing the shift operation, the data in the data latch 422 remains unchanged, and it is used to maintain the combination signal. In the comparison process of successive approximation, the combination signal is sent to the switch controller 423 as an intermediate result. Based on the combination signal, the switch controller 423 uses the synchronous successive approximation logic timing to generate the control signal for the next round of approximation, and feeds it back to the digital-to-analog conversion array module 200 to control the state of the two groups of switching switches S1 to S9 of the capacitor pairs in the digital-to-analog conversion array module 200. When the successive approximation is completed, the combined signal in the data latch 422 is the result of this analog-to-digital conversion.
[0052] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.
Claims
1. An analog-to-digital converter based on a dynamic floating inverse conversion preamplifier comparator, characterized in that: It comprises a sampling and holding module, a digital-to-analog conversion array module, an amplification and comparison module and a successive approximation logic control module; the successive approximation logic module provides a reference clock beat to the digital-to-analog conversion array module, the amplification and comparison module and itself; the sampling and holding module is used to sample and hold the input signal, and transmit it to the digital-to-analog conversion array module connected thereto; the digital-to-analog conversion array module combines the input signal and the control signal output by the successive approximation logic control module to generate an error signal and transmit it to the amplification and comparison module; the amplification and comparison module is used to generate a comparison result signal after comparing the error signal; the amplification and comparison module comprises a preamplifier with a dynamic floating inverse transformation structure, which is used to pre-amplify the error signal; the successive approximation logic control module generates the control signal according to the comparison result signal, and feeds it back to the digital-to-analog conversion array module to generate the error signal of the next round, until the successive approximation is completed and the analog-to-digital conversion result is obtained.
2. The analog-to-digital converter based on a dynamic floating inverse conversion preamplifier comparator according to claim 1, characterized in that: The sampling and holding module includes a voltage stabilizing unit, a first clock control unit and a sampling unit; the first clock control unit controls the electrical connection relationship between the voltage stabilizing unit and the sampling unit based on an external clock beat; when the external clock beat is low, the voltage stabilizing unit is isolated from the sampling unit and is only connected to a power supply, and the power supply charges the voltage stabilizing unit to an operating voltage; when the external clock beat is high, the voltage stabilizing unit is disconnected from the power supply and connected to the sampling unit, and the input signal is superimposed on the operating voltage to ensure that the input signals of different amplitudes can be processed by the sampling unit.
3. The analog-to-digital converter based on a dynamic floating inverse conversion preamplifier comparator according to claim 2, characterized in that: The sampling and holding module further comprises an isolation unit; the isolation unit is located between the voltage stabilizing unit, the power supply and the sampling unit, and is used to isolate clutter and improve reliability.
4. The analog-to-digital converter based on a dynamic floating inverse conversion preamplifier comparator according to claim 1, characterized in that: The digital-to-analog conversion array module uses a common-mode level capacitor switch switching algorithm to complete digital-to-analog conversion, and includes multiple capacitors to form a group of capacitor pairs with binary weights; under the control of the successive approximation logic control module, the capacitors are successively connected to a reference voltage or a common-mode voltage to generate the error signal in combination with the input signal during each round of approximation.
5. The analog-to-digital converter based on a dynamic floating inverse conversion preamplifier comparator according to claim 1, characterized in that: The amplification and comparison module includes the preamplifier and the comparator; the preamplifier is an amplifier with a dynamic floating inverse transformation structure, which is used to amplify the error signal and use it as the input of the comparator; the comparator compares the error signal, generates the comparison result signal, and transmits it to the successive approximation logic control module.
6. The analog-to-digital converter based on a dynamic floating inverse conversion preamplifier comparator according to claim 5, characterized in that: The preamplifier comprises a charging unit, an integrating unit and a first differential input unit; The first differential input unit is connected to the integration unit; the electrical connection between the charging unit and the integration unit is controlled by the reference clock beat; when the reference clock beat is low, the power supply and the common-mode voltage are simultaneously connected to the charging unit and the integration unit, respectively, to charge the charging unit and the integration unit respectively; when the reference clock beat is high, the power supply and the common-mode voltage are disconnected from the charging unit and the integration unit, and the charging unit and the integration unit are connected to each other; the charging unit supplies power to the integration unit and suppresses the common-mode current; wherein the error signal from the first differential input unit completes the integration operation through the integration unit.
7. The analog-to-digital converter based on a dynamic floating inverse conversion preamplifier comparator according to claim 5, characterized in that: The comparator comprises a second clock control unit, a second differential input unit and an amplifying unit; the second differential unit is connected to the output of the preamplifier; the second clock control unit is connected to the amplifying unit, and controls the operation of the amplifying unit based on the reference clock beat; When the reference clock beat is high, the differential signal from the preamplifier enters the amplifying unit from the second differential input unit, is processed by the amplifying unit and output to form the comparison result signal; when the reference clock beat is low, the signal of the second differential input unit is grounded, and the amplifying unit maintains the comparison result signal of the previous round.
8. The analog-to-digital converter based on a dynamic floating inverse conversion preamplifier comparator according to claim 1, characterized in that: The successive approximation logic module includes a clock unit and a logic unit; the clock unit is connected to the digital-to-analog conversion array module, the amplification and comparison module and the logic unit, and is used to provide the reference clock beat; the logic unit is a digital circuit, which, driven by the reference clock beat, generates the control signal based on the comparison result signal, feeds back to the digital-to-analog conversion array module, and generates the digital result signal.
9. The analog-to-digital converter based on a dynamic floating inverse conversion preamplifier comparator according to claim 8, characterized in that: The logic unit includes a shift register, a data latch and a switch controller; the shift register shifts the previously saved historical comparison result signal, then receives the comparison result signal, forms a combination signal after splicing, and sends it to the data latch; the data latch is used to hold the combination signal from the shift register, on the one hand as the analog-to-digital conversion result output, and on the other hand to send it to the switch controller; the switch controller forms a new control signal based on the combination signal, and feeds it back to the digital-to-analog conversion array module.
10. The analog-to-digital converter based on dynamic floating inverse conversion preamplifier comparator according to claim 9, characterized in that: The switch controller uses synchronous successive approximation logic timing.