Method for unloading 10-gigabit network embedded data based on UDP (User Datagram Protocol) through FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a method for unloading 10-gigabit network embedded data based on a UDP (User Datagram Protocol) through an FPGA (Field Programmable Gate Array), which relates to the technical field of embedded storage and is used for solving the problem of low data unloading rate. Frame data is cached and packaged into an IP frame, a sending packet sequence number is attached to the IP frame, the IP frame is transmitted to a host end, the host end analyzes the sending packet sequence number after receiving the IP frame, generates a response frame and transmits the response frame back, a device end verifies the received packet sequence number and the sending packet sequence number, IP frame retransmission or confirmation is selected according to a verification result, the IP frame is fragmented into IP sub-frames, and the IP sub-frames are sent to the host end. According to the method, the sending flow of IP frames is controlled by inserting delay counting, finally, the IP frames are converted into UDP data to interact with a host end, and the problems that a native UDP protocol has no response mechanism and is low in transmission efficiency are solved by integrating two-way handshake, IP fragmentation and an FPGA hardware layer to formulate a dynamic flow control mechanism.

Description

Technical Field

[0001] The present invention relates to the field of embedded storage technology, and more specifically, to a method for implementing 10G network embedded data unloading based on UDP protocol through FPGA. Background Art

[0002] With the rapid development of information technology, high-speed, massive embedded data storage has been widely used in many fields such as radar, communication, remote sensing, etc. In view of the current large-capacity, high-speed data storage, a convenient, fast and reliable data unloading method has become increasingly important.

[0003] The prior art has the following deficiencies: Currently, there are two mainstream data offloading methods for embedded storage: one is to offload through Gigabit Ethernet, and the other is to offload through USB. Both offloading methods have the advantages of simple interface, universality, and convenient transmission, but their transmission speed is limited. The transmission speed of Gigabit Ethernet is 1Gbps, and the fastest USB3.0 transmission speed is only 5Gbps. For some applications with large-capacity storage (TB level) and requirements for data offloading time, the offloading speed of Gigabit Ethernet and USB cannot meet the application requirements. Summary of the invention

[0004] In order to overcome the above-mentioned defects of the prior art, an embodiment of the present invention provides a 10 Gigabit network embedded data unloading method based on the UDP protocol through FPGA, which solves the problems of the native UDP protocol no-response mechanism and the low transmission efficiency caused by frequent interruptions of IP frames at the host receiving end by integrating two-way handshake, IP fragmentation and FPGA hardware layer to improve the effectiveness and rate of data transmission, and completely solves the problems raised in the above-mentioned background technology by achieving a transmission speed of up to 10Gbps through the 10G-UDP protocol.

[0005] To achieve the above object, the present invention provides the following technical solutions: A method for implementing 10G network embedded data unloading based on UDP protocol through FPGA includes the following steps: Step S1: The device side unloads the stored data in the solid state drive through the SATA or PCIE interface, and packages the unloaded data into frame data; Step S2: After the frame data is cached, it is packaged into an IP frame and transmitted to the host with a sending packet sequence number. After receiving the IP frame, the host parses the sending packet sequence number and generates a response frame, and transmits the response frame back to the receiving end two-way handshake protocol module through the 10 Gigabit network. The two-way handshake protocol module parses the received response frame to obtain the receiving packet sequence number, and verifies it with the sending packet sequence number, and selects to retransmit the IP frame or confirm the IP frame according to the verification result; Step S3: When sending IP frames, the adaptive IP fragmentation module fragments the IP frames to obtain multiple IP frames. The IP frames are automatically assembled at the host driver layer to generate IP frames and an interrupt is generated to notify the host to receive the IP frames. At the same time, the sending flow of the IP frames is controlled by inserting a delay count. Step S4: After the IP frame is fragmented by the IP fragmentation module, the multiple IP frames are converted into UDP data through the 10G-UDP protocol module to exchange information with the host end.

[0006] In a preferred embodiment, in step S1, the data unloading module includes four parts: a SATA / PCIE interface control module, a Raid control module, a FIFO cache module, and a data packaging module, which are used to complete the data unloading and packaging of the solid state drive; The SATA / PCIE interface control module is used to implement SATA / PCIE interface protocol parsing and send the parsed data to the Raid control module. The SATA / PCIE interface control module parses different hard disk protocol types and supports SATA1.0 / 2.0 / 3.0 and PCIE1.0 / 2.0 / 3.0 interfaces; The Raid control module is used for disk array management, improving storage system performance, supporting custom configuration of device quantity, and built-in DMA data transmission engine; the Raid control module organizes the received parsed data and sends it to the FIFO cache module for caching through DMA; The FIFO buffer module is used to buffer the offload data; The data packing module packs the cache data in the FIFO cache module, and the default data packing length can be customized in the data packing module.

[0007] In a preferred embodiment, in step S2, the two-way handshake protocol module implements a double handshake between the device and the host through a packet sequence number return verification mechanism, and retransmits the currently sent frame when the handshake fails or the response times out.

[0008] In a preferred embodiment, in step S2, the two-way handshake protocol module includes five parts: a sending packet sequence number module, a receiving packet sequence number module, a timeout module, an SRAM cache module, and a handshake protocol logic control module. The functions of each module are as follows: The sending packet sequence number module is used to generate the sending packet sequence number required for handshake. When the IP frame data is sent and the correct response packet sequence number is successfully received, the sending packet sequence number is automatically increased by 1; The receiving packet sequence number module is used to receive the response frame and output the receiving packet sequence number, which is used to check and compare the sending packet sequence number with the receiving packet sequence number; The timeout module is used to generate an over-response interrupt. When the IP frame data starts to be sent, the timeout module starts timing. If the response frame sent by the host is not received within the specified time, the timeout module generates a timeout response interrupt and retransmits the IP frame. When the response frame is received, the timeout timing counter is cleared. The SRAM cache module is used to cache frame data, adopts a dual SRAM mechanism, and uses a ping-pong operation method to read and write data; The handshake protocol logic control module is used to complete the logic control of the handshake protocol.

[0009] In a preferred embodiment, in step S2, the handshake protocol logic control module completes the logic control of the handshake protocol, including the following steps: Step 1: Perform SRAM cache read and write mechanism on frame data; Step 2: Pack the frame data and the sending packet sequence number and output the IP frame; Step 3: Perform handshake verification on the sending packet sequence number and the receiving packet sequence number. If the handshake verification succeeds, the next IP frame is sent; Step 4: If the handshake verification fails or the response times out, the current IP frame is retransmitted.

[0010] In a preferred embodiment, in step S2, the specific steps of the two-way handshake protocol process are as follows: The device caches the received frame data in a ping-pong operation mode, reads the sending frame data from the SRAM cache, packages the sending frame data and the sending packet sequence number into an IP frame, sends the IP frame and enters the waiting response frame state. After receiving the IP frame, the host parses the corresponding packet sequence number, and packages the extracted packet sequence number into a response frame and transmits it back to the device. After receiving the response frame or receiving the response timeout, the device verifies and compares the sending packet sequence number with the receiving packet sequence number. If the sending packet sequence number is equal to the receiving packet sequence number, the sending packet sequence number is automatically increased by 1, the retransmission counter is cleared to 0, and preparations are made to send the next frame; if the sending packet sequence number is not equal to the receiving packet sequence number, the current frame is retransmitted. If the number of retransmissions is greater than the preset retransmission threshold, the retransmission is terminated and the network transmission failure is reported.

[0011] In a preferred embodiment, in step S3, the adaptive IP fragmentation module includes six parts: an automatic flow control module, a FIFO buffer module, a fragmentation logic control module, a fragmentation identification module, a fragmentation flag module, and a fragmentation offset module. The functions of each module are as follows: The automatic flow control module is used to complete the flow control of IP frame transmission. After the IP frame transmission is completed, the transmission time between IP frames is controlled by inserting a delay count; The FIFO buffer module is used to buffer IP frames; The sharding logic control module is used to complete sharding logic control and data sharding; The fragment identification module is used to generate IP fragment identification; The fragmentation mark module is used to generate IP fragmentation marks; The fragment offset module is used to generate IP fragment offset coordinates to mark the relative position of the current fragment in the entire IP message.

[0012] In a preferred embodiment, in step S3, the automatic flow control principle in the automatic flow control module is as follows: When the flow control module detects an IP frame retransmission interruption, it indicates that the current transmission network may be congested and there may be frame loss. The delay count time automatically increases by 1, prolongs the sending time between IP sub-frames, reduces the sending rate of IP sub-frames, and resets the 1-second timer. When no IP frame retransmission interruption is detected within 1 second, it indicates that the current transmission network is unobstructed, and the delay count time automatically decreases by 1, shortens the sending time between IP sub-frames, increases the sending rate of IP sub-frames, and thus improves data transmission efficiency. When a network transmission error is detected, the delay count time is reset, and flow control is performed again after the network is restored.

[0013] In a preferred embodiment, in step S4, the 10G-UDP protocol module is a network protocol implemented based on 10 Gigabit network and is used to complete the underlying logical interface protocol conversion.

[0014] The technical effects and advantages of the method for implementing 10G network embedded data unloading based on UDP protocol through FPGA in the present invention are as follows: The device end of the present invention unloads the storage data in the solid state hard disk through the SATA or PCIE interface, and packs the unloaded data into frame data, caches the frame data and packs it into an IP frame and transmits it to the host end with a sending packet sequence number, after receiving the IP frame, the host end parses the sending packet sequence number and generates a response frame and transmits it back to the device end, the device end parses the received response frame to obtain the receiving packet sequence number, and verifies it with the sending packet sequence number, and performs a two-way handshake verification on the sequence numbers of the sending packet and the receiving packet to ensure whether the previous data is lost during the transmission process, and selects to retransmit the IP frame or confirm the IP frame according to the verification result, and at the same time, fragments the IP frame when sending it to obtain multiple IP sub-frames, and the IP sub-frames are automatically packaged in the host end driver layer Generate IP frames and generate interrupt notifications for the host to receive. Through IP fragmentation, the single data transmission volume of IP frames is increased, effectively reducing the interruption reception frequency of IP frames on the host side. At the same time, when sending IP frames, the sending flow of IP frames is controlled by inserting delay counting, which effectively reduces the number of retransmissions and improves data transmission efficiency. Finally, multiple IP frames are converted into UDP data through the 10G-UDP protocol module to interact with the host side. The dynamic flow control mechanism is formulated by integrating two-way handshake, IP fragmentation and FPGA hardware layer to solve the problems of the native UDP protocol no response mechanism and the low transmission efficiency caused by frequent interruptions of IP frames on the host receiving end, thereby improving the effectiveness and rate of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a flow chart of a method for implementing embedded data unloading of 10G network based on UDP protocol through FPGA of the present invention. Figure 2 The present invention is a logic flow chart of a method for implementing a 10G network embedded data unloading method based on UDP protocol through FPGA. Figure 3 This is a data unloading module diagram of a 10G network embedded data unloading method based on UDP protocol implemented by FPGA in the present invention. Figure 4 This is a two-way handshake protocol module diagram of a 10G network embedded data unloading method based on UDP protocol implemented by FPGA in the present invention. Figure 5 The present invention is a two-way handshake protocol flow chart of a 10G network embedded data unloading method based on UDP protocol implemented by FPGA. Figure 6 This is a diagram of an adaptive IP fragmentation module of the present invention, which implements a UDP protocol-based 10G network embedded data unloading method through FPGA. Figure 7This is a schematic diagram of an automatic flow control method for implementing a UDP protocol-based 10G network embedded data unloading method through FPGA in the present invention. Figure 8 This is a flow chart of an adaptive IP fragmentation method for implementing a UDP protocol-based 10G network embedded data unloading method through FPGA in the present invention. Fig. 9 The present invention is a 10G-UDP protocol module diagram of a 10G network embedded data unloading method based on the UDP protocol implemented by FPGA. DETAILED DESCRIPTION

[0016] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] The device end of the present invention unloads the storage data in the solid-state hard disk through the SATA or PCIE interface, and packs the unloaded data into frame data, caches the frame data, packs it into an IP frame and transmits it to the host end with a sending packet sequence number, and after receiving the IP frame, the host end parses the sending packet sequence number and generates a response frame and transmits it back to the device end, the device end parses the received response frame to obtain the receiving packet sequence number, and verifies it with the sending packet sequence number, and selects to retransmit the IP frame or confirm the IP frame according to the verification result, and when sending the IP frame, the IP frame is IP fragmented to obtain multiple IP sub-frames, thereby reducing the host end IP frame interruption reception frequency, and controls the sending flow of the IP sub-frame by inserting a delay counting method, thereby reducing the number of retransmissions and improving data transmission efficiency, and finally converts the multiple IP sub-frames into UDP data through a 10G-UDP protocol module to exchange information with the host end.

[0018] Embodiment, a method for implementing 10G network embedded data unloading based on UDP protocol through FPGA, such as Figure 1 As shown, the following steps are included: Step S1: The device side unloads the stored data in the solid state drive through the SATA or PCIE interface, and packages the unloaded data into frame data; Step S2: After the frame data is cached, it is packaged into an IP frame and transmitted to the host with a sending packet sequence number. After receiving the IP frame, the host parses the sending packet sequence number and generates a response frame, and transmits the response frame back to the receiving end two-way handshake protocol module through the 10 Gigabit network. The two-way handshake protocol module parses the received response frame to obtain the receiving packet sequence number, and verifies it with the sending packet sequence number, and selects to retransmit the IP frame or confirm the IP frame according to the verification result; Step S3: When sending IP frames, the adaptive IP fragmentation module fragments the IP frames to obtain multiple IP frames. The IP frames are automatically assembled at the host driver layer to generate IP frames and an interrupt is generated to notify the host to receive the IP frames. At the same time, the sending flow of the IP frames is controlled by inserting a delay count. Step S4: After the IP frame is fragmented by the IP fragmentation module, the multiple IP frames are converted into UDP data through the 10G-UDP protocol module to exchange information with the host end.

[0019] The specific implementation is as follows: The embedded data unloading method of 10G network based on UDP protocol is implemented in FPGA, which mainly includes four modules, such as Figure 2 As shown, they are data unloading module, two-way handshake protocol module, adaptive IP fragmentation module, and 10G-UDP protocol module.

[0020] The data unloading module is mainly used to complete the data unloading of the solid state drive, and pack the unloaded data into the corresponding frame format and send it to the two-way handshake protocol module.

[0021] The two-way handshake protocol module is mainly used to implement the protocol handshake and message retransmission between the device and the host to improve the reliability of data transmission. Because the UDP protocol is an unreliable transmission protocol and has no response confirmation mechanism, it has the advantages of fast transmission speed and simple and easy implementation.

[0022] The adaptive IP fragmentation module is used to automatically complete IP fragmentation according to different frame lengths; it can effectively reduce the number of network reception interruption responses on the host side and improve the transmission efficiency of network data.

[0023] The 10G-UDP protocol module is used to complete the analysis of network protocols such as UDP, ARP, ICMP, and realize the sending and receiving of communication data.

[0024] It should be noted that the solid-state drive is a data storage device used to store various types of data in the computer. The response confirmation mechanism is a mechanism used to ensure reliable data transmission in network communication and data transmission. UDP, ARP, and ICMP are different network protocols. UDP is a transport layer protocol used to provide connectionless data transmission services. ARP and ICMP are network layer protocols. The ARP protocol is used to resolve IP addresses into MAC addresses so that devices within the local area network can communicate. The ICMP protocol is used to send error messages and network control information to help diagnose and manage network connections.

[0025] In step S1, the data unloading module includes four parts: SATA / PCIE interface control module, Raid control module, FIFO buffer module, and data packaging module. Figure 3As shown, the data unloading module is used to complete the data unloading and packaging of the solid state drive.

[0026] The SATA / PCIE interface control module is used to implement SATA / PCIE interface protocol parsing and send the parsed data to the Raid control module. The SATA / PCIE interface control module can parse different hard disk protocol types and support SATA1.0 / 2.0 / 3.0 and PCIE1.0 / 2.0 / 3.0 interfaces; The Raid control module is used for disk array management, improving storage system performance, supporting custom configuration of device quantity, and built-in DMA data transmission engine; the Raid control module organizes the received parsed data and sends it to the FIFO cache module for caching through DMA; The FIFO buffer module is used to buffer the offload data; The data packaging module packages the cached data in the FIFO cache module. The default data packaging length can be customized in the data packaging module. For example, the default data packaging length is set to 48KB. The frame data after packaging is sent to the two-way handshake protocol module for subsequent UDP protocol sending. The frame data parameters include: frame data length, marked as frame_len; frame data, marked as frame_data; frame data validity, marked as frame_data_val; frame data end flag, marked as frame_data_last.

[0027] It should be noted that SATA and PCIE are two common computer interface standards, which are used to connect storage devices and expansion cards respectively; the DMA data transmission engine is a hardware mechanism used to achieve high-speed data transmission in computer systems; since the maximum length of a network IP frame does not exceed 64KB, when customizing the default data packaging length, ensure that its length does not exceed 64KB.

[0028] In step S2, the two-way handshake protocol module implements a double handshake between the device and the host through a packet sequence number return verification mechanism. When the handshake fails or the response times out, the current sending frame is retransmitted to make up for the transmission problem caused by the UDP transmission protocol's non-response confirmation mechanism and improve the reliability of data transmission.

[0029] The two-way handshake protocol module includes five parts: sending packet sequence number module, receiving packet sequence number module, timeout module, SRAM cache module, and handshake protocol logic control module. Figure 4 As shown, the functions of each module are as follows: The sending packet sequence number module is used to generate the sending packet sequence number required for handshake. When the IP frame data is sent and the correct response packet sequence number is successfully received, the sending packet sequence number is automatically increased by 1; The receiving packet sequence number module is used to receive the response frame and output the receiving packet sequence number, which is used to check and compare the sending packet sequence number with the receiving packet sequence number; The timeout module is used to generate an over-response interrupt. When the IP frame data starts to be sent, the timeout module starts timing. If the response frame sent by the host is not received within the specified time, the timeout module generates a timeout response interrupt and retransmits the IP frame. When the response frame is received, the timeout timing counter is cleared. The SRAM cache module is used to cache frame data, adopts a dual SRAM mechanism, and uses a ping-pong operation method to read and write data. It needs to be explained that since the maximum length of an IP frame is 64KB, the SRAM cache capacity is 64KB.

[0030] The handshake protocol logic control module is mainly used to complete the logic control of the handshake protocol, including the following steps: Step 1: Perform SRAM cache read and write mechanism on frame data; Step 2: Pack the frame data and the sending packet sequence number and output the IP frame; Step 3: Perform handshake verification on the sending packet sequence number and the receiving packet sequence number. If the handshake verification succeeds, the next IP frame is sent; Step 4: If the handshake verification fails or the response times out, the current IP frame is retransmitted.

[0031] The IP frame parameters output by the handshake protocol logic control module include: IP frame length, including frame data length and sending packet sequence number length, marked as ip_len; IP frame data, including frame data and packet sequence number, marked as ip_data; IP frame data validity, marked as ip_data_val; IP frame data end flag, marked as ip_data_last; IP frame retransmission interrupt, used for fragmentation flow control, marked as ip_retrans_int; network error flag, marked as ethnet_error.

[0032] The two-way handshake protocol process is as follows Figure 5 As shown, the specific steps are as follows: The device side caches the received frame data using a ping-pong operation, reads the sending frame data from the SRAM cache, packages the sending frame data and the sending packet sequence number into an IP frame, sends the IP frame and enters the waiting response frame state. After receiving the IP frame, the host side parses the corresponding packet sequence number, and the host side packages the extracted packet sequence number into a response frame and transmits it back to the device side. After the device side receives the response frame or the response is received and times out, it verifies and compares the sending packet sequence number and the receiving packet sequence number.

[0033] If the sending packet sequence number is equal to the receiving packet sequence number, the sending packet sequence number is automatically increased by 1, the retransmission counter is cleared to 0, and preparations are made to send the next frame; if the sending packet sequence number is not equal to the receiving packet sequence number, the current frame is retransmitted. If the number of retransmissions is greater than the preset retransmission threshold, the retransmission is terminated and the network transmission failure is reported.

[0034] It should be noted that the dual SRAM mechanism is a cache management strategy used in embedded system and microcontroller design to improve the efficiency and reliability of data access. The dual SRAM mechanism uses two independent SRAM blocks, namely two independent static random access memories, to achieve data storage and management. The ping-pong operation mode is a common data transmission and processing strategy, which is widely used in computer systems, embedded systems and signal processing fields. The two storage areas are used alternately to improve the efficiency and speed of data processing.

[0035] In step S3, the maximum message length of the network IP frame is 64KB, but the maximum transmission unit allowed by the link layer is mostly 1500 bytes. When the IP transmission message length is greater than the maximum transmission unit of the link layer, the IP needs to be fragmented. IP fragmentation is implemented through FPGA to reduce the number of interrupt responses received by the host network and improve the transmission efficiency of network data.

[0036] The adaptive IP fragmentation module includes six parts: automatic flow control module, FIFO buffer module, fragmentation logic control module, fragmentation identification module, fragmentation mark module, and fragmentation offset module. Figure 6 As shown, the adaptive IP fragmentation module is used to implement adaptive IP fragmentation.

[0037] The automatic flow control module is used to complete the flow control of IP frame transmission. After the IP frame transmission is completed, the transmission time between IP frames is controlled by inserting a delay count to achieve flow control of IP frame transmission. The delay count time is automatically adjusted by detecting IP retransmission interruption to achieve automatic flow control. The FIFO buffer module is used to buffer IP frames; The fragmentation logic control module is used to complete fragmentation logic control and data fragmentation; the fragmentation logic control module includes the following control and output parameters: the number of IP subframes is marked as ip_seg_num, the length of the IP frame is divided by the length of the IP subframe, and if there is a remainder, it is increased by 1; the IP subframe count is marked as ip_seg_cnt, and it is automatically increased by 1 after sending a frame of IP subframe; the completion of IP frame sending is marked as ip_seg_tx_done; the completion of IP frame sending is marked as ip_tx_done; the length of IP subframe is marked as ip_seg_len; the IP subframe data is marked as ip_seg_data; the valid IP subframe data is marked as ip_seg_data_valid; the start bit of IP subframe data is marked as ip_seg_data_sof; the end bit of IP subframe data is marked as ip_seg_data_eof; The fragment identification module is used to generate IP fragment identification to distinguish different IP frames. For the fragments of the same IP message, the same fragment identification is used. When all IP fragments are sent, the IP fragment identification automatically increases by 1. The fragment identification module sets the IP fragment identification ip_seg_id by detecting the IP frame sending completion flag ip_tx_done parameter. When ip_seg_id is equal to 1, that is, the IP frame is sent, it automatically increases by 1; The fragmentation flag module is used to generate the IP fragmentation flag, which contains two flag bits, DF and MF. When DF is 1, fragmentation is prohibited, and when DF is 0, fragmentation is allowed. When MF is 1, it means there are more fragments to come, and when MF is 0, it means the current fragment is the last fragment. The fragmentation flag module sets the following parameters by detecting the IP frame number ip_seg_num and IP frame count ip_seg_cnt parameters: Setting 1: Mark the IP fragmentation flag DF bit as ip_seg_df. When ip_seg_num is greater than 1, ip_seg_df is set to 0, allowing fragmentation; otherwise, ip_seg_df is set to 1, prohibiting fragmentation. Setting 2: Mark the IP fragmentation flag MF bit as ip_seg_mf. When ip_seg_cnt is equal to ip_seg_num minus 1, ip_seg_mf is set to 0, indicating that the current IP fragment is the last fragment. Otherwise, ip_seg_mf is set to 1, indicating that the current IP fragment is not the last fragment. The fragment offset module is used to generate IP fragment offset coordinates, which are used to mark the relative position of the current fragment in the entire IP message, with 8 bytes as a unit. The fragment offset module sets the IP fragment offset by detecting the IP frame sending completion flag ip_seg_tx_done parameter: The IP fragment offset is marked as ip_seg_offset. When ip_seg_tx_done is set to 1, the IP frame sending is completed, and ip_seg_len is automatically added and divided by 8.

[0038] The automatic flow control principle in the automatic flow control module is as follows Figure 7 As shown, the specific steps are as follows: When the flow control module detects an IP frame retransmission interruption, it indicates that the current transmission network may be congested and there may be frame loss. The delay count time automatically increases by 1, prolongs the sending time between IP sub-frames, reduces the sending rate of IP sub-frames, and resets the 1-second timer. When no IP frame retransmission interruption is detected within 1 second, it indicates that the current transmission network is unobstructed, and the delay count time automatically decreases by 1, shortens the sending time between IP sub-frames, increases the sending rate of IP sub-frames, and thus improves data transmission efficiency. When a network transmission error is detected, the delay count time is reset, and flow control is performed again after the network is restored.

[0039] The working principle of the adaptive IP fragmentation module is as follows Figure 8 As shown, the specific steps are as follows: When a new IP frame is received, the IP frame is first cached, and the number of IP frames ip_seg_num is calculated using the IP frame length ip_len and the IP sub-frame length ip_seg_len; When ip_seg_num is greater than 1, the IP fragmentation flag ip_seg_df is set to 0, allowing fragmentation; otherwise, ip_seg_df is set to 1, prohibiting fragmentation; When the IP frame count ip_seg_cnt is equal to the IP frame number ip_seg_num minus 1, the IP fragmentation flag ip_seg_mf is set to 0, and the current fragment is the last fragment; otherwise, the IP fragmentation flag ip_seg_mf is set to 1, and the current fragment is not the last fragment; After the IP fragmentation flag is configured, the IP fragmentation data is read from the FIFO buffer for transmission. The data length is the IP frame length ip_seg_len. After the IP frame is sent, the IP frame count ip_seg_cnt is increased by 1, and the IP fragmentation offset ip_seg_offset is increased by ip_seg_len divided by 8. After the flow control delay timing is completed, it is determined whether the IP frame count ip_seg_cnt is equal to the IP frame number ip_seg_num. If they are equal, the IP frame is sent, the IP fragment identifier ip_seg_id is increased by 1, and the next IP frame data is waited for; if they are not equal, the next IP frame data is prepared to be sent.

[0040] It should be noted that the delay count is a technology used to measure and control time delay. In this example, the delay count is used to implement automatic flow control.

[0041] In step S4, the 10G-UDP protocol module is a network protocol based on 10G network, including five parts: UDP sending module, UDP receiving module, ARP protocol module, ICMP protocol module, and 10G Ethernet PCS / PMA IP interface control module. Fig. 9 As shown, the 10G-UDP protocol module supports multiple protocols and can realize two-way UDP communication.

[0042] The UDP sending module is used to implement the UDP protocol to send group packets and complete the message sending of fragmented frames; The UDP receiving module is used to implement UDP protocol parsing and complete the correct reception of the response packet sequence number; The ARP protocol module is used to complete active or passive address protocol resolution; The ICMP protocol module is used to complete the response to the host PING command; As the PHY module of 10G Ethernet, the 10G Ethernet PCS / PMA IP interface control module directly calls the 10G Ethernet PCS / PMA IP implementation inside the FPGA to complete the underlying logic interface protocol conversion.

[0043] It should be noted that the PHY module is a physical layer module, which is used to implement the physical layer function of data communication and ensure the transmission of data on the physical medium.

[0044] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented by software, the above embodiments may be implemented in whole or in part in the form of a computer program product.

[0045] Those of ordinary skill in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application of the technical solution and the invention constraints. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0046] In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module.

[0047] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0048] Finally: The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for implementing 10G network embedded data unloading based on UDP protocol through FPGA, characterized in that: The following steps are involved: Step S1: The device side unloads the stored data in the solid state drive through the SATA or PCIE interface, and packages the unloaded data into frame data; Step S2: After the frame data is cached, it is packaged into an IP frame and transmitted to the host with a sending packet sequence number. After receiving the IP frame, the host parses the sending packet sequence number and generates a response frame, and transmits the response frame back to the receiving end two-way handshake protocol module through the 10 Gigabit network. The two-way handshake protocol module parses the received response frame to obtain the receiving packet sequence number, and verifies it with the sending packet sequence number, and selects to retransmit the IP frame or confirm the IP frame according to the verification result; Step S3: When sending IP frames, the adaptive IP fragmentation module fragments the IP frames to obtain multiple IP frames. The IP frames are automatically assembled at the host driver layer to generate IP frames and an interrupt is generated to notify the host to receive the IP frames. At the same time, the sending flow of the IP frames is controlled by inserting a delay count. Step S4: After the IP frame is fragmented by the IP fragmentation module, the multiple IP frames are converted into UDP data through the 10G-UDP protocol module to exchange information with the host end; The host driver layer is a key software component in the computer system that is responsible for communicating and controlling hardware devices and is used to assemble IP frames.

2. The method for implementing 10G network embedded data unloading based on UDP protocol by FPGA according to claim 1, characterized in that: In step S1, the data unloading module includes four parts: SATA / PCIE interface control module, Raid control module, FIFO cache module, and data packaging module, which are used to complete data unloading and packaging of the solid state drive; The SATA / PCIE interface control module is used to implement SATA / PCIE interface protocol parsing and send the parsed data to the Raid control module. The SATA / PCIE interface control module parses different hard disk protocol types and supports SATA1.0 / 2.0 / 3.0 and PCIE1.0 / 2.0 / 3.0 interfaces; The Raid control module is used for disk array management, improving storage system performance, supporting custom configuration of device quantity, and built-in DMA data transmission engine; the Raid control module organizes the received parsed data and sends it to the FIFO cache module for caching through DMA; The FIFO buffer module is used to buffer the offload data; The data packing module packs the cache data in the FIFO cache module, and the default data packing length can be customized in the data packing module.

3. The method for implementing 10G network embedded data unloading based on UDP protocol by FPGA according to claim 1, characterized in that: In step S2, the two-way handshake protocol module implements a double handshake between the device and the host through a packet sequence number return verification mechanism, and retransmits the current sending frame when the handshake fails or the response times out.

4. The method for implementing 10G network embedded data unloading based on UDP protocol by FPGA according to claim 3, characterized in that: In step S2, the two-way handshake protocol module includes five parts: a sending packet sequence number module, a receiving packet sequence number module, a timeout module, an SRAM cache module, and a handshake protocol logic control module. The functions of each module are as follows: The sending packet sequence number module is used to generate the sending packet sequence number required for handshake. When the IP frame data is sent and the correct response packet sequence number is successfully received, the sending packet sequence number is automatically increased by 1; The receiving packet sequence number module is used to receive the response frame and output the receiving packet sequence number, which is used to check and compare the sending packet sequence number with the receiving packet sequence number; The timeout module is used to generate an over-response interrupt. When the IP frame data starts to be sent, the timeout module starts timing. If the response frame sent by the host is not received within the specified time, the timeout module generates a timeout response interrupt and retransmits the IP frame. When the response frame is received, the timeout timing counter is cleared. The SRAM cache module is used to cache frame data, adopts a dual SRAM mechanism, and uses a ping-pong operation method to read and write data; The handshake protocol logic control module is used to complete the logic control of the handshake protocol.

5. The method for implementing 10G network embedded data unloading based on UDP protocol by FPGA according to claim 4, characterized in that: In step S2, the handshake protocol logic control module completes the logic control of the handshake protocol, including the following steps: Step 1: Perform SRAM cache read and write mechanism on frame data; Step 2: Pack the frame data and the sending packet sequence number and output the IP frame; Step 3: Perform handshake verification on the sending packet sequence number and the receiving packet sequence number. If the handshake verification succeeds, the next IP frame is sent; Step 4: If the handshake verification fails or the response times out, the current IP frame is retransmitted.

6. The method for implementing 10G network embedded data unloading based on UDP protocol by FPGA according to claim 3, characterized in that: In step S2, the specific steps of the two-way handshake protocol process are as follows: The device caches the received frame data in a ping-pong operation mode, reads the sending frame data from the SRAM cache, packages the sending frame data and the sending packet sequence number into an IP frame, sends the IP frame and enters the waiting response frame state. After receiving the IP frame, the host parses the corresponding packet sequence number, and packages the extracted packet sequence number into a response frame and transmits it back to the device. After receiving the response frame or receiving the response timeout, the device verifies and compares the sending packet sequence number with the receiving packet sequence number. If the sending packet sequence number is equal to the receiving packet sequence number, the sending packet sequence number is automatically increased by 1, the retransmission counter is cleared to 0, and preparations are made to send the next frame; if the sending packet sequence number is not equal to the receiving packet sequence number, the current frame is retransmitted. If the number of retransmissions is greater than the preset retransmission threshold, the retransmission is terminated and the network transmission failure is reported.

7. The method for implementing 10G network embedded data unloading based on UDP protocol by FPGA according to claim 1, characterized in that: In step S3, the adaptive IP fragmentation module includes six parts: automatic flow control module, FIFO buffer module, fragmentation logic control module, fragmentation identification module, fragmentation mark module, and fragmentation offset module. The functions of each module are as follows: The automatic flow control module is used to complete the flow control of IP frame transmission. After the IP frame transmission is completed, the transmission time between IP frames is controlled by inserting a delay count; The FIFO buffer module is used to buffer IP frames; The sharding logic control module is used to complete sharding logic control and data sharding; The fragment identification module is used to generate IP fragment identification; The fragmentation mark module is used to generate IP fragmentation marks; The fragment offset module is used to generate IP fragment offset coordinates to mark the relative position of the current fragment in the entire IP message.

8. The method for implementing 10G network embedded data unloading based on UDP protocol by FPGA according to claim 7, characterized in that: In step S3, the automatic flow control principle in the automatic flow control module is as follows: When the flow control module detects an IP frame retransmission interruption, it indicates that the current transmission network is congested and frame loss occurs. The delay count time automatically increases by 1, extending the sending time between IP frames, reducing the sending rate of IP frames, and at the same time, the 1-second timer is reset to zero. When no IP frame retransmission interruption is detected within 1 second, it indicates that the current transmission network is unobstructed. The delay count time automatically decreases by 1, shortening the sending time between IP frames, increasing the sending rate of IP frames, and thus improving data transmission efficiency. When a network transmission error is detected, the delay count time is reset to zero, and flow control is performed again after the network is restored.

9. The method for implementing 10G network embedded data unloading based on UDP protocol by FPGA according to any one of claims 1 to 7, characterized in that: In step S4, the 10G-UDP protocol module is a network protocol implemented based on 10 Gigabit network and is used to complete the underlying logical interface protocol conversion.

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