Heterojunction bipolar transistor device and forming method thereof

Abstract

The invention discloses a heterojunction bipolar transistor device and a forming method thereof. The method comprises the following steps: providing a substrate; forming an emitter material layer on the substrate; forming a base material layer on the emitter material layer; forming a collector material layer on the base material layer; the collector material layer is etched to form a plurality of collector layers, and the collector layers are arranged in the first direction; etching the base material layer until the emitter material layer is exposed to form a base layer; implanting ions into the base layer located in the first isolation region and the emitter material layer and the base layer located below the first isolation region by adopting an ion implantation process so as to form a first isolation structure in the emitter material layer and the base layer, and forming an emitter layer by using the emitter material layer, the stray capacitance between the collector layer and the base layer is reduced, the stray capacitance between the emitter layer and the base layer is reduced, and the cut-off frequency and the radio frequency gain of the device are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a heterojunction bipolar transistor device and a forming method thereof. Background Art

[0002] The RF front-end chips of wireless communication devices include power amplifiers, antenna switches, RF filters, multiplexers, and low noise amplifiers, etc. Among them, power amplifiers include bipolar junction transistor (BJT) power amplifiers, heterojunction bipolar transistor (HBT) power amplifiers, pseudomorphic high electron mobility transistor (PHEMT) power amplifiers, etc.

[0003] With the development of wireless communication technology, more and more frequency bands are used, and more frequency bands mean more complex circuit design. However, the parasitic capacitance inside the device is a factor that limits the operating frequency and bandwidth of the device.

[0004] Therefore, the existing heterojunction bipolar transistor technology needs to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a heterojunction bipolar transistor device and a forming method thereof, so as to improve the performance of the heterojunction bipolar transistor device.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a heterojunction bipolar transistor device, including: a substrate; an emitter layer located on the substrate, a base layer located on the emitter layer, a plurality of collector layers and a base contact layer located on the base layer, and a first isolation structure located in the emitter layer and the base layer, the base layer includes a plurality of collector regions, a plurality of electrical contact regions and a plurality of first isolation regions, the plurality of collector regions are arranged along a first direction, the collector layer is located on the collector region, the base contact layer is located on the electrical contact region, and the first isolation structure is located in the first isolation region.

[0007] Optionally, the plurality of collector regions are further arranged along a second direction, and the first direction and the second direction are perpendicular to each other.

[0008] Optionally, the electrical contact region is located between the collector regions adjacent to each other in the second direction, and the first isolation region is located between the collector regions adjacent to each other in the first direction.

[0009] Optionally, the electrical contact regions located in the first direction are interconnected and extend along the first direction.

[0010] Optionally, the first isolation regions located in the second direction are connected to each other and extend along the second direction.

[0011] Optionally, the base contact layer includes a plurality of first contact strips, wherein the first contact strips are located on the electrical contact region and extend along the first direction, and the first contact strips are located between the collector layers adjacent to each other in the second direction.

[0012] Optionally, the first contact strip crosses the first isolation region.

[0013] Optionally, the base contact layer further includes: a plurality of second contact strips connected to the plurality of first contact strips, the second contact strips are located on the first isolation region and extend along the second direction, and the second contact strips are located between two adjacent collector layers in the first direction.

[0014] Optionally, it also includes: a blocking layer located on the surface of the base layer, a plurality of collector layers located on part of the surface of the blocking layer, the material of the blocking layer is different from the material of the base layer, and the conductivity type of the blocking layer is different from the conductivity type of the base layer; the base contact layer is embedded in the blocking layer and in contact with the base layer.

[0015] Optionally, it also includes: a collector contact layer located on the surface of each collector layer, a collector conductive structure electrically connected to the collector contact layer, and a base conductive structure electrically connected to the base contact layer; the collector conductive structure includes a plurality of collector conductive parts and a collector conductive bus, a plurality of collector conductive parts are electrically connected to a plurality of the collector contact layers, and the collector conductive bus is connected to a plurality of the collector conductive parts.

[0016] Optionally, a plurality of collector conductive parts extend along the second direction and are arranged along the first direction, and the collector conductive bus extends along the first direction; the base conductive structure and the collector conductive bus are located on opposite sides of the base layer in the second direction, or the base conductive structure is located between two adjacent collector layers in the first direction.

[0017] Optionally, a plurality of collector conductive parts extend along the first direction and are arranged along the second direction, and the collector conductive bus extends along the second direction; the base conductive structure is located between two adjacent collector layers in the second direction, or the base conductive structure and the collector conductive bus are located on opposite sides of the base layer in the first direction.

[0018] Correspondingly, the technical solution of the present invention also provides a method for forming a heterojunction bipolar transistor device, comprising: providing a substrate; forming an emitter material layer on the substrate; forming a base material layer on the emitter material layer; forming a collector material layer on the base material layer; etching the collector material layer to form a plurality of collector layers, wherein the plurality of collector layers are arranged along a first direction; etching the base material layer until the emitter material layer is exposed to form a base layer, wherein the base layer comprises a plurality of collector regions, a plurality of electrical contact regions and a plurality of first isolation regions, wherein the plurality of collector regions are arranged along a first direction, and the collector layer is formed on the collector region; using an ion implantation process to implant ions into the base layer located in the first isolation region and the emitter material layer located below the first isolation region to form a first isolation structure in the emitter material layer and the base layer, and to form an emitter layer with the emitter material layer; and forming a base contact layer on the electrical contact region.

[0019] Optionally, the process parameters of the ion implantation process include: the ions include one or more of boron ions, helium ions and hydrogen ions, and the implantation dose range is 1×10 13 ion / cm 2 Up to 1×10 14 ion / cm 2 .

[0020] Optionally, the plurality of collector regions are further arranged along a second direction, and the first direction and the second direction are perpendicular to each other.

[0021] Optionally, the electrical contact region is located between the collector regions adjacent to each other in the second direction, and the first isolation region is located between the collector regions adjacent to each other in the first direction.

[0022] Optionally, the electrical contact regions located in the first direction are interconnected and extend along the first direction.

[0023] Optionally, the first isolation regions located in the second direction are connected to each other and extend along the second direction.

[0024] Optionally, the method for forming the base contact layer includes: forming a plurality of first contact strips, wherein the first contact strips are located on the electrical contact region and extend along the first direction, and the first contact strips are located between the collector layers adjacent to each other in the second direction.

[0025] Optionally, the first contact strip crosses the first isolation region.

[0026] Optionally, it also includes: forming a barrier material layer on the surface of the base material layer, the collector material layer is formed on the surface of the barrier material layer, the material of the barrier material layer is different from the material of the base material layer, and the conductivity type of the barrier material layer is different from the conductivity type of the base material layer; the method for forming the collector layer also includes: etching the collector material layer until the barrier material layer on the surface of the base material layer is exposed to form a plurality of collector layers; etching the barrier material layer to form a barrier layer.

[0027] Optionally, the method for forming the base contact layer further includes: annealing the base contact layer so that the base contact layer is embedded in the barrier layer, and diffusing the material of the base contact layer into the base layer so that the base contact layer is in contact with the base layer.

[0028] Optionally, the method for forming the base contact layer further includes: forming a plurality of second contact strips connected to the plurality of first contact strips, the second contact strips being located on the first isolation region and extending along the second direction, the second contact strips being located between two adjacent collector layers in the first direction.

[0029] Optionally, it also includes: forming a collector contact layer on the surface of each collector layer; forming a collector conductive structure on the surface of the collector contact layer; the collector conductive structure includes a plurality of collector conductive parts and a collector conductive bus, the plurality of collector conductive parts are electrically connected to the plurality of collector contact layers, and the collector conductive bus is connected to the plurality of collector conductive parts; and forming a base conductive structure on the surface of the base contact layer.

[0030] Optionally, a plurality of collector conductive parts extend along the second direction and are arranged along the first direction, and the collector conductive bus extends along the first direction; the base conductive structure and the collector conductive bus are located on opposite sides of the base layer in the second direction, or the base conductive structure is located between two adjacent collector layers in the first direction.

[0031] Optionally, a plurality of collector conductive parts extend along the first direction and are arranged along the second direction, and the collector conductive bus extends along the second direction; the base conductive structure is located between two adjacent collector layers in the second direction, or the base conductive structure and the collector conductive bus are located on opposite sides of the base layer in the first direction.

[0032] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0033] In the heterojunction bipolar transistor device provided by the technical solution of the present invention, the emitter layer is placed at the bottom layer to carry the emitter contact layer and the base layer, so the area of ​​the emitter layer is the largest. Under the requirement of a fixed emitter layer area, the area of ​​the PN junction formed between the collector layer and the base layer is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer. BC By providing a plurality of collector layers arranged along the first direction, the total area of ​​the collector layer is reduced, and the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer is further reduced. BC At the same time, by providing a first isolation structure in the emitter layer and the base layer, the PN junction area formed between the emitter layer and the base layer can be reduced, thereby reducing the parasitic capacitance C between the emitter layer and the base layer. BE , which is beneficial to improve the cutoff frequency and RF gain of the device.

[0034] Furthermore, the first isolation regions located in the second direction are interconnected and extend along the second direction, and the first contact strips cross the first isolation regions. By increasing the size of the first isolation regions along the second direction, the area of ​​the first isolation regions is increased, and the area of ​​the PN junction formed between the emitter layer and the base layer is further reduced, so as to further reduce the parasitic capacitance C between the emitter layer and the base layer. BE , improving the cutoff frequency and RF gain of the device.

[0035] Furthermore, several of the second contact strips in the base contact layer are arranged between the collector layers adjacent to each other in the first direction, so as to disperse the base current, reduce the heat concentration effect caused by the current concentration, and improve the heat dissipation capacity. Moreover, the arrangement of several of the second contact strips and several of the first contact strips makes the distribution of the base contact layer more uniform, which is beneficial to reduce stress and prevent device deformation.

[0036] In the method for forming a heterojunction bipolar transistor device provided by the technical solution of the present invention, the emitter layer is placed at the bottom layer to carry the emitter contact layer and the base layer, so the area of ​​the emitter layer is the largest. Under the requirement of a fixed emitter layer area, the area of ​​the PN junction formed between the collector layer and the base layer is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer. BC By forming a plurality of collector regions arranged along the first direction, the total area of ​​the collector layer is reduced, and the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer is further reduced. BC At the same time, by providing a first isolation structure in the emitter layer and the base layer, the PN junction area formed between the emitter layer and the base layer can be reduced, thereby reducing the parasitic capacitance C between the emitter layer and the base layer. BE , which is beneficial to improve the cutoff frequency and RF gain of the device.

[0037] Furthermore, the first isolation regions located in the second direction are interconnected and extend along the second direction, and the first contact strips cross the first isolation regions. By increasing the size of the first isolation regions along the second direction, the area of ​​the first isolation regions is increased, and the area of ​​the PN junction formed between the emitter layer and the base layer is further reduced, so as to further reduce the parasitic capacitance C between the emitter layer and the base layer. BE , improving the cutoff frequency and RF gain of the device.

[0038] Furthermore, several of the second contact strips in the base contact layer are arranged between the collector layers adjacent to each other in the first direction, so as to disperse the base current, reduce the heat concentration effect caused by the current concentration, and improve the heat dissipation capacity. Moreover, the arrangement of several of the second contact strips and several of the first contact strips makes the distribution of the base contact layer more uniform, which is beneficial to reduce stress and prevent device deformation. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figures 1 to 3 It is a schematic diagram of the structure of a heterojunction bipolar transistor device;

[0040] Figures 4 to 40 It is a structural schematic diagram of each step of a method for forming a heterojunction bipolar transistor device according to an embodiment of the present invention;

[0041] Figure 41 to Figure 43 It is a structural schematic diagram of each step of a method for forming a heterojunction bipolar transistor device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0042] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0043] As described in the background art, the performance of heterojunction bipolar transistor devices formed by the existing technology needs to be improved. Now, a heterojunction bipolar transistor device is described and analyzed.

[0044] Figures 1 to 3 It is a structural schematic diagram of a heterojunction bipolar transistor device.

[0045] Please refer to Figures 1 to 3 , Figure 1 for Figure 2 and Figure 3 The schematic diagram of the top view of the passivation layer is omitted. Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the DD1 direction, Figure 3 for Figure 1The cross-sectional structural schematic diagram along the EE1 direction in the figure, the heterojunction bipolar transistor device comprises: a substrate 100; a first collector portion 101, an isolation layer 102 and a prism structure on the first collector portion 101 located on the substrate 100, the prism structure comprising a second collector portion 103 and a base layer 104 located on the second collector portion 103, the collector layer comprising the first collector portion 101 and the second collector portion 103, the isolation layer 102 is located on the side wall of the first collector portion 101 and surrounds the first collector portion 101; a plurality of emitter layers 105 and a base contact layer located on the base layer 104, the plurality of emitter layers 105 are arranged parallel to the first direction X and along the second direction Y, the first The direction X is perpendicular to the second direction Y, the base contact layer includes a base bus line 106 parallel to the second direction Y and a plurality of base portions 107 parallel to the first direction X, each of the base portions 107 is located between adjacent emitter layers 105 and is electrically connected to the base bus line 106; an emitter contact layer 108 located on each of the emitter layers 105; a passivation layer 109 located on the surfaces of the emitter layer 105, the emitter contact layer 108 and the base layer 104, the passivation layer 109 having an opening (not shown in the figure), the opening exposing a portion of the surface of the base layer 104, and the base contact layer is also located in the opening; a collector contact layer 110 located on the first collector portion 101.

[0046] In the above heterojunction bipolar transistor device, there is a parasitic capacitance (ie, junction capacitance) C at the contact surface (ie, PN interface) between the collector layer and the base layer 104. BC The prism structure formed by the second collector portion 103 of the collector layer and the base layer 104 is at the bottom layer, which is used to carry the emitter layer 105 and the base contact layer. Therefore, the area of ​​the upper surface of the prism structure is larger than the area of ​​the emitter layer 105. The area of ​​the emitter layer 105 determines the output power of the device. Under the requirement of a fixed emitter layer area, the above structure makes the contact surface between the collector layer and the base layer 104 larger, thereby making the parasitic capacitance C BC It is large, affecting the device's RF performance (such as power gain).

[0047] In order to solve the above problems, the present invention provides a heterojunction bipolar transistor device and a method for forming the same, in which the emitter layer is placed at the bottom layer to carry the emitter contact layer and the base layer, so that the area of ​​the emitter layer is the largest. Under the requirement of a fixed emitter layer area, the area of ​​the PN junction formed between the collector layer and the base layer is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer. BC By forming a plurality of collector regions arranged along the first direction, the total area of ​​the collector layer is reduced, and the parasitic capacitance (i.e., junction capacitance) C between the collector layer and the base layer is further reduced.BC At the same time, by providing a first isolation structure in the emitter layer and the base layer, the PN junction area formed between the emitter layer and the base layer can be reduced, thereby reducing the parasitic capacitance C between the emitter layer and the base layer. BE , which is beneficial to improve the cutoff frequency and RF gain of the device.

[0048] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0049] Figures 4 to 40 It is a structural schematic diagram of each step of a method for forming a heterojunction bipolar transistor device according to an embodiment of the present invention.

[0050] Please refer to Figures 4 to 5 , Figure 4 for Figure 5 A top view of the structure. Figure 5 yes Figure 4 A schematic cross-sectional structure diagram along the MM1 direction in FIG. 1 provides a substrate 200 .

[0051] In this embodiment, the substrate 200 includes a device region C and a second isolation region I, and the second isolation region I surrounds the device region C. The device region C is used to define the position of the emitter layer, and the second isolation region I is used to define the position of the second isolation structure.

[0052] In this embodiment, the device region C includes a base mesa region bp; the base mesa region bp includes a base lead-out region bc, a gap region g and a collector mesa region cp arranged along the second direction Y, and the base lead-out region bc and the collector mesa region cp are located on both sides of the gap region g. The base mesa region bp is used to define the position of the base layer, the collector mesa region cp is used to define the positions of several collector layers, and the base lead-out region bc is used to define the position of the base terminal.

[0053] In this embodiment, the device region C further includes two emission extraction regions ec, the two emission extraction regions ec and the base platform region cp are arranged along the first direction X, and the two emission extraction regions ec are respectively located on both sides of the base platform region cp. The emission extraction region ec is used to define the position of the emitter contact layer.

[0054] The material of the substrate 200 includes gallium arsenide or indium phosphide. In this embodiment, the material of the substrate 200 is gallium arsenide.

[0055] Please continue to refer to Figure 4 and Figure 5, an emitter material layer 201 is formed on the substrate 200 ; a base material layer 202 is formed on the emitter material layer 201 ; and a collector material layer 203 is formed on the base material layer 202 .

[0056] In this embodiment, the material of the emitter material layer 201 includes one or more of gallium arsenide, indium gallium arsenide and indium gallium phosphide; the material of the base material layer 202 includes gallium arsenide; and the material of the collector material layer 203 includes gallium arsenide.

[0057] In this embodiment, the thickness of the emitter material layer 201 is in the range of 0.2 μm to 2 μm; the thickness of the base material layer 202 is in the range of 40 nm to 80 nm; and the thickness of the collector material layer 203 is in the range of 1 μm to 2 μm.

[0058] The emitter material layer 201 is used to form an emitter layer, the base material layer 202 is used to form a base layer, and the collector material layer 203 is used to form a collector layer.

[0059] In this embodiment, it is used to form an NPN type heterojunction bipolar transistor, that is, the conductivity type of the collector layer and the emitter layer is N type, and the conductivity type of the base layer is P type. In another embodiment, it can also be used to form a PNP type heterojunction bipolar transistor.

[0060] In this embodiment, the conductive ion doping concentration in the emitter material layer 201 is in the range of 1.0×10 17 atom / cm 3 Up to 2.0×10 19 atom / cm 3 The conductive ion doping concentration in the base material layer is in the range of 1.0×10 19 atom / cm 3 Up to 5.5×10 19 atom / cm 3 The conductive ion doping concentration in the collector material layer 203 is in the range of 1×10 15 atom / cm 3 Up to 5.0×10 18 atom / cm 3 .

[0061] In this embodiment, a barrier material layer (not shown in the figure) is also formed on the surface of the base material layer 202, and the collector material layer 203 is formed on the surface of the barrier material layer. The material of the barrier material layer is different from that of the base material layer 202, and the conductivity type of the barrier material layer is different from that of the base material layer 202. The barrier material layer is used to protect the base layer to reduce the influence of surface defects on the performance of the base layer. In the etching process of forming the collector, it also serves as an etching stop layer to protect the base layer. In another embodiment, the barrier material layer may not be formed.

[0062] In this embodiment, the material of the barrier material layer includes indium gallium phosphide; the thickness of the barrier material layer ranges from 30 nm to 50 nm; the conductive ion doping concentration in the barrier material layer ranges from 2.0×10 17 atom / cm 3 Up to 5.0×10 17 atom / cm 3 .

[0063] Please refer to Figures 6 to 9 , Figure 6 for Figures 7 to 9 A top view of the structure. Figure 7 yes Figure 6 Schematic diagram of the cross-sectional structure along the MM1 direction, Figure 8 yes Figure 6 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig. 9 yes Figure 6 The cross-sectional structure schematic diagram along the FF1 direction, etching the collector material layer 203 (such as Figure 4 As shown), to form a plurality of collector layers 205, and the plurality of collector layers 205 are arranged along the first direction X.

[0064] In this embodiment, a collector contact layer 204 is further formed on the surface of each collector layer 205 .

[0065] Specifically, the method for forming the plurality of collector contact layers 204 and the plurality of collector layers 205 also includes: forming the plurality of collector contact layers 204 on a portion of the surface of the collector material layer 203; and etching the collector material layer 203 using the plurality of collector contact layers 204 as masks to form the plurality of collector layers 205.

[0066] In this embodiment, more specifically, the collector material layer 203 is etched using the plurality of collector contact layers 204 as masks until the barrier material layer on the surface of the base material layer 202 is exposed, so as to form a plurality of collector layers 205. Here, due to the barrier material layer on the surface of the base material layer 202, in the process of etching the collector material layer 203, a process having different etching selectivities for the base material layer 202 and the barrier material layer can be selected, so that the barrier material layer acts as an etching stop layer, reducing etching damage to the base material layer 202, and facilitating improving the performance of the formed base layer.

[0067] In another embodiment, the barrier material layer may not be formed, and the collector material layer may be etched using the plurality of collector contact layers as masks until the surface of the base material layer is exposed, so as to form a plurality of collector layers.

[0068] In this embodiment, a plurality of collector layers 205 are formed on the collector surface region cp.

[0069] In this embodiment, a plurality of the collector contact layers 204 are also arranged along a second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

[0070] In this embodiment, the plurality of collector layers 205 are further arranged along the second direction Y. Here, by arranging the plurality of collector layers 205 along the second direction Y, the total area of ​​the collector layer 205 is further reduced under the requirement of a fixed emitter layer area, and the parasitic capacitance (i.e., junction capacitance) C between the collector layer 205 and the subsequently formed base layer is further reduced. BC A base contact layer may be provided on the surface of the base layer between adjacent collector layers 205 in the second direction Y (see the subsequent description of the first contact strip).

[0071] It should be noted that Figure 6 Only a number of collector layers arranged in a 3×2 array are shown. The number and arrangement of the collector layers are not limited thereto and can be adjusted according to actual needs. For example, the arrangement of the collector layers can also be a 2×3 array.

[0072] In another embodiment, a plurality of the collector layers are arranged along the first direction and extend along the second direction, but are not arranged along the second direction. For example, the plurality of collector layers are arranged in a 3×1 array.

[0073] In yet another embodiment, a plurality of the collector layers are arranged along a first direction and extend along the first direction, but are not arranged along the second direction.

[0074] In this embodiment, the material of the collector contact layer 204 includes metal, and the metal includes one or more of gold germanium, nickel and gold.

[0075] In this embodiment, the formation process of the collector contact layer 204 includes an evaporation process.

[0076] In this embodiment, the method for forming the collector contact layer 204 also includes: forming a first mask layer (not shown in the figure) on the surface of the collector material layer 203, the first mask layer having a first mask groove (not shown in the figure), the first mask groove exposing a portion of the collector material layer 203; forming the collector contact layer 204 in the first mask groove; and removing the first mask layer.

[0077] In this embodiment, the material of the first mask layer includes photoresist.

[0078] The process of etching the collector material layer 203 includes one of a dry etching process and a wet etching process or a combination of the two. In this embodiment, the process of etching the collector material layer 203 is a dry etching process.

[0079] Please refer to Figures 10 to 13 , Fig.10 for Figures 11 to 13 A top view of the structure. Fig.11 yes Fig.10 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.12 yes Fig.10 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.13 yes Fig.10 The cross-sectional structure schematic diagram along the FF1 direction, etching the base material layer 202 (such as Figure 6 As shown), until the emitter material layer 201 is exposed, a base layer 206 is formed, the base layer 206 includes a plurality of collector regions (not shown in the figure), a plurality of electrical contact regions S1 and a plurality of first isolation regions S2, the plurality of collector regions are arranged along the first direction X and the second direction Y, and the collector layer 205 is formed on the collector regions.

[0080] In this embodiment, the base layer 206 is formed on the base mesa region bp.

[0081] In this embodiment, the method for forming the base layer 206 also includes: forming a second mask layer (not shown in the figure) on the base platform area bp; using the second mask layer as a mask, etching the base material layer 202 to form the base layer 206.

[0082] The collector region is used to define the position of the collector layer 205, and the collector layer 205 is located on the collector region; the electrical contact region S1 is used to define the position where the base contact layer is in electrical contact with the base layer 206; and the first isolation region S2 is used to define the position of the first isolation structure.

[0083] In this embodiment, the electrical contact region S1 is located between the collector regions adjacent to each other in the second direction Y, and the first isolation region S2 is located between the collector regions adjacent to each other in the first direction X.

[0084] In another embodiment, a plurality of collector regions are arranged along the first direction and extend along the second direction but are not arranged along the second direction, and the electrical contact region is located at one side of the collector region in the second direction.

[0085] In this embodiment, the electrical contact regions S1 located in the first direction X are interconnected and extend along the first direction X.

[0086] In this embodiment, a plurality of first isolation regions S2 are located between the collector regions adjacent to each other in the first direction X, and are arranged along the second direction Y at intervals.

[0087] In another embodiment, the first isolation region is adjacent to the electrical contact region.

[0088] In another embodiment, the electrical contact region is located between the collector regions adjacent to each other in the second direction and arranged along the first direction; the first isolation region is located between the collector regions adjacent to each other in the first direction, and the first isolation regions located in the second direction are interconnected and extend along the second direction, and the area of ​​the first isolation region is increased by increasing the size of the first isolation region along the second direction.

[0089] In this embodiment, the barrier material layer is further etched to form a barrier layer.

[0090] Specifically, before etching the base material layer 202 , the barrier material layer is etched using the second mask layer as a mask to form a barrier layer.

[0091] In this embodiment, the material of the second mask layer includes photoresist.

[0092] Please refer to Figures 14 to 17 , Fig.14 for Figures 15 to 17 A top view of the structure. Fig.15 yes Fig.14 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.16 yes Fig.14 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.17 yes Fig.14, ions are injected into the base layer 206 located in the first isolation region S2 and the emitter material layer 201 located below the first isolation region S2 by using an ion implantation process, that is, into the emitter material layer 201 (such as Fig.10 As shown in the figure, ions are implanted into the emitter material layer 201 and the base layer 206 to form a first isolation structure 207 in the emitter material layer 201 and the base layer 206, and an emitter layer 208 is formed with the emitter material layer 201.

[0093] In this embodiment, specifically, the emitter material layer 201 on the device region C is used to form the emitter layer 208 .

[0094] In this embodiment, the first isolation structure 207 is formed between two adjacent collector layers 205 in the first direction X, and the first isolation structures 207 are arranged at intervals along the second direction Y (eg, Fig.14 shown).

[0095] In another embodiment, the first isolation structure is formed between two adjacent collector layers in the first direction, and the first isolation structures in the second direction are interconnected and extend along the second direction. By increasing the size of the first isolation structure in the second direction, the area of ​​the first isolation structure is increased, and the area of ​​the PN junction formed between the emitter layer and the base layer is further reduced, so as to further reduce the parasitic capacitance C between the emitter layer and the base layer. BE , improving the cutoff frequency and RF gain of the device.

[0096] In this embodiment, while forming the first isolation structure 207, the ion implantation process is also used to implant the ions into the emitter material layer 201 on the second isolation region I to form a second isolation structure 209 with the emitter material layer 201 on the second isolation region I.

[0097] In this embodiment, the process parameters of the ion implantation process include: the ions include one or more of boron ions, helium ions and hydrogen ions, and the implantation dose range is 1×10 13 ion / cm 2 Up to 1×10 14 ion / cm 2 .

[0098] Subsequently, the base contact layer is formed on the electrical contact region.

[0099] In this embodiment, the emitter contact layer is formed on the exposed surface of the emitter layer 208 .

[0100] In this embodiment, after forming the base contact layer, the emitter contact layer is formed. For details, please refer to Figures 18 to 25 .

[0101] Please refer to Figures 18 to 21 , Fig.18 for Figures 19 to 21 The schematic diagram of the top view of the first protective layer is omitted. Fig.19 yes Fig.18 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig. 20 yes Fig.18 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.21 yes Fig.18 The schematic diagram of the cross-sectional structure along the FF1 direction in the figure shows that a first protective layer 210 is formed on the emitter layer 208, the base layer 206 and the collector contact layer 204, and the first protective layer 210 has a first groove (not shown in the figure), and the first groove exposes part of the barrier layer; a base contact layer is formed in the first groove, and the base contact layer includes a plurality of first contact strips 302, and the first contact strips 302 extend along the first direction X, and the first contact strips 302 are located between the collector layers 205 adjacent to each other in the second direction Y.

[0102] The method for forming the base contact layer includes: forming a first contact strip 302 located on the electrical contact region, wherein the first contact strip 302 extends along the first direction X, and the first contact strip 302 connects the electrical contact regions adjacent to each other in the first direction X.

[0103] In another embodiment, the first isolation regions located in the second direction Y are connected to each other and extend along the second direction Y, and the first contact strips cross the first isolation regions.

[0104] In another embodiment, the barrier layer may not be formed, and the first groove exposes a portion of the base layer.

[0105] In this embodiment, the method for forming the first protective layer 210 includes: forming a first protective material layer on the emitter layer 208, the base layer 206 and the collector contact layer 204; forming a patterned first photoresist layer (not shown in the figure) on the surface of the first protective material layer; and etching the first protective material layer using the first photoresist layer as a mask.

[0106] The material of the first protective layer 210 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the first protective layer 210 is silicon nitride.

[0107] In this embodiment, the process for forming the base contact layer includes an evaporation process.

[0108] The base contact layer includes a multi-layer metal structure, which includes: a first metal layer, a second metal layer, a third metal layer and a fourth metal layer stacked in sequence in a direction perpendicular to the surface of the substrate 200 .

[0109] In this embodiment, the material of the first metal layer includes platinum, the material of the second metal layer includes titanium, the material of the third metal layer includes platinum, and the material of the fourth metal layer includes copper or gold.

[0110] In this embodiment, the method for forming the base contact layer further includes: forming a plurality of second contact strips 301 connected to the plurality of first contact strips 302, wherein the second contact strips 301 are located on the first isolation region S2 and extend along the second direction Y, and the second contact strips 301 are located between two adjacent collector layers 205 in the first direction X.

[0111] Here, relative to setting only a plurality of first contact strips, a plurality of second contact strips 301 in the base contact layer are set between the collector layers 205 adjacent to each other in the first direction X, so as to disperse the base current, reduce the heat concentration effect caused by the current concentration, and improve the heat dissipation capacity. Moreover, the setting of the plurality of second contact strips 301 and the plurality of first contact strips 302 makes the distribution of the base contact layer more uniform, which is beneficial to reduce stress and prevent device deformation.

[0112] In this embodiment, the method for forming the base contact layer further includes: forming a base terminal 300 on one side of the collector layer 205 in the second direction Y, and connecting the second contact strips 301 to the base terminal 300. Specifically, the base terminal 300 is formed on the base lead-out region bc.

[0113] In another embodiment, the base terminal may not be formed. By omitting the base terminal, the base layer does not need to provide a placement position for the base terminal, which can effectively reduce the area of ​​the base layer, further reduce the area of ​​the PN junction formed between the base layer and the emitter layer, and further reduce the parasitic capacitance C between the emitter layer and the base layer. BE , thereby improving the RF gain and cutoff frequency of the device structure and improving the performance of the device structure. Since the base layer removes the portion that is provided for the base terminal and cannot contribute to current, the utilization efficiency of the device structure can be effectively improved.

[0114] In another embodiment, the electrical contact regions located in the first direction X are interconnected and extend along the first direction X, the base contact layer includes a plurality of first contact strips and a base terminal, the second contact strips are omitted, each of the first contact strips is located between the adjacent collector layers in the second direction Y and extends along the first direction X; the base terminal is located on one side of the plurality of collector layers in the first direction X.

[0115] In another embodiment, the base contact layer comprises only the first contact strip.

[0116] In this embodiment, the method for forming the base contact layer further includes: performing an annealing treatment on the base contact layer so that the base contact layer is embedded in the barrier layer and the material of the base contact layer is diffused into the base layer so that the base contact layer is in contact with the base layer. The annealing treatment is used to reduce the ohmic contact resistance between the base contact layer and the base layer 206.

[0117] After forming the first isolation structure 207 , the base contact layer is formed.

[0118] In this embodiment, the first isolation structure 207 is formed between two adjacent collector layers 205 in the first direction X; and the second contact strip 301 is located on the first isolation structure 207 .

[0119] In another embodiment, the electrical contact region is formed between two adjacent collector layers in the first direction, the isolation region is formed between two adjacent collector layers in the second direction, and the first isolation structure is formed between two adjacent collector layers in the second direction; the first contact strip is located on the first isolation structure.

[0120] Subsequently, an emitter contact layer is formed on the emitter layer 208. The emitter contact layer is formed on both sides of the base layer 206 in the first direction X and extends along the second direction Y. For details, please refer to Figure 22 to Figure 25 .

[0121] Please refer to Figure 22 to Figure 25 , Fig. 22 for Figure 23 to Figure 25 The schematic diagram of the top view of the first protective layer and the second protective layer is omitted. Fig.23 yes Fig. 22 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.24 yes Fig. 22 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.25 yes Fig. 22In the schematic diagram of the cross-sectional structure along the FF1 direction, a second protective layer 211 is formed on the surface of the first protective layer 210 and the base contact layer; a second groove (not shown in the figure) is formed in the first protective layer 210 and the second protective layer 211, and the second groove exposes part of the emitter layer 208; and the emitter contact layer 303 is formed in the second groove.

[0122] At this point, the emitter layer 208 is placed at the bottom layer to support the emitter contact layer 303 and the base layer 209, so the area of ​​the emitter layer 208 is the largest. Under the requirement of a fixed emitter layer 208 area, the area of ​​the PN junction formed between the collector layer 205 and the base layer 206 is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer 205 and the base layer 206. BC By forming a plurality of collector regions arranged along the first direction X, the total area of ​​the collector layer 205 is reduced, and the parasitic capacitance (ie, junction capacitance) C between the collector layer 205 and the base layer 206 is further reduced. BC At the same time, by providing a first isolation structure in the emitter layer 208 and the base layer 209, the PN junction area formed between the emitter layer 208 and the base layer 209 can be reduced, thereby reducing the parasitic capacitance C between the emitter layer 208 and the base layer 209. BE , which is beneficial to improve the cutoff frequency and RF gain of the device.

[0123] In this embodiment, the method for forming the second protective layer 211 includes: forming a second protective material layer on the surface of the first protective layer 210 and the base contact layer; forming a patterned second photoresist layer (not shown in the figure) on the surface of the second protective material layer; and etching the second protective material layer using the second photoresist layer as a mask.

[0124] The material of the second protective layer 211 includes a dielectric material, and the dielectric material includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the second protective layer 211 is silicon nitride.

[0125] The emitter contact layer 303 includes a stack of multiple metal layers, and the materials of two adjacent metal layers are different from each other; the material of the metal layer includes titanium or platinum. In this embodiment, the emitter contact layer 303 includes a stack of a titanium metal layer, a platinum metal layer, a titanium metal layer, a platinum metal layer and a titanium metal layer.

[0126] In this embodiment, the emitter contact layer 303 is formed on the two emitter extraction regions ec.

[0127] Subsequently, a collector conductive structure is formed on the surface of the collector contact layer 204 .

[0128] In this embodiment, an emitter conductive structure is further formed on the surface of the emitter contact layer 303 ; and a base conductive structure is formed on the surface of the base contact layer.

[0129] The materials of the collector conductive structure, the emitter conductive structure and the base conductive structure include metal, and the metal includes one or more combinations of gold, titanium, platinum, copper, aluminum, tungsten, cobalt, nickel and tantalum. In this embodiment, the metal includes titanium, platinum and gold.

[0130] In this embodiment, the base conductive structure includes a first base conductive portion and a second base conductive portion located on the first base conductive portion, and the first base conductive portion is electrically connected to the base terminal; the emitter conductive structure includes an emitter conductive portion and an emitter conductive bus, the emitter conductive bus is connected to the emitter conductive portion, the emitter conductive portion is electrically connected to the emitter contact layer, the emitter conductive portion extends along the second direction Y, and the emitter conductive bus extends along the first direction X; the collector conductive structure includes a plurality of collector conductive portions and a collector conductive bus, a plurality of collector conductive portions are connected to a plurality of collector contact layers, the collector conductive bus is connected to a plurality of collector conductive portions, a plurality of collector conductive portions extend along the second direction Y, and are arranged along the first direction X, and the collector conductive bus extends along the first direction X.

[0131] In this embodiment, the formation method of the collector conductive structure, the emitter conductive structure and the base conductive structure can be referred to Figures 26 to 40 .

[0132] Please refer to Figure 26 to Figure 29 , Fig.26 for Figure 27 to Figure 29 The schematic diagram of the top view of the first protective layer, the second protective layer and the third protective layer is omitted. Fig. 27 yes Fig.26 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.28 yes Fig.26 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.29 yes Fig.26In the schematic diagram of the cross-sectional structure along the FF1 direction, a third protective layer 212 is formed on the substrate; a first opening 213 is formed in the third protective layer 212, the first opening 213 is located on the emitter lead-out region ec, and exposes the emitter contact layer 303; a second opening 214 is formed in the second protective layer 211 and the third protective layer 212, the second opening 214 exposes the base contact layer; a plurality of third openings 215 are formed in the first protective layer 210, the second protective layer 211 and the third protective layer 212, and one of the third openings 215 exposes one of the collector contact layers 204.

[0133] Specifically, the second opening 214 exposes the base terminal 300 .

[0134] In this embodiment, the method for forming the third protective layer 212 includes: forming a third protective material layer on the surface of the second protective layer 211 and the emitter contact layer 303; forming a patterned third photoresist layer (not shown in the figure) on the surface of the third protective material layer; and etching the third protective material layer using the third photoresist layer as a mask.

[0135] The material of the third protective layer 212 includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the third protective layer 212 is silicon nitride.

[0136] Please refer to Figure 30 to Figure 33 , Fig.30 for Figure 31 to Figure 33 The schematic diagram of the top view of the first protective layer, the second protective layer and the third protective layer is omitted. Fig.31 yes Fig.30 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.32 yes Fig.30 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.33 yes Fig.30The schematic diagram of the cross-sectional structure along the FF1 direction in the figure forms the emitter conductive structure and the first base conductive part 305a, the emitter conductive structure includes an emitter conductive part 304a and an emitter conductive bus 304b, the emitter conductive bus 304b is connected to the emitter conductive part 304a, the emitter conductive part 304a extends along the second direction Y, the emitter conductive bus 304b extends along the first direction X, the emitter conductive part 304a is located in the first opening 213 to be electrically connected to the emitter contact layer 303, the emitter conductive bus 304b is located on the surface of the third protective layer 212, and the first base conductive part 305a is located in the second opening 214 to be electrically connected to the base contact layer.

[0137] The emitter conductive structure is used to draw out the current in the emitter layer 208 .

[0138] The formation process of the emitter conductive structure and the first base conductive part 305a includes a lift-off process.

[0139] Please refer to Figure 34 to Figure 36 , Fig.34 The viewing direction is the same as Fig.31 , Fig.35 The viewing direction is the same as Fig.32 , Fig.36 The viewing direction is the same as Fig.33 A packaging material layer 216 is formed on the surface of the emitter conductive structure, the surface of the first base conductive portion 305a, and the surface of the third protective layer 212, and the packaging material layer 216 exposes the surface of the first base conductive portion 305a and exposes a plurality of the third openings 215.

[0140] The material of the packaging material layer 216 includes a polymer material. In this embodiment, the material of the packaging material layer 216 is polyimide.

[0141] Please refer to Figures 37 to 40 , Fig.37 for Figures 38 to 40 The schematic diagram of the top view of the structure of the first protective layer, the second protective layer, the third protective layer and the packaging material layer is omitted. Fig.38 yes Fig.37 Schematic diagram of the cross-sectional structure along the MM1 direction, Fig.39 yes Fig.37 Schematic diagram of the cross-sectional structure along the NN1 direction, Fig.40 yes Fig.37Schematic diagram of the cross-sectional structure along the FF1 direction, a second base conductive portion 305b is formed on the surface of the first base conductive portion 305a, and a collector conductive structure is formed in the plurality of the third openings 215 and on the surface of part of the packaging material layer 216, the collector conductive structure includes a plurality of collector conductive portions 306a and a collector conductive bus 306b, the collector conductive bus 306b is connected to the plurality of the collector conductive portions 306a, the plurality of collector conductive portions 306a extend along the second direction Y and are arranged along the first direction X, the collector conductive bus 306b extends along the first direction X, the collector conductive bus 306b is located on the surface of the packaging material layer 216, each of the collector conductive portions 306a is located in the third openings 215 running along the second direction Y, and is located on the surface of the packaging material layer 216 between adjacent third openings 215, and the second base conductive portion 305b is located on the surface of the first base conductive portion 305a.

[0142] The formation process of the second base conductive portion 305 b and the collector conductive structure includes a lift-off process.

[0143] In this embodiment, the base conductive structure includes the first base conductive portion 305a and the second base conductive portion 305b. The base conductive structure is used to draw out the current of the base layer 206, and is composed of the first base conductive portion 305a and the second base conductive portion 305b. Therefore, it has a large thickness, which is conducive to reducing the current density.

[0144] The collector conductive structure is used to draw out the current in the collector layer 205 .

[0145] In this embodiment, the second base conductive portion 305 b also extends to a portion of the surface of the packaging material layer 216 .

[0146] In this embodiment, the base conductive structure and the collector conductive bus 306 b are located on two opposite sides of the base layer 206 in the second direction Y.

[0147] In this embodiment, the emitter conductive bus 304b and the collector conductive bus 306b are both located on a side of the collector layer away from the base conductive structure.

[0148] In another embodiment, the base contact layer includes a plurality of first contact strips and a plurality of second contact strips, the base terminal is omitted, the base conductive structure is located on the surface of the plurality of second contact strips, and the base conductive structure is located between two adjacent collector layers in the first direction.

[0149] In another embodiment, the base contact layer includes only a plurality of first contact strips, a plurality of collector conductive portions extend along the first direction and are arranged along the second direction, the collector conductive bus extends along the second direction, the base conductive structure is located on the surfaces of the plurality of first contact strips, and the base conductive structure is located between two adjacent collector layers in the second direction.

[0150] In another embodiment, the base contact layer includes a plurality of first contact strips and a base terminal, the second contact strip is omitted, a plurality of collector conductive portions extend along the first direction and are arranged along the second direction, the collector conductive bus extends along the second direction, the base terminal is located on one side of the plurality of collector layers in the first direction X, the base conductive structure is located on the surface of the base terminal, and the base conductive structure and the collector conductive bus are located on opposite sides of the base layer in the first direction X.

[0151] In this embodiment, after the conductive structure is formed, a fourth protective layer (not shown in the figure) is further formed on the surface of the conductive structure and the surface of the packaging material layer 216 .

[0152] The material of the fourth protective layer includes a dielectric material, and the dielectric material includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbon nitride. In this embodiment, the material of the fourth protective layer is silicon nitride.

[0153] Accordingly, the embodiment of the present invention also provides a heterojunction bipolar transistor device formed by the above method, please continue to refer to Figures 37 to 40 The heterojunction bipolar transistor device includes: a substrate 200; an emitter layer 208 located on the substrate, a base layer 206 located on the emitter layer 208, a plurality of collector layers 205 and a base contact layer located on the base layer 206, and a first isolation structure 207 located in the emitter layer 208 and the base layer 206, the base layer includes a plurality of collector regions (not shown in the figure), a plurality of electrical contact regions S1 and a plurality of first isolation regions S2, the plurality of collector regions are arranged along a first direction X, the collector layer 205 is located on the collector region, the base contact layer is located on the electrical contact region, and the first isolation structure 207 is located in the first isolation region S2.

[0154] At this point, the emitter layer 211 is placed at the bottom layer to carry the emitter contact layer 212 and the base layer 209, so the area of ​​the emitter layer 211 is the largest. Under the requirement of a fixed emitter layer 211 area, the area of ​​the PN junction formed between the collector layer 205 and the base layer 209 is small, thereby reducing the parasitic capacitance (i.e., junction capacitance) C between the collector layer 205 and the base layer 209.BC By forming a plurality of collector regions arranged along the first direction X, the total area of ​​the collector layer 205 is reduced, and the parasitic capacitance (ie, junction capacitance) C between the collector layer 205 and the base layer 206 is further reduced. BC At the same time, by providing a first isolation structure in the emitter layer 208 and the base layer 209, the PN junction area formed between the emitter layer 208 and the base layer 209 can be reduced, thereby reducing the parasitic capacitance C between the emitter layer 208 and the base layer 209. BE , which is beneficial to improve the cutoff frequency and RF gain of the device.

[0155] It should be noted that there is no overlap between the plurality of collector regions, the plurality of electrical contact regions S1 and the plurality of first isolation regions S2.

[0156] In this embodiment, the substrate 200 includes a device region C and a second isolation region I, and the second isolation region I surrounds the device region C.

[0157] Specifically, a plurality of collector layers 205 are arranged along the first direction X.

[0158] In this embodiment, some of the collector regions are further arranged along the second direction, that is, some of the collector layers 205 are further arranged along the second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

[0159] In another embodiment, a plurality of the collector layers are arranged along the first direction and extend along the second direction, but are not arranged along the second direction. For example, the plurality of collector layers are arranged in a 3×1 array.

[0160] In this embodiment, the heterojunction bipolar transistor device further includes: a second isolation structure 209 located on the second isolation region I and on the side wall of the emitter layer 208 .

[0161] In this embodiment, the device region C includes a base mesa surface region bp; and the base layer 206 is located on the base mesa surface region bp.

[0162] In this embodiment, the base mesa surface area bp includes a base lead-out area bc, a gap area g and a collector mesa surface area cp arranged along the second direction Y, and the base lead-out area bc and the collector mesa surface area cp are located on both sides of the gap area g; a plurality of collector layers 205 are located on the collector mesa surface area cp.

[0163] In this embodiment, the base contact layer includes a plurality of first contact strips 302, which are located on the electrical contact region S1 and extend along the first direction X. The first contact strips 302 connect the adjacent electrical contact regions S1 in the first direction X. The first contact strips 302 are located between the adjacent collector layers 205 in the second direction Y.

[0164] In this embodiment, the electrical contact region S1 is located between the collector regions adjacent to each other in the second direction Y, and the first isolation region S2 is located between the collector regions adjacent to each other in the first direction X.

[0165] In this embodiment, the electrical contact regions S1 located in the first direction X are interconnected and extend along the first direction X.

[0166] In this embodiment, a plurality of first isolation regions S2 are located between the collector regions adjacent to each other in the first direction X, and are arranged along the second direction Y at intervals.

[0167] In another embodiment, the first isolation region is adjacent to the electrical contact region.

[0168] In another embodiment, the electrical contact region is located between the collector regions adjacent to each other in the second direction and arranged along the first direction; the first isolation region is located between the collector regions adjacent to each other in the first direction, the first isolation regions located in the second direction are interconnected and extend along the second direction, and each first contact strip spans the first isolation region.

[0169] In this embodiment, the base contact layer further includes: a plurality of second contact strips 301 connected to the plurality of first contact strips 302 , the second contact strips 301 are located on the first isolation region S2 and extend along the second direction Y, and the second contact strips 301 are located between two adjacent collector layers 205 in the first direction X.

[0170] Here, relative to only setting a plurality of first contact strips 302, a plurality of second contact strips 301 in the base contact layer are set between the collector layers 205 adjacent to each other in the first direction X, so as to disperse the base current, reduce the heat concentration effect caused by the current concentration, and improve the heat dissipation capacity. Moreover, the setting of the plurality of second contact strips 301 and the plurality of first contact strips 302 makes the distribution of the base contact layer more uniform, which is beneficial to reducing stress and preventing device deformation.

[0171] In this embodiment, the base contact layer further includes a base terminal 300, and the plurality of second contact strips 301 are connected to the base terminal 300, and the base terminal 300 is located on one side of the plurality of collector layers 205 in the second direction Y. Specifically, the base terminal 300 is located on the base lead-out region bc.

[0172] In this embodiment, the heterojunction bipolar transistor device also includes: a blocking layer (not shown in the figure) located on the surface of the base layer 206, a plurality of collector layers 205 located on part of the surface of the blocking layer, the material of the blocking layer is different from the material of the base layer 206, and the conductivity type of the blocking layer is different from the conductivity type of the base layer 206; the base contact layer is embedded in the blocking layer and in contact with the base layer 206.

[0173] In this embodiment, the heterojunction bipolar transistor device further includes: a base conductive structure electrically connected to the base contact layer. Specifically, the base conductive structure includes a first base conductive portion 305a and a second base conductive portion 305b located on the first base conductive portion 305a, and the first base conductive portion 305a is electrically connected to the base terminal 300.

[0174] In this embodiment, the device region C further includes two emission extraction regions ec, the two emission extraction regions ec and the base mesa region bp are arranged along the first direction X, and the two emission extraction regions ec are respectively located on both sides of the base mesa region bp.

[0175] In this embodiment, the heterojunction bipolar transistor device further includes: an emitter contact layer 303 located on the emitter layer 208, the emitter contact layer 303 is located on both sides of the base layer 206 in the first direction X, and extends along the second direction Y. Specifically, the emitter contact layer 303 is located on the two emitter extraction regions ec.

[0176] In this embodiment, the heterojunction bipolar transistor device also includes: an emitter conductive structure electrically connected to the emitter contact layer 303; the emitter conductive structure includes an emitter conductive portion 304a and an emitter conductive bus 304b, the emitter conductive bus 304b is connected to the emitter conductive portion 304a, the emitter conductive portion 304a is electrically connected to the emitter contact layer 303, the emitter conductive portion 304a extends along the second direction Y, and the emitter conductive bus 304a extends along the first direction X.

[0177] In this embodiment, the heterojunction bipolar transistor device further includes: a collector contact layer 204 located on the surface of each collector layer 205, a collector conductive structure electrically connected to the collector contact layer 204, and a base conductive structure electrically connected to the base contact layer.

[0178] In this embodiment, the collector conductive structure includes a plurality of collector conductive parts 306a and a collector conductive bus 306b. The plurality of collector conductive parts 306a are electrically connected to the plurality of collector contact layers 204, and the collector conductive bus 306b is connected to the plurality of collector conductive parts 306a.

[0179] In this embodiment, a plurality of collector conductive portions 306 a extend along the second direction Y and are arranged along the first direction X, and the collector conductive bus 306 b extends along the first direction X.

[0180] In this embodiment, the base conductive structure and the collector conductive bus 306 b are located on two opposite sides of the base layer 206 in the second direction Y.

[0181] In another embodiment, the base conductive structure is located between two adjacent collector layers in the first direction.

[0182] In this embodiment, the emitter conductive bus 304b and the collector conductive bus 306b are both located on a side of the collector layer away from the base conductive structure.

[0183] In another embodiment, the base contact layer includes a plurality of first contact strips and a plurality of second contact strips, the base terminal is omitted, the base conductive structure is located on the surface of the plurality of second contact strips, and the base conductive structure is located between two adjacent collector layers in the first direction.

[0184] In another embodiment, the base contact layer includes only a plurality of first contact strips, a plurality of collector conductive portions extend along the first direction and are arranged along the second direction, the collector conductive bus extends along the second direction, the base conductive structure is located on the surfaces of the plurality of first contact strips, and the base conductive structure is located between two adjacent collector layers in the second direction.

[0185] In another embodiment, the base contact layer includes a plurality of first contact strips and a base terminal, the second contact strip is omitted, a plurality of collector conductive portions extend along the first direction and are arranged along the second direction, the collector conductive bus extends along the second direction, the base terminal is located on one side of the plurality of collector layers in the first direction X, the base conductive structure is located on the surface of the base terminal, and the base conductive structure and the collector conductive bus are located on opposite sides of the base layer in the first direction X.

[0186] Figure 41 to Figure 43 It is a structural schematic diagram of each step of a method for forming a heterojunction bipolar transistor device according to another embodiment of the present invention.

[0187] This embodiment is based on the previous embodiment ( Fig. 9 ) continues to describe the method for forming a heterojunction bipolar transistor device, and the rest is the same as the previous embodiment. Fig.10 ) is mainly different in that the first isolation region and the electrical contact region are distributed differently. Specific description will be given below in conjunction with the accompanying drawings.

[0188] Please refer to Fig.41 , Fig.41 The collector contact layer 204 is omitted, and the base material layer 202 (such as Figure 6 As shown), until the emitter material layer 201 is exposed, a base layer 406 is formed, the base layer 406 includes a plurality of collector regions (not shown in the figure), a plurality of electrical contact regions n1 and a plurality of first isolation regions n2, the plurality of collector regions are arranged along a first direction X, and the collector layer 205 is formed on the collector regions.

[0189] In this embodiment, the first isolation region n2 is adjacent to the electrical contact region n1.

[0190] In this embodiment, the electrical contact region n1 is located between the adjacent collector regions in the second direction Y and is arranged along the first direction X; the first isolation region n2 is located between the adjacent collector regions in the first direction X, and the first isolation regions n2 located in the second direction Y are interconnected and extend along the second direction Y.

[0191] In another embodiment, the electrical contact region is located between the collector regions adjacent to each other in the second direction, and the electrical contact regions located in the first direction are interconnected and extend along the first direction; the first isolation region is located between the collector regions adjacent to each other in the first direction and arranged along the second direction; the first isolation region is adjacent to the electrical contact region.

[0192] Please refer to Fig.42, an ion implantation process is used to implant ions into the base layer 406 located in the first isolation region n2 and the emitter material layer 201 located below the first isolation region n2, that is, ions are implanted into the emitter material layer 201 and the base layer 406 between two adjacent collector layers 205 in the first direction X to form a first isolation structure 407 in the emitter material layer 201 and the base layer 406, and to form an emitter layer 408 with the emitter material layer 201.

[0193] Please refer to Fig.43 , the base contact layer is formed on the electrical contact region n1, the base contact layer includes a plurality of first contact strips 602, the first contact strips 602 extend along the first direction X, the first contact strips 602 connect the adjacent electrical contact regions n1 in the first direction X, and the first contact strips 602 are located between the adjacent collector layers 205 in the second direction Y.

[0194] In this embodiment, the first contact strip 602 crosses the first isolation region n2.

[0195] Here, relative to the previous embodiment, by increasing the size of the first isolation region n2 along the second direction, thereby increasing the area of ​​the first isolation region n2, the area of ​​the PN junction formed between the emitter layer 408 and the base layer 406 is further reduced, so as to further reduce the parasitic capacitance C between the emitter layer 408 and the base layer 406. BE , improving the cutoff frequency and RF gain of the device.

[0196] In this embodiment, the method for forming the base contact layer also includes: forming a plurality of second contact strips 601 connected to the plurality of first contact strips 602, wherein the second contact strips 601 are located on the first isolation region n2 and extend along the second direction Y, and the second contact strips 601 are located between two adjacent collector layers 205 in the first direction X.

[0197] In this embodiment, the method for forming the base contact layer further includes: forming a base terminal 600 on one side of the collector layer 205 in the second direction Y, and connecting the second contact strips 601 to the base terminal 600. Specifically, the base terminal 600 is formed on the base lead-out region bc.

[0198] Subsequently, the method for forming the semiconductor device may refer to the method in the previous embodiment. Figures 22 to 40 And related narratives will not be repeated here.

[0199] Accordingly, the embodiment of the present invention also provides a heterojunction bipolar transistor device formed by the above method, please continue to refer to Fig.43 , I will not go into details here.

[0200] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A heterojunction bipolar transistor device, characterized in that: include: substrate; An emitter layer located on the substrate, a base layer located on the emitter layer, a plurality of collector layers and a base contact layer located on the base layer, and a first isolation structure located within the emitter layer and the base layer, the base layer comprising a plurality of collector regions, a plurality of electrical contact regions and a plurality of first isolation regions, the plurality of collector regions being arranged along a first direction, the collector layer being located on the collector region, the base contact layer being located on the electrical contact region, and the first isolation structure being located in the first isolation region.

2. The heterojunction bipolar transistor device according to claim 1, characterized in that: The plurality of collector regions are also arranged along a second direction, and the first direction and the second direction are perpendicular to each other.

3. The heterojunction bipolar transistor device according to claim 2, characterized in that: The electrical contact region is located between the collector regions adjacent to each other in the second direction, and the first isolation region is located between the collector regions adjacent to each other in the first direction.

4. The heterojunction bipolar transistor device according to claim 3, characterized in that: The electrical contact regions located in the first direction are connected to each other and extend along the first direction.

5. The heterojunction bipolar transistor device according to claim 3, characterized in that: The first isolation regions located in the second direction are connected to each other and extend along the second direction.

6. The heterojunction bipolar transistor device according to claim 3, characterized in that: The base contact layer includes a plurality of first contact strips, wherein the first contact strips are located on the electrical contact region and extend along the first direction, and the first contact strips are located between the collector layers adjacent to each other in the second direction.

7. The heterojunction bipolar transistor device according to claim 6, characterized in that: The first contact strip crosses the first isolation region.

8. The heterojunction bipolar transistor device according to claim 6, characterized in that: The base contact layer further includes: a plurality of second contact strips connected to the plurality of first contact strips, the second contact strips are located on the first isolation region and extend along the second direction, and the second contact strips are located between two adjacent collector layers in the first direction.

9. The heterojunction bipolar transistor device according to claim 1, characterized in that: Also includes: A barrier layer is located on the surface of the base layer, and a plurality of collector layers are located on a portion of the surface of the barrier layer. The material of the barrier layer is different from that of the base layer, and the conductivity type of the barrier layer is different from that of the base layer. The base contact layer is embedded in the barrier layer and contacts the base layer.

10. The heterojunction bipolar transistor device according to claim 3, characterized in that: Also includes: A collector contact layer located on the surface of each collector layer, a collector conductive structure electrically connected to the collector contact layer, and a base conductive structure electrically connected to the base contact layer; the collector conductive structure includes a plurality of collector conductive parts and a collector conductive bus, the plurality of collector conductive parts are electrically connected to the plurality of collector contact layers, and the collector conductive bus is connected to the plurality of collector conductive parts.

11. The heterojunction bipolar transistor device according to claim 10, characterized in that: A plurality of collector conductive parts extend along the second direction and are arranged along the first direction, and the collector conductive bus extends along the first direction; the base conductive structure and the collector conductive bus are located on two opposite sides of the base layer in the second direction, or the base conductive structure is located between two adjacent collector layers in the first direction.

12. The heterojunction bipolar transistor device according to claim 10, characterized in that: A plurality of collector conductive parts extend along the first direction and are arranged along the second direction, and the collector conductive bus extends along the second direction; the base conductive structure is located between two adjacent collector layers in the second direction, or the base conductive structure and the collector conductive bus are located on opposite sides of the base layer in the first direction.

13. A method for forming a heterojunction bipolar transistor device, characterized in that: include: providing a substrate; forming an emitter material layer on the substrate; forming a base material layer on the emitter material layer; forming a collector material layer on the base material layer; Etching the collector material layer to form a plurality of collector layers, wherein the plurality of collector layers are arranged along a first direction; Etching the base material layer until the emitter material layer is exposed to form a base layer, wherein the base layer includes a plurality of collector regions, a plurality of electrical contact regions and a plurality of first isolation regions, wherein the plurality of collector regions are arranged along a first direction, and the collector layer is formed on the collector regions; Using an ion implantation process, ions are implanted into the base layer located in the first isolation region and the emitter material layer located below the first isolation region to form a first isolation structure in the emitter material layer and the base layer, and an emitter layer is formed by the emitter material layer; A base contact layer is formed on the electrical contact region.

14. The method for forming a heterojunction bipolar transistor device according to claim 13, wherein: The process parameters of the ion implantation process include: the ions include one or more of boron ions, helium ions and hydrogen ions, and the implantation dose range is 1×10 13 ion / cm 2 Up to 1×10 14 ion / cm 2 .

15. The method for forming a heterojunction bipolar transistor device according to claim 13, characterized in that: The plurality of collector regions are also arranged along a second direction, and the first direction and the second direction are perpendicular to each other.

16. The method for forming a heterojunction bipolar transistor device according to claim 15, characterized in that: The electrical contact region is located between the collector regions adjacent to each other in the second direction, and the first isolation region is located between the collector regions adjacent to each other in the first direction.

17. The method for forming a heterojunction bipolar transistor device according to claim 16, wherein: The electrical contact regions located in the first direction are interconnected and extend along the first direction.

18. The method for forming a heterojunction bipolar transistor device according to claim 16, wherein: The first isolation regions located in the second direction are connected to each other and extend along the second direction.

19. The method for forming a heterojunction bipolar transistor device according to claim 16, wherein: The method for forming the base contact layer includes: forming a plurality of first contact strips, wherein the first contact strips are located on the electrical contact region and extend along the first direction, and the first contact strips are located between the collector layers adjacent to each other in the second direction.

20. The method for forming a heterojunction bipolar transistor device according to claim 19, wherein: The first contact strip crosses the first isolation region.

21. The method for forming a heterojunction bipolar transistor device according to claim 13, wherein: Also includes: A barrier material layer is formed on the surface of the base material layer, the collector material layer is formed on the surface of the barrier material layer, the material of the barrier material layer is different from that of the base material layer, and the conductivity type of the barrier material layer is different from that of the base material layer; The method for forming the collector layer further includes: etching the collector material layer until the barrier material layer on the surface of the base material layer is exposed to form a plurality of collector layers; The barrier material layer is etched to form a barrier layer.

22. The method for forming a heterojunction bipolar transistor device according to claim 21, characterized in that: The method for forming the base contact layer further includes: annealing the base contact layer so that the base contact layer is embedded in the barrier layer, and diffusing the material of the base contact layer into the base layer so that the base contact layer contacts the base layer.

23. The method for forming a heterojunction bipolar transistor device according to claim 19, wherein: The method for forming the base contact layer also includes: forming a plurality of second contact strips connected to the plurality of first contact strips, wherein the second contact strips are located on the first isolation region and extend along the second direction, and the second contact strips are located between two adjacent collector layers in the first direction.

24. The method for forming a heterojunction bipolar transistor device according to claim 16, wherein: Also includes: A collector contact layer is formed on the surface of each collector layer; a collector conductive structure is formed on the surface of the collector contact layer; the collector conductive structure includes a plurality of collector conductive parts and a collector conductive bus, the plurality of collector conductive parts are electrically connected to the plurality of collector contact layers, and the collector conductive bus is connected to the plurality of collector conductive parts; a base conductive structure is formed on the surface of the base contact layer.

25. The method for forming a heterojunction bipolar transistor device according to claim 24, characterized in that: A plurality of collector conductive parts extend along the second direction and are arranged along the first direction, and the collector conductive bus extends along the first direction; the base conductive structure and the collector conductive bus are located on two opposite sides of the base layer in the second direction, or the base conductive structure is located between two adjacent collector layers in the first direction.

26. The method for forming a heterojunction bipolar transistor device according to claim 24, characterized in that: A plurality of collector conductive parts extend along the first direction and are arranged along the second direction, and the collector conductive bus extends along the second direction; the base conductive structure is located between two adjacent collector layers in the second direction, or the base conductive structure and the collector conductive bus are located on opposite sides of the base layer in the first direction.

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