Field effect transistor with vertical sub-1nm gate length and preparation method thereof

Abstract

The invention relates to the technical field of transistor preparation, and provides a vertical sub-1nm gate length field effect transistor and a preparation method thereof, and the transistor comprises a step substrate, a graphene gate, a low dielectric constant dielectric layer, a high dielectric constant dielectric layer, a two-dimensional thin film channel, and contact metal. The step substrate has a step structure, and the step substrate is used as a supporting layer of the graphene gate, so that graphene in the graphene gate is attached to the side wall of the step substrate; the low-dielectric-constant dielectric layer serves as a backfill step and is meshed with the step structure of the step substrate to fill the step structure of the step substrate; the high-dielectric-constant dielectric layer is arranged at the top of the low-dielectric-constant dielectric layer as a gate dielectric layer; the two-dimensional thin film channel is arranged at the top of the high dielectric constant dielectric layer, and the contact metal is arranged on the two-dimensional thin film channel and is electrically connected with the two-dimensional thin film channel. The invention innovatively provides how to prepare vertical single-gate and multi-gate transistors with the gate length of less than 1 nanometer.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor preparation, and in particular to a vertical sub-1nm gate length field effect transistor and a preparation method thereof. Background Art

[0002] In the field of microelectronics, the continuous reduction in the size of transistors is the core driving force for the development of the industry. With the advancement of technology, the characteristic size of transistors has approached the sub-10 nanometer level, and traditional planar silicon-based devices face major challenges at this scale. In order to overcome these challenges, the industry has begun to explore new transistor structures, including dual-gate, multi-gate, and surround-gate designs. Although these new structures can continue Moore's Law, they often require more complex manufacturing processes and higher costs.

[0003] Traditional planar field effect transistors (FETs) use doping technology to form a conductive channel in a silicon substrate, constructing a metal-oxide-semiconductor (MOS) structure. As the channel length continues to shorten, the metal gate's control over the channel gradually weakens, leading to increasingly serious short channel effect problems. To solve this problem, the industry has proposed a variety of new transistor structures, including fin FETs, fully depleted silicon-on-insulator (FD-SOI) FETs, and wrap-around gate nanowire FETs.

[0004] Fin FET enhances the gate's control over the channel by designing the channel into a three-dimensional structure, effectively alleviating the short channel effect. However, as technology further develops, when the transistor size is further reduced to below 10 nanometers, the cost issue of this design becomes particularly prominent. FD-SOI FET improves the gate's control over the channel by forming an oxide layer between the silicon film and the insulator, reducing leakage current and Kink effect (warping effect), but it also brings about a larger leakage current and lateral bipolar transistor effect, and the manufacturing cost is higher.

[0005] The all-around gate nanowire FET provides greater control through a gate design that surrounds the entire channel, but this design faces many technical challenges in the manufacturing process, including complex gate manufacturing, nanowire and contact issues, and reliance on non-silicon materials, which increase manufacturing costs and reduce compatibility with traditional CMOS processes.

[0006] Although the above technical solutions have made some progress in improving the control of the gate over the conductive channel, how to further reduce the effective channel length without relying on the accuracy of the lithography machine is still the focus of current research. Two-dimensional materials are ideal for ultra-thin bodies due to their atomic layer thickness, effectively suppressing the short channel effect, and showing superior properties to traditional silicon-based materials in many aspects. They are regarded as potential mainstream materials for the next generation of CMOS processes.

[0007] At present, research on transistors based on two-dimensional materials has made extensive progress, but how to use its atomic layer thickness to prepare transistors with extremely narrow effective gate lengths is still an urgent problem to be solved. Studies have reduced the gate length to 1 nanometer by using carbon nanotubes as gates. In recent studies, a research team proposed a sub-nanometer transistor with a horizontal gate structure and a vertical channel, but this structure cannot be integrated with the planar transistor process, and its speed improvement is limited due to its large capacitance. In addition, the team also proposed a planar transistor structure that uses the conductive grain boundaries generated during the generation of molybdenum disulfide (MoS2) as a sub-nanometer gate, but the generation of this structure is random, and it is difficult to achieve large-scale array preparation.

[0008] In summary, the semiconductor industry currently has no clear solution to achieve transistors with a gate length of less than 1 nanometer that are compatible with planar transistor processes and can be prepared in scalable arrays. This remains a technical bottleneck that needs to be overcome urgently. Summary of the invention

[0009] The present invention provides a vertical sub-1nm gate length field effect transistor and a preparation method, which are used to solve the problem in the prior art that it is difficult to carry out large-scale array preparation of transistors with a gate length of less than 1nm, and innovatively proposes how to prepare vertical single-gate and multi-gate transistors with a gate length of less than 1 nanometer.

[0010] The present invention provides a vertical sub-1nm gate length field effect transistor, comprising: Step substrate, graphene gate, low dielectric constant dielectric layer, high dielectric constant dielectric layer, two-dimensional thin film channel and contact metal; The step substrate has a step structure, and the step substrate is used as a support layer of the graphene grid, so that the graphene in the graphene grid is attached to the side wall of the step substrate; The low dielectric constant dielectric layer acts as a backfill step and meshes with the step structure of the step base to fill the step structure of the step base; The high dielectric constant dielectric layer is arranged on top of the low dielectric constant dielectric layer as a gate dielectric layer; The two-dimensional thin film channel is arranged on the top of the high dielectric constant dielectric layer, and the contact metal is arranged on the two-dimensional thin film channel to form an electrical connection with the two-dimensional thin film channel.

[0011] According to a vertical sub-1 nm gate length field effect transistor provided by the present invention, the step substrate includes a side wall and a horizontal portion, and the side wall and the horizontal portion are both set to insulating material.

[0012] According to a vertical sub-1nm gate length field effect transistor provided by the present invention, the graphene gate is used as a gate electrode, the thickness is sub-1nm, and the vertical graphene is transferred to the side wall of the step substrate by wet transfer; The sidewall of the step substrate is patterned by photolithography so that the graphene has a target structure.

[0013] According to a vertical sub-1nm gate length field effect transistor provided by the present invention, after the low dielectric constant dielectric layer backfills the step structure of the step substrate, the low dielectric constant dielectric layer and the step structure are ground and polished below the junction by chemical mechanical polishing to obtain a vertical graphene surface.

[0014] The present invention also provides a method for preparing a vertical sub-1nm gate length field effect transistor, comprising: Etching a step base by using a silicon deep etching device; Generating an initial silicon dioxide layer on the surface of the step structure by a thermal oxidation device; A buffered oxide etchant is used to remove the initial silicon dioxide layer to obtain a smooth silicon surface; Generating a first silicon dioxide layer on the silicon surface by using an inductively coupled plasma enhanced chemical vapor deposition device, wherein the first silicon dioxide layer is a base silicon dioxide layer; Transferring graphene onto the sidewall of a stepped substrate having a silicon dioxide layer by wet transfer and patterning the graphene; The graphene contact metal is deposited by photolithography, and a seed layer is generated on the graphene surface by angle deposition, and a second silicon dioxide layer is generated on the seed layer surface by inductively coupled plasma enhanced chemical vapor deposition equipment; Grinding below the junction of the first silicon dioxide layer and the second silicon dioxide layer by chemical mechanical polishing to obtain vertical graphene and a flat wafer interface; A high dielectric constant dielectric layer is generated on the wafer surface above the vertical graphene, and a two-dimensional thin film channel is constructed on the top of the high dielectric constant dielectric layer; A contact metal of two-dimensional material is deposited on the two-dimensional thin film channel to complete the preparation of the transistor.

[0015] According to a method for preparing a vertical sub-1 nm gate length field effect transistor provided by the present invention, the initial silicon dioxide layer is removed by using a buffered oxide etchant to obtain a smooth silicon surface, comprising: The initial silicon dioxide layer on the surface of the step structure is washed with a BOE solution, the initial silicon dioxide layer is oxidized and etched, and the silicon surface is obtained after the initial silicon dioxide layer is removed.

[0016] According to a method for preparing a vertical sub-1 nm gate length field effect transistor provided by the present invention, the graphene is transferred to the side wall of a stepped substrate having a silicon dioxide layer by wet transfer and patterned, comprising: Transferring graphene to the step sidewall with the silicon dioxide layer by wet transfer; The graphene is vertically attached to the side wall of the step through a set stress release method; Photolithography patterning is performed on the graphene on the sidewall of the step so that the graphene has a specific structure.

[0017] According to a method for preparing a vertical sub-1 nm gate length field effect transistor provided by the present invention, the graphene is transferred to the step sidewall having a silicon dioxide layer by wet transfer, comprising: Coating a polymer support layer on the surface of graphene; Continue coating a photoresist layer on the surface of the graphene with the polymer support layer; The photoresist layer is patterned to form a stress transfer area without photoresist and a stress protection area with photoresist, so as to construct a composite sacrificial coating; transferring the graphene with the composite sacrificial coating onto a target substrate; The target substrate is a step sidewall having a silicon dioxide layer.

[0018] According to a method for preparing a vertical sub-1 nm gate length field effect transistor provided by the present invention, the graphene with a composite sacrificial coating is transferred to a target substrate, comprising: The pattern of the photoresist layer is adjusted, and the stress release degree of the photoresist layer in different thickness areas is different through photolithography, so as to achieve stress release of graphene; During the graphene stress release process, natural fracture occurs in the area of ​​the photoresist layer without photoresist protection, allowing the graphene to be completely transferred on the step sidewall with the silicon dioxide layer.

[0019] According to a method for preparing a vertical sub-1 nm gate length field effect transistor provided by the present invention, the contact metal of a two-dimensional material is deposited on a two-dimensional thin film channel to complete the preparation of the transistor, comprising: Metal titanium, palladium, chromium, gold or bismuth is deposited on the two-dimensional thin film channel to construct contact metal and complete the transistor preparation.

[0020] The present invention provides a vertical sub-1nm gate length field effect transistor and a preparation method, which further reduces the size of the transistor by using a sub-1nm vertical graphene gate, maintains compatibility with existing processes, and has the potential for large-scale manufacturing. This design can not only increase the density of transistors, but also can be prepared on a large scale, proposing a feasible path for advanced process chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 It is a schematic diagram of the structure of a vertical sub-1nm gate length field effect transistor provided by the present invention.

[0023] Figure 2 It is a schematic diagram of the manufacturing process of the single-gate vertical sub-1nm transistor provided by the present invention.

[0024] Figure 3 It is a schematic diagram of the manufacturing process of the dual-gate vertical sub-1nm transistor provided by the present invention.

[0025] Figure 4 It is a schematic diagram of the manufacturing process of the dual-gate or even multi-gate vertical sub-1nm transistor provided by the present invention.

[0026] Figure 5 It is a light microscope photo provided by the present invention.

[0027] Figure 6 This is an electrical test curve of the single-grid embodiment provided by the present invention.

[0028] Figure 7 This is an electrical test curve of the dual-gate embodiment provided by the present invention.

[0029] Reference numerals: 101: stepped substrate; 102: graphene gate; 103: low dielectric constant dielectric layer; 104: high dielectric constant dielectric layer; 105: two-dimensional thin film channel; 106: contact metal. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] Combine the following Figure 1 A vertical sub-1nm gate length field effect transistor of the present invention is described, comprising: Step substrate 101, graphene gate 102, low dielectric constant dielectric layer 103, high dielectric constant dielectric layer 104, two-dimensional thin film channel 105 and contact metal 106; The step substrate 101 has a step structure, and the step substrate 101 is used as a support layer of the graphene gate 102, so that the graphene in the graphene gate 02 is attached to the side wall of the step substrate 101; The low dielectric constant dielectric layer 103 acts as a backfill step and meshes with the step structure of the step substrate 101 to fill the step structure of the step substrate 101; The high dielectric constant dielectric layer 104 is disposed on top of the low dielectric constant dielectric layer 103 as a gate dielectric layer; The two-dimensional thin film channel 105 is disposed on the top of the high dielectric constant dielectric layer 104 , and the contact metal 106 is disposed on the two-dimensional thin film channel 105 to form an electrical connection with the two-dimensional thin film channel 105 .

[0032] In the present invention, the step substrate 101 serves as a gate support layer, has a smooth surface, includes step sidewalls and a horizontal portion, and is usually made of an insulating material, such as SiO2. The vertical graphene gate 102 serves as a gate, and its thickness is at a sub-1 nm level. The thickness of the graphene is used to define the gate, and a sub-1 nm gate length is achieved. The low-dielectric constant dielectric layer 103 serves as a backfill step, completely filling the step structure, and is usually the same dielectric as the step-shaped low-dielectric constant dielectric layer 103. The high-dielectric constant dielectric layer 104 serves as a gate dielectric layer, and usually uses a high-dielectric material, such as HfO2, ZrO2, and Al2O3. The two-dimensional thin film channel 105 is arranged horizontally, and uses a two-dimensional thin film or oxide semiconductor with semiconductor properties. The contact metal 106 is used to form an electrical connection with the two-dimensional thin film channel 105, and can be a metal or a conductive non-metal.

[0033] The graphene gate 102 is used as a gate electrode, and has a thickness of sub-1 nm. The vertical graphene is transferred to the sidewall of the step substrate 101 by wet transfer. The sidewalls of the step substrate 101 are patterned by photolithography so that the graphene has a specific structure.

[0034] Transfer of the graphene gate 102: The vertical graphene is transferred to the side wall of the step substrate 101 by wet transfer, and a special stress release process is used to ensure that the graphene is vertically attached to the step side wall without damage. Photolithography patterning: The vertical graphene gate 102 needs to be photolithographically patterned after transfer to complete the appropriate structural area.

[0035] In addition, a seed layer is generated on the graphene surface by angle deposition, and a seed layer, such as SiO2 and Al2O3, is generated on the surface of the vertical graphene gate 102 so as to continue to generate other materials.

[0036] After the low dielectric constant dielectric layer 103 backfills the step structure of the step substrate 101, the low dielectric constant dielectric layer 103 and the step structure are ground and polished below the junction by chemical mechanical polishing to obtain a smooth vertical graphene surface.

[0037] In the present invention, the cutting of graphene is completed by chemical mechanical polishing, and a smooth surface is obtained to facilitate the formation of the high dielectric constant dielectric layer 104.

[0038] See also Figure 2 The present invention also discloses a method for preparing a vertical sub-1nm gate length field effect transistor, comprising: refer to Figure 2 a, etching a step base using silicon deep etching equipment; refer to Figure 2 b, generating an initial silicon dioxide layer on the surface of the step structure by a thermal oxidation device; refer to Figure 2 c, using a buffered oxide etchant to remove the initial silicon dioxide layer and obtain a smooth silicon surface; refer to Figure 2 d, forming a smooth first silicon dioxide layer on the smooth silicon surface by an inductively coupled plasma enhanced chemical vapor deposition device, wherein the first silicon dioxide layer is a base silicon dioxide layer; refer to Figure 2 e, graphene is transferred to the sidewall of the stepped substrate with a silicon dioxide layer by wet transfer and patterned; refer to Figure 2 f and Figure 2 g, completing the deposition of graphene contact metal by photolithography, and generating a seed layer on the graphene surface by angle deposition, and generating a second silicon dioxide layer on the seed layer surface by inductively coupled plasma enhanced chemical vapor deposition equipment; refer to Figure 2 h, grinding the bottom of the junction between the first silicon dioxide layer and the second silicon dioxide layer by chemical mechanical polishing to obtain smooth vertical graphene and a flat wafer interface; refer to Figure 2 i and Figure 2 j, generating a high dielectric constant dielectric layer on the smooth vertical graphene surface, and constructing a two-dimensional thin film channel on top of the high dielectric constant dielectric layer; refer to Figure 2 k, depositing contact metal of two-dimensional material on the two-dimensional thin film channel to complete the preparation of the transistor.

[0039] Specifically, a step base is etched with a thickness of 500 nm using a silicon deep etching device.

[0040] Thermal oxidation equipment is used to generate a silicon dioxide layer of about 350nm on the step surface. Thermal oxidation equipment can make the underlying silicon surface smooth, so thermal oxidation technology is used to complete the surface smoothing.

[0041] In the process of removing the initial silicon dioxide layer by using a buffered oxidation etchant to obtain a smooth silicon surface, the initial silicon dioxide layer on the surface of the step structure is washed with a BOE solution, the initial silicon dioxide layer is oxidized and etched, and a smooth silicon surface is obtained after removing the initial silicon dioxide layer.

[0042] By using ICP-PECVD to generate a smooth silicon dioxide dielectric, an insulating silicon dioxide layer is generated on the step surface. In this embodiment, 400nm of SiO2 is generated at 130°C.

[0043] Among them, ICP-PECVD (Inductively Coupled Plasma - Plasma Enhanced ChemicalVapor Deposition) is a technology used to deposit high-quality thin films in semiconductor manufacturing and other microelectronic applications. This technology combines the advantages of plasma enhanced chemical vapor deposition (PECVD) and inductively coupled plasma (ICP), and can achieve high-quality and high-density thin film deposition at lower temperatures.

[0044] Compared with traditional thermal CVD, ICP-PECVD can deposit thin films at lower temperatures, which helps protect temperature-sensitive substrate materials and allows a wider range of material choices. By using a radio frequency (RF) power source to generate an inductively coupled plasma, ICP-PECVD can generate a high-density plasma, thereby improving reaction rates and film quality. ICP-PECVD can provide better film thickness uniformity and composition consistency, which is critical for the production of high-performance microelectronic devices. Due to the activation of the plasma, ICP-PECVD generally has a higher deposition rate than traditional PECVD. For substrates with complex topological structures, such as high aspect ratio features, ICP-PECVD can provide better step coverage capabilities, ensuring that all surfaces are evenly covered with thin films. The ICP-PECVD system can be adjusted according to different process requirements, such as changing parameters such as power, pressure, and gas mixture to adapt to different types of film deposition requirements.

[0045] The typical ICP-PECVD process flow includes: 1. Preparation Loading substrate: Place the substrate to be processed into the reaction chamber, ensuring that the substrate is well fixed and the surface is clean and free of contamination.

[0046] Evacuate: Close the reaction chamber and use a vacuum pump to reduce the pressure inside the chamber to the desired low vacuum state, usually mTorr or lower.

[0047] 2. Preprocessing (optional) Substrate preheating: If necessary, the substrate can be heated first to remove moisture or other impurities adsorbed on the surface. This helps to improve the quality and adhesion of the film.

[0048] Plasma Cleaning: Plasma generated from oxygen or other gases is sometimes used to clean the substrate surface to further improve film quality.

[0049] 3. Process parameter setting Set Temperature: Adjusting the substrate heater so that the substrate reaches the specified operating temperature is very important to ensure uniform film deposition.

[0050] Adjust gas flow: Introduce an appropriate amount of reaction gas (such as silane, ammonia, etc.) through a mass flow controller, and these gases will undergo chemical reactions under the action of plasma.

[0051] Set RF power: Apply appropriate RF power to the inductively coupled coil to generate sufficient plasma density. ICP source can provide higher plasma density than traditional PECVD, thus promoting more efficient reactions.

[0052] 4. Plasma generation and deposition Start plasma: Turn on the RF power to activate the inductively coupled plasma. At this time, the reaction gas is dissociated into active species, which react chemically on the substrate and form the desired film.

[0053] Monitoring process: Optical emission spectrometer (OES), mass spectrometer and other tools are used to monitor the state of plasma and film formation in real time to ensure the stability of the deposition process.

[0054] 5. Ending stage Turn off plasma: When the predetermined deposition time or film thickness is reached, turn off the RF power supply to terminate plasma generation.

[0055] Cool the substrate: Allow the substrate to cool naturally or use forced cooling measures to reduce its temperature to a safe level.

[0056] Restore atmospheric pressure: Slowly fill the reaction chamber with inert gas (such as nitrogen) until it returns to atmospheric pressure.

[0057] Unloading substrate: Open the reaction chamber and take out the substrate on which the thin film has been deposited.

[0058] 6. Inspection and analysis Check film properties: Use various characterization techniques (such as scanning electron microscopy (SEM), X-ray diffraction (XRD), ellipsometry, etc.) to evaluate the thickness, composition, structure, and other physical properties of the film to ensure that it meets the expected standards.

[0059] The graphene is transferred to the sidewall of the step substrate having the silicon dioxide layer by wet transfer and patterned, including: Transferring graphene to the step sidewall with the silicon dioxide layer by wet transfer; The graphene is vertically attached to the side wall of the step through a set stress release method; Photolithography patterning is performed on the graphene on the sidewall of the step so that the graphene has a specific structure.

[0060] The method of transferring graphene to the step sidewall having a silicon dioxide layer by wet transfer comprises: Coating a polymer support layer on the surface of graphene; Continue coating a photoresist layer on the surface of the graphene with the polymer support layer; The photoresist layer is patterned to form a stress transfer area without photoresist and a stress protection area with photoresist, so as to construct a composite sacrificial coating; transferring the graphene with the composite sacrificial coating onto a target substrate; The target substrate is a step sidewall having a silicon dioxide layer.

[0061] The pattern of the photoresist layer is adjusted, and the stress release degree of the photoresist layer in different thickness areas is different through photolithography, so as to achieve stress release of graphene; During the graphene stress release process, natural fracture occurs in the area of ​​the photoresist layer without photoresist protection, allowing the graphene to be completely transferred on the step sidewall with the silicon dioxide layer.

[0062] In the present invention, the deposition of graphene contact metal is completed by photolithography, which can usually be metal and other conductive non-metals, highly doped p-type and n-type silicon, germanium semiconductor, flexible electrode material, etc. For this embodiment, it is 5nm / 30nm metal Ti / Pd. The silicon oxide seed layer is deposited by angle, and then the 1.5um SiO2 layer is completed by ICP-PECVD. After that, an annealing process is performed at 250°C for more than 1 hour.

[0063] The high dielectric constant dielectric layer is usually HfO2, ZrO2, Al2O3, and in this embodiment, 15nm of HfO2 is used to carve holes for the gate.

[0064] Depositing a contact metal of a two-dimensional material on a two-dimensional thin film channel to complete the preparation of the transistor includes: Metal titanium, palladium, chromium, gold or bismuth is deposited on the two-dimensional thin film channel to construct contact metal and complete the transistor preparation.

[0065] Specifically, the contact metal for depositing the two-dimensional material can generally be metal and other conductive non-metal, highly doped p-type and n-type silicon, germanium semiconductor, flexible electrode material, etc. For this embodiment, it is 5nm / 30nm metal Ti / Pd.

[0066] In another embodiment, reference Figure 3 When preparing the step substrate, the steps are etched into a denser structure, so that a dual-gate transistor can be realized, and the other steps are the same as the previous embodiment.

[0067] In yet another embodiment, reference Figure 4 When transferring graphene, the multi-gate structure is completed by transferring graphene multiple times and separating them with dielectric layers (see Figure 4 l- Figure 4 n), and the other steps are the same as those in the previous embodiment.

[0068] After experiment, reference Figure 5 Light microscope photos of several different embodiments are shown. Figure 5 a and 5b show the optical microscope images of the graphene gate on the left and right walls, respectively. Figure 5 c shows a light microscope image of a dual-gate transistor. All embodiments have distinct features.

[0069] In order to verify the effect of the embodiment of the present invention, the prepared device was tested. Figure 6 , is the transfer characteristic curve of the vertical sub-1nm single-gate transistor prepared in the example of the present invention (I ds -V g ) figure, which shows the ds = Transfer characteristic curves at voltages of 0.01, 0.1, and 1 V, with the gate voltage scanned from -6 V to 6 V. The device shown in the embodiment has typical saturation characteristics and has obvious curve characteristics of a sub-1 nm transistor.

[0070] also, Figure 7 The transfer characteristics of a vertical sub-1nm dual-gate transistor (I ds -V g )picture. Figure 7 The left figure shows the device state diagram when the second gate is floating. Figure 7 The right figure shows the transfer characteristic curve of the device when the second gate is given different voltages. It can be seen that the device has obvious characteristics modulated by the double gate.

[0071] The core of the present invention is to use a single layer or a few layers of vertical graphene with a thickness of sub-1nm as the gate. Unlike traditional transistors, the present invention uses vertically structured graphene as the gate, and adopts a special step wet transfer process, a low dielectric constant backfill process, and a chemical mechanical polishing process to complete the entire gate preparation. In addition, silicon oxide serves as a low dielectric constant insulating layer to reduce the gate leakage and gate source capacitance; the two-dimensional film is used as a conductive channel to cover the high dielectric constant insulating layer, thereby completing the entire single-gate or double-gate vertical sub-1nm gate length and planar two-dimensional film field effect transistor.

[0072] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0073] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A vertical sub-1nm gate length field effect transistor, characterized in that: include: Step substrate, graphene gate, low dielectric constant dielectric layer, high dielectric constant dielectric layer, two-dimensional thin film channel and contact metal; The step substrate has a step structure, and the step substrate is used as a support layer of the graphene grid, so that the graphene in the graphene grid is attached to the side wall of the step substrate; The low dielectric constant dielectric layer acts as a backfill step and meshes with the step structure of the step base to fill the step structure of the step base; The high dielectric constant dielectric layer is arranged on top of the low dielectric constant dielectric layer as a gate dielectric layer; The two-dimensional thin film channel is arranged on the top of the high dielectric constant dielectric layer, and the contact metal is arranged on the two-dimensional thin film channel to form an electrical connection with the two-dimensional thin film channel.

2. The vertical sub-1 nm gate length field effect transistor according to claim 1, characterized in that: The step base includes a side wall and a horizontal portion, and both the side wall and the horizontal portion are provided with an insulating material.

3. The vertical sub-1 nm gate length field effect transistor according to claim 1, characterized in that: The graphene gate is used as a gate electrode, and has a thickness of sub-1 nm. The vertical graphene is transferred to the sidewall of the step substrate by wet transfer; The sidewall of the step substrate is patterned by photolithography so that the graphene has a target structure.

4. The vertical sub-1 nm gate length field effect transistor according to claim 1, characterized in that: After the low dielectric constant dielectric layer backfills the step structure of the step substrate, the low dielectric constant dielectric layer and the step structure are ground and polished below the junction by chemical mechanical polishing to obtain a vertical graphene surface.

5. A method for preparing a vertical sub-1 nm gate length field effect transistor, used to prepare a vertical sub-1 nm gate length field effect transistor as claimed in any one of claims 1 to 4, characterized in that: include: Etching a step base by using a silicon deep etching device; Generating an initial silicon dioxide layer on the surface of the step structure by a thermal oxidation device; A buffered oxide etchant is used to remove the initial silicon dioxide layer to obtain a smooth silicon surface; Generating a first silicon dioxide layer on the silicon surface by using an inductively coupled plasma enhanced chemical vapor deposition device, wherein the first silicon dioxide layer is a base silicon dioxide layer; Transferring graphene onto the sidewall of a stepped substrate having a silicon dioxide layer by wet transfer and patterning the graphene; The graphene contact metal is deposited by photolithography, and a seed layer is generated on the graphene surface by angle deposition, and a second silicon dioxide layer is generated on the seed layer surface by inductively coupled plasma enhanced chemical vapor deposition equipment; Grinding below the junction of the first silicon dioxide layer and the second silicon dioxide layer by chemical mechanical polishing to obtain vertical graphene and a flat wafer interface; A high dielectric constant dielectric layer is generated on the wafer surface above the vertical graphene, and a two-dimensional thin film channel is constructed on the top of the high dielectric constant dielectric layer; A contact metal of two-dimensional material is deposited on the two-dimensional thin film channel to complete the preparation of the transistor.

6. The method for preparing a vertical sub-1 nm gate length field effect transistor according to claim 5, characterized in that: The method of removing the initial silicon dioxide layer by using a buffered oxide etchant to obtain a smooth silicon surface comprises: The initial silicon dioxide layer on the surface of the step structure is washed with a BOE solution, the initial silicon dioxide layer is oxidized and etched, and the silicon surface is obtained after the initial silicon dioxide layer is removed.

7. The method for preparing a vertical sub-1 nm gate length field effect transistor according to claim 5, characterized in that: The method of transferring graphene to the sidewall of a step substrate having a silicon dioxide layer by wet transfer and patterning the graphene comprises: Transferring graphene to the step sidewall with the silicon dioxide layer by wet transfer; The graphene is vertically attached to the side wall of the step through a set stress release method; Photolithography patterning is performed on the graphene on the sidewall of the step so that the graphene has a specific structure.

8. The method for preparing a vertical sub-1 nm gate length field effect transistor according to claim 7, characterized in that: The step of transferring the graphene to the step sidewall having the silicon dioxide layer by wet transfer comprises: Coating a polymer support layer on the surface of graphene; Continue coating a photoresist layer on the surface of the graphene with the polymer support layer; The photoresist layer is patterned to form a stress transfer area without photoresist and a stress protection area with photoresist, so as to construct a composite sacrificial coating; transferring the graphene with the composite sacrificial coating onto a target substrate; The target substrate is a step sidewall having a silicon dioxide layer.

9. The method for preparing a vertical sub-1 nm gate length field effect transistor according to claim 8, characterized in that: The step of transferring the graphene with the composite sacrificial coating to a target substrate comprises: The pattern of the photoresist layer is adjusted, and the stress release degree of the photoresist layer in different thickness areas is different through photolithography, so as to achieve stress release of graphene; During the graphene stress release process, natural fracture occurs in the area of ​​the photoresist layer without photoresist protection, allowing the graphene to be completely transferred on the step sidewall with the silicon dioxide layer.

10. The method for preparing a vertical sub-1 nm gate length field effect transistor according to claim 5, characterized in that: The step of depositing a contact metal of a two-dimensional material on a two-dimensional thin film channel to complete the preparation of a transistor includes: Metal titanium, palladium, chromium, gold or bismuth is deposited on the two-dimensional thin film channel to construct contact metal and complete the transistor preparation.

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