Double-buried-gate power MOSFET structure based on charge plasma

Abstract

The invention relates to a power MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), in particular to a charge plasma-based double-buried gate power MOSFET structure which sequentially comprises a p-type body region and an n-type drift region from top to bottom, polycrystalline silicon layers are arranged at the left end and the right end of the n-type drift region respectively, the upper surface, the lower surface and the inner surface of each polycrystalline silicon layer are wrapped by oxide layers, and n + charge plasma regions are formed at the left end and the right end of the p-type body region. A p + charge plasma region is formed at the top of the p-type body region; metalizing the substrate to form a drain electrode; metalizing the polysilicon gate layer on the outer side to form a gate; metalizing the outer side of the n + charge plasma region to form a first source electrode, and metalizing the p + charge plasma region to form a second source electrode; compared with an existing VDMOS structure, the VDMOS structure has the advantages of being smaller in thermal budget, lower in manufacturing complexity, lower in on resistance and charge, larger in power density and better in high-frequency performance index.

Description

Technical Field

[0001] The invention relates to a power MOSFET, and in particular to a double buried gate power MOSFET structure based on charge plasma. Background Art

[0002] In order to achieve the ideal switching state, power MOSFET devices need to have lower resistance in the on state and higher breakdown voltage in the off state. In order to achieve better high-frequency characteristics, the device should have lower parasitic capacitance Cgs and lower on-resistance to reduce conduction loss. Trench gate power MOSFET is the most widely used power MOSFET structure. This structure digs grooves in the drift region to form a vertical gate structure. This structure removes the parasitic JFET present in the DMOS structure; secondly, the deep trench in the drift region reduces the drift region resistance of the device. Compared with the lateral structure, the trench MOSFET structure adopts a low effective area design, so it has low on-resistance and high power density. However, trench gate MOSFET has three limitations. One is the high gate-drain coupling caused by the reduced distance between the gate and the drain. This increases the parasitic gate-drain capacitance, thereby reducing the switching performance of the device; secondly, the n+source-p body and the n drift region form a parasitic BJT, which interferes with the normal behavior of the transistor in the OFF state; it has a high breakdown voltage while having a low on-resistance. Improving all three parameters of power devices to enhance benefits remains a challenge for device designers. Summary of the invention

[0003] In order to reduce the complexity and cost of device manufacturing, reduce the risk of random doping and high mutation junction formation, and improve the parasitic triode effect, the present invention proposes a double buried gate power MOSFET structure based on charge plasma, including:

[0004] Growing an epitaxial layer on an n+ type substrate to form an n- type drift region;

[0005] An oxide layer is grown and polysilicon is deposited on the surface of the n-type drift region in sequence to form an oxide layer and a polysilicon gate layer;

[0006] Etching the oxide layer and the polysilicon gate layer, retaining the oxide layer and the polysilicon gate layer at the left and right ends and removing the oxide layer and the polysilicon gate layer at the middle position after etching;

[0007] Depositing a gate oxide layer on the etched surface and etching the redundant oxide layer in the middle and on the n-type drift region, so that the upper surface and the inner side of the polysilicon gate layer are wrapped with silicon dioxide;

[0008] Continue to grow an epitaxial layer on the n-type drift region and the upper surface of the oxide layer, and perform p-type doping on the epitaxial layer above the oxide layer to form a p-type body region;

[0009] n+ charged plasma regions are formed at the left and right ends of the p-type body region, and p+ charged plasma region is formed on the top of the p-type body region;

[0010] The substrate is metalized to form a drain; the outer polysilicon gate layer is metalized to form a gate; the outer side of the n+ charge plasma region is metalized to form a first source, and the p+ charge plasma region is metalized to form a second source.

[0011] Compared with the existing VDMOS structure, the structure of the present invention has a smaller thermal budget, lower manufacturing complexity, lower on-resistance and charge, higher power density, and better high-frequency performance indicators. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a schematic diagram of the structure of a double buried gate power MOSFET device of the charge plasma of the present invention;

[0013] Figure 2 The present invention is a flow chart for manufacturing a double buried gate power MOSFET device of a charge plasma. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] The present invention proposes a double buried gate power MOSFET structure based on charge plasma, comprising:

[0016] Growing an epitaxial layer on an n+ type substrate to form an n- type drift region;

[0017] An oxide layer is grown and polysilicon is deposited on the surface of the n-type drift region in sequence to form an oxide layer and a polysilicon gate layer;

[0018] Etching the oxide layer and the polysilicon gate layer, retaining the oxide layer and the polysilicon gate layer at the left and right ends and removing the oxide layer and the polysilicon gate layer at the middle position after etching;

[0019] Depositing a gate oxide layer on the etched surface and etching the redundant oxide layer in the middle and on the n-type drift region, so that the upper surface and the inner side of the polysilicon gate layer are wrapped with silicon dioxide;

[0020] Continue to grow an epitaxial layer on the n-type drift region and the upper surface of the oxide layer, and perform p-type doping on the epitaxial layer above the oxide layer to form a p-type body region;

[0021] n+ charged plasma regions are formed at the left and right ends of the p-type body region, and p+ charged plasma region is formed on the top of the p-type body region;

[0022] The substrate is metalized to form a drain; the outer polysilicon gate layer is metalized to form a gate; the outer side of the n+ charge plasma region is metalized to form a first source, and the p+ charge plasma region is metalized to form a second source.

[0023] This embodiment proposes a double buried gate power MOSFET structure of charge plasma. First, a metal electrode is used on a silicon film to utilize the work function difference of a metal semiconductor to generate an induced charge plasma to realize an n+ source region and a p+ body region, thereby reducing the risk of high mutation junctions and random doping during the manufacturing process, reducing the high temperature process required for doping, and reducing the thermal budget; second, due to the presence of Gaussian hole plasma in the p-type body region, the body region doping concentration can be higher, the device on-resistance is smaller, and the Baliga figure of merit (FOM1=BV / Rsp) of the device is increased by 10%; third, the coupling between the gate and the drain is reduced, and the gate-drain coupling capacitance is reduced, and the Baliga high-frequency figure of merit FOM2=Rsp.Qsp is better. At the same time, due to the absence of doping in the n+ source region and the p+ body region, the triode effect can be effectively suppressed.

[0024] like Figure 1 The present invention proposes a double buried gate power MOSFET structure based on charge plasma, which comprises an n-type drift region and a p-type body region from bottom to top, and a polysilicon layer is formed at the left and right ends of the upper part of the n-type drift region. After the polysilicon layer is formed, the n-type drift region is in a convex shape, and the surfaces of the polysilicon in contact with the n-type drift region and the p-type body region are isolated by an oxide layer, and n+ charge plasma regions are formed at the left and right ends of the p-type body region, and a p+ charge plasma region is formed on the top of the p-type body region. The substrate is metalized to form a drain; the outer polysilicon gate layer is metalized to form a gate; the outer side of the n+ charge plasma region is metalized to form a first source, and the p+ charge plasma region is metalized to form a second source.

[0025] As an optional embodiment, the n-type drift region is doped with phosphorus ions with a doping concentration of 6.8×10 15 / cm 3 ~7.1×10 15 / cm 3

[0026] As an optional implementation, the p-type body region is doped with boron ions at a doping concentration of 1.0×10 16 / cm3 ~1.3×10 16 / cm 3 .

[0027] This embodiment also provides specific dimensions of a dual buried gate power MOSFET structure based on charge plasma. The overall dimensions of a dual buried gate power MOSFET structure based on charge plasma are 3um×7um, the thickness of the polysilicon layer is about 0.1um, the width is about 0.7~0.75um, and the wrapped polysilicon layer is about 50nm; the thickness of the p-type body region is about 0.5um.

[0028] In this embodiment, the oxide layer material is silicon dioxide, the first source electrode is metallized with TiW material, and the second source electrode is metallized with Pt material.

[0029] This embodiment also provides Figure 2 The preparation process of a double buried gate power MOSFET structure based on charge plasma shown in the figure specifically includes the following steps:

[0030] (1) performing epitaxial layer growth, that is, performing epitaxial layer growth on an n+ type substrate, which forms an n- type drift region after subsequent doping;

[0031] (2) growing an oxide layer on the surface of the epitaxial layer;

[0032] (3) depositing polysilicon on the oxide layer;

[0033] (4) Selecting to remove the polysilicon and oxide layer etching, that is, retaining the oxide layer and polysilicon gate layer at the left and right ends, and removing the oxide layer and polysilicon gate layer at the middle position;

[0034] (5) depositing a gate oxide layer, that is, depositing an oxide layer on the surface of the polysilicon gate layer and the epitaxial layer;

[0035] (6) selectively etching the oxide layer, that is, etching the excess oxide layer in the middle position and on the n-type drift region, so that the upper surface and the inner side of the polysilicon gate layer are wrapped with silicon dioxide;

[0036] (7) continuing to grow the silicon epitaxial layer;

[0037] (8) doping the epitaxial layer above the polysilicon layer to form a p-type body region, and doping the region below the upper surface of the polysilicon layer to form an n-type drift region;

[0038] (9) Metallizing the substrate to form a drain; metallizing the outer polysilicon gate layer to form a gate; metallizing the outer side of the n+ charge plasma region to form a first source, and metallizing the p+ charge plasma region to form a second source.

[0039] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A dual buried gate power MOSFET structure based on charge plasma, characterized in that: The following steps are involved: Growing an epitaxial layer on an n+ type substrate to form an n- type drift region; An oxide layer is grown and polysilicon is deposited on the surface of the n-type drift region in sequence to form an oxide layer and a polysilicon gate layer; Etching the oxide layer and the polysilicon gate layer, retaining the oxide layer and the polysilicon gate layer at the left and right ends and removing the oxide layer and the polysilicon gate layer at the middle position after etching; Depositing a gate oxide layer on the etched surface and etching the redundant oxide layer in the middle and on the n-type drift region, so that the upper surface and the inner side of the polysilicon gate layer are wrapped with silicon dioxide; Continue to grow an epitaxial layer on the n-type drift region and the upper surface of the oxide layer, and perform p-type doping on the epitaxial layer above the oxide layer to form a p-type body region; n+ charged plasma regions are formed at the left and right ends of the p-type body region, and p+ charged plasma region is formed on the top of the p-type body region; The substrate is metalized to form a drain; the outer polysilicon gate layer is metalized to form a gate; the outer side of the n+ charge plasma region is metalized to form a first source, and the p+ charge plasma region is metalized to form a second source.

2. A dual buried gate power MOSFET structure based on charge plasma according to claim 1, characterized in that: The n-type drift region is doped with phosphorus ions with a doping concentration of 6.8×10 15 / cm 3 ~7.1×10 15 / cm 3 .

3. The dual buried gate power MOSFET structure based on charge plasma according to claim 1, characterized in that: The thickness of the polysilicon gate layer is 0.1um.

4. The dual buried gate power MOSFET structure based on charge plasma according to claim 1, characterized in that: The width of the oxide layer covering each polysilicon layer is 0.75-0.8 um, and the thickness of the oxide layer between the polysilicon layer and the p-type body region or between the polysilicon layer and the n-type drift region is 50 nm.

5. The dual buried gate power MOSFET structure based on charge plasma according to claim 1, characterized in that: The oxide layer material is silicon dioxide.

6. The dual buried gate power MOSFET structure based on charge plasma according to claim 1, characterized in that: The p-type body region is doped with boron ions, with a doping concentration of 1.0×10 16 / cm 3 ~1.3×10 16 / cm 3 .

7. The dual buried gate power MOSFET structure based on charge plasma according to claim 1, characterized in that: The thickness of the p-type body region is 0.5um.

8. The dual buried gate power MOSFET structure based on charge plasma according to claim 1, characterized in that: The first source electrode is metallized with TiW material, and the second source electrode is metallized with Pt material.

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