Display panel and manufacturing method thereof

Abstract

The invention relates to a display panel and a manufacturing method thereof. A display panel of the present invention may include a base layer, a pixel defining film disposed on the base layer and defining a light emitting opening, a partition wall defining a partition wall opening overlapping the light emitting opening, and a light emitting layer disposed on the pixel defining film. The light emitting device includes a pixel defining film disposed on a substrate and including a first partition wall layer disposed on the pixel defining film and a second partition wall layer disposed on the first partition wall layer, and a light emitting element disposed in a partition wall opening portion and including an anode, an intermediate layer, and a cathode in contact with the partition wall; the first partition wall layer includes an amorphous (amorphous) alloy.

Description

Technical Field

[0001] The present invention relates to a display panel and a method for manufacturing the display panel, and more particularly to a display panel with improved display quality. Background Art

[0002] Display devices such as televisions, monitors, smartphones, and tablet PCs that provide images to users include display panels that display images. Various display panels have been developed, including liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels.

[0003] An organic light emitting display panel may include an anode, a cathode, and a light emitting pattern. The light emitting pattern is separated on each light emitting region, and the cathode may provide a common voltage to each light emitting region. Summary of the invention

[0004] An object of the present invention is to provide a display panel and a method for manufacturing the same, which can form a light-emitting element without using a metal mask to improve display quality.

[0005] According to an embodiment of the present invention, a display panel may include: a base layer, a pixel definition film, which is arranged on the base layer and defines a light-emitting opening portion, a partition wall, which defines a partition wall opening portion overlapping the light-emitting opening portion and includes a first partition wall layer arranged on the pixel definition film and a second partition wall layer arranged on the first partition wall layer, and a light-emitting element, which is arranged in the partition wall opening portion and includes an anode, an intermediate layer and a cathode in contact with the partition wall; the first partition wall layer contains an amorphous alloy.

[0006] The first partition wall layer may define a first region of the partition wall opening, the second partition wall layer may define a second region of the partition wall opening, and a width of the first region in a first direction may be greater than a width of the second region in the first direction.

[0007] The first partition wall layer may include a first sub-layer disposed on the pixel definition film and a second sub-layer disposed on the first sub-layer, wherein the second sub-layer includes an amorphous alloy.

[0008] An inner side surface of the first sub-layer and an inner side surface of the second sub-layer may be aligned.

[0009] The cathode may extend along the inner side surface of the first sub-layer and the inner side surface of the second sub-layer, and an end of the cathode may contact the second sub-layer.

[0010] The thickness of the first sub-layer can be (Angstroms) or more and (Angstroms) or less.

[0011] The thickness of the second sub-layer can be (Angstroms) or more and (Angstroms) or less.

[0012] The thickness of the second partition wall layer can be (Angstroms) or more and (Angstroms) or less.

[0013] The amorphous alloy may include at least one of an amorphous molybdenum alloy and an amorphous tungsten alloy.

[0014] The display panel may further include a lower encapsulation inorganic pattern covering the light emitting element, and a dummy region may be defined between the partition wall and the lower encapsulation inorganic pattern.

[0015] The display panel may further include an encapsulation organic film disposed on the lower encapsulation inorganic pattern, and a portion of the encapsulation organic film may fill the dummy region.

[0016] According to an embodiment of the present invention, a method for manufacturing a display panel may include: a step of providing a preliminary display panel, the preliminary display panel including a base layer and a pixel definition film arranged on the base layer, a step of forming a first preliminary partition wall layer containing an amorphous alloy on the preliminary display panel, a step of forming a second preliminary partition wall layer on the first preliminary partition wall layer, a step of etching the second preliminary partition wall layer to form a second partition wall layer defining a first opening portion, and a step of etching the first preliminary partition wall layer to form a first partition wall layer defining a second opening portion; the width of the first opening portion in the first direction is smaller than the width of the second opening portion in the first direction.

[0017] The step of forming the first preliminary partition wall layer may include: forming a first preliminary sub-layer on the pixel definition film; and forming a second preliminary sub-layer on the first preliminary sub-layer.

[0018] The step of forming the first preliminary sub-layer may include: (Angstrom) to The deposition step is performed with a thickness of (angstroms).

[0019] The step of forming the second preliminary sub-layer may include: (Angstrom) to The deposition step is performed with a thickness of (angstroms).

[0020] The second preliminary sub-layer may include at least one of an amorphous molybdenum alloy and an amorphous tungsten alloy.

[0021] The step of etching the first preliminary partition wall layer to form the first partition wall layer defining the second opening may include etching the second preliminary sub-layer to form a second sub-layer; and etching the first preliminary sub-layer to form a first sub-layer.

[0022] An inner side surface of the first sub-layer and an inner side surface of the second sub-layer may be aligned.

[0023] The step of forming the second preliminary partition wall layer may include: (Angstrom) to The deposition step is performed with a thickness of (angstroms).

[0024] The method for manufacturing the display panel may further include: forming a light emitting element in the second opening; and forming a lower encapsulation inorganic pattern covering the light emitting element.

[0025] (Effects of the Invention)

[0026] According to the content as described above, the second sublayer of the first partition wall layer of the present invention may include at least one of an amorphous molybdenum alloy and an amorphous tungsten alloy. The second sublayer may not have a columnar crystal structure. The bonding force between the second sublayer and the cathode may be improved, and the moisture permeability reliability may be improved. Therefore, the pixel defects (dark spots, pixel shrinkage, etc.) of the display panel caused by impurities may be reduced or removed.

[0027] Furthermore, the first partition wall layer may include a first sublayer and a second sublayer including molybdenum or tungsten. Since the first partition wall layer includes molybdenum or tungsten, the phenomenon of increased resistance caused by the formation of an oxide film by the first partition wall layer can be reduced or eliminated. That is, the partition wall of the present invention does not form an interface oxide film, so the resistance is low, and the electrical reliability of the display panel can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1A It is a perspective view of a display device according to an embodiment of the present invention.

[0029] Figure 1B It is an exploded perspective view of a display device according to an embodiment of the present invention.

[0030] Figure 2 is a cross-sectional view of a display module according to an embodiment of the present invention.

[0031] Figure 3 FIG. 1 is a top view of a display panel according to an embodiment of the present invention.

[0032] Figure 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0033] Figure 5 FIG. 1 is an enlarged plan view of a portion of a display area of ​​a display panel according to an embodiment of the present invention.

[0034] Figure 6 It is along Figure 3 A cross-sectional view of a display panel according to an embodiment of the present invention taken along line II'.

[0035] Figure 7 It is along Figure 5 A cross-sectional view taken along line II-II'.

[0036] Fig. 8A is a cross-sectional view of the second sub-layer of the comparative example.

[0037] Figure 8B FIG. 4 is a cross-sectional view of a second sub-layer according to an embodiment of the present invention.

[0038] FIG. 9A to FIG. 9K It is a cross-sectional view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention.

[0039] Description of Reference Numerals

[0040] DP: display panel; BL: base layer; PDL: pixel definition film; PW: partition wall; L1: first partition wall layer; L2: second partition wall layer; LS1: first sublayer; LS2: second sublayer; LIL: lower encapsulation inorganic pattern DETAILED DESCRIPTION

[0041] In this specification, when it is mentioned that a certain component (or region, layer, part, etc.) is "on" another component, "connected" or "combined with" another component, it means that the certain component can be directly configured / connected / combined on the other component, or a third-party component can be configured between them.

[0042] The same reference numerals represent the same components. In addition, in the drawings, the thickness, ratio and size of the components are exaggerated for effective description of the technical content. "And / or" includes all of the combinations of more than one defined for the components related to each other.

[0043] The terms first, second, etc. can be used to describe a variety of constituent elements, but the constituent elements are not limited to the terms. The terms are used only for the purpose of distinguishing one constituent element from other constituent elements. For example, without departing from the scope of the present invention, the first constituent element can be referred to as the second constituent element, and similarly, the second constituent element can also be referred to as the first constituent element. Unless the context clearly indicates a different meaning, a singular expression includes a plural expression.

[0044] Furthermore, terms such as “lower”, “lower side”, “upper”, and “upper side” are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0045] The terms "including" or "having" should be understood as intending to specify the existence of the features, numbers, steps, actions, constituent elements, parts or their combinations recorded in the specification, but are not intended to preclude the existence or additional possibilities of one or more other features, numbers, steps, actions, constituent elements, parts or their combinations.

[0046] Unless defined differently, all terms (including technical terms and scientific terms) used in this specification have the same meanings as those generally understood by those skilled in the art to which the present invention belongs. In addition, terms that are the same as those defined in generally used dictionaries should be interpreted as having the same meanings as those in the context of the relevant technology, and should not be interpreted as overly ideal or formal meanings unless clearly defined.

[0047] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0048] Figure 1A is a three-dimensional diagram of a display device DD according to an embodiment of the present invention, Figure 1B It is an exploded perspective view of a display device DD according to an embodiment of the present invention.

[0049] In one embodiment, the display device DD may be a large electronic device, such as a television, a monitor, or an external billboard. Also, the display device DD may be a small or medium-sized electronic device, such as a personal computer, a notebook computer, a personal digital terminal, a car navigation unit, a game console, a smart phone, a tablet PC, and a camera. However, this is only exemplary and may also be applied to other display devices without departing from the concept of the present invention. Figure 1A and Figure 1B The display device DD is exemplarily shown as a smart phone.

[0050] Reference Figure 1A and Figure 1B The display device DD can display an image IM toward the third direction DR3 on a display surface FS that is parallel to each of the first direction DR1 and the second direction DR2. The image IM may include not only dynamic images but also static images. Figure 1A , a clock window and an icon are shown as an example of the image IM. The display surface FS displaying the image IM may correspond to the front surface of the display device DD.

[0051] In this embodiment, the front (or upper surface) and the back (or lower surface) of each component are defined based on the direction of displaying the image IM. The front and back surfaces may face each other in the third direction DR3, and the normal directions of the front and back surfaces are parallel to the third direction DR3. In addition, the directions indicated by the first to third directions DR1, DR2, and DR3 are relative concepts and may be transformed into other directions. In this specification, "on a plane" may refer to the situation when observed from the third direction DR3.

[0052] The display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be combined with each other to form the appearance of the display device DD.

[0053] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front side of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. For example, the transmission area TA may be an area having a visible light transmittance of about 90% or more.

[0054] The frame area BZA may be an area with a relatively low transmittance compared to the transmission area TA. The frame area BZA may define the shape of the transmission area TA. The frame area BZA may be adjacent to the transmission area TA and surround the transmission area TA. However, this is only an illustrative diagram, and the frame area BZA of the window WP may be omitted. The window WP may include at least one functional layer of an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, which is not limited to a certain embodiment.

[0055] The display module DM may be disposed below the window WP. The display module DM may be a structure that substantially generates an image IM. The image IM generated in the display module DM is displayed on the display surface IS of the display module DM and is visible to the user from the outside through the transmission area TA.

[0056] The display module DM may include a display area DA and a non-display area NDA. The display area DA may be an area activated based on an electrical signal. The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA is an area covered by the frame area BZA and therefore is not visually recognized from the outside.

[0057] The housing HAU may be combined with the window WP. The housing HAU may be combined with the window WP to provide a prescribed internal space. The display module DM may be accommodated in the internal space.

[0058] The housing HAU may include a relatively high rigidity material. For example, the housing HAU may include glass, plastic, or metal, or include a plurality of frames and / or plates formed by a combination thereof. The housing HAU may stably protect the components of the display device DD accommodated in the internal space from external impacts.

[0059] Figure 2 FIG. 4 is a cross-sectional view of a display module DM according to an embodiment of the present invention.

[0060] Reference Figure 2 The display module DM may include a display panel DP and an input sensor INS. Although not shown in the figure, the display device DD (see Figure 1A ) may further include a protection member disposed on the lower surface of the display panel DP or an anti-reflection member and / or a window member disposed on the upper surface of the input sensor INS.

[0061] The display panel DP may be a light-emitting display panel. However, this is merely illustrative and is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting substance. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0062] The display panel DP may include: a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The input sensor INS may be directly disposed on the thin film encapsulation layer TFE. In this specification, if it is described as "structure A is directly disposed on structure B", it means that no adhesive layer is disposed between the A structure and the B structure.

[0063] The base layer BL may include at least one plastic film. The base layer BL is a flexible substrate, which may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate. Figure 1BThe display area DA and the non-display area NDA described in the figure.

[0064] The circuit element layer DP-CL may include at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines, pixel driving circuits, and the like.

[0065] The display element layer DP-OLED may include partition walls and a light emitting element. The light emitting element may include an anode, an intermediate layer and a cathode.

[0066] The thin film encapsulation layer TFE may include a plurality of thin films, some of which may be configured to improve optical efficiency, and some of which may be configured to protect the organic light emitting diode.

[0067] The input sensor INS obtains coordinate information of the external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a single-layer or multi-layer conductive layer. Furthermore, the input sensor INS may include a single-layer or multi-layer insulating layer. The input sensor INS may sense the external input using a capacitive method. However, this is merely illustrative and is not limited thereto. For example, in one embodiment, the input sensor INS may also sense the external input using an electromagnetic induction method or a pressure sensing method. In addition, in another embodiment of the present invention, the input sensor INS may be omitted.

[0068] Figure 3 FIG. 4 is a top view of a display panel DP according to an embodiment of the present invention.

[0069] Reference Figure 3 In the display panel DP, a display area DA and a non-display area NDA around the display area DA may be defined. The display area DA and the non-display area NDA may be divided according to whether pixels PX are configured. The display area DA may be configured with pixels PX, and the non-display area NDA may not be configured with pixels PX.

[0070] The display panel DP may include pixels PX, initialization scan lines GIL1-GILm, compensation scan lines GCL1-GCLm, write scan lines GWL1-GWLm, black scan lines GBL1-GBLm, light emission control lines ECL1-ECLm, data lines DL1-DLn, first and second control lines CSL1, CSL2, driving voltage lines PL, a scanning driving unit SDV, a data driving unit, a light emission driving unit EDV, a driving chip DIC, and pads PD. Wherein, m and n are natural numbers greater than 2. The data driving unit may be a partial circuit formed in the driving chip DIC.

[0071] The pixels PX may be connected to initialization scan lines GIL1 -GILm, compensation scan lines GCL1 -GCLm, write scan lines GWL1 -GWLm, black scan lines GBL1 -GBLm, emission control lines ECL1 -ECLm, and data lines DL1 -DLn.

[0072] The initialization scan lines GIL1-GILm, the compensation scan lines GCL1-GCLm, the write scan lines GWL1-GWLm, and the black scan lines GBL1-GBLm may extend in the first direction DR1 and be electrically connected to the scan driving part SDV. The data lines DL1-DLn may extend in the second direction DR2 and be electrically connected to the driving chip DIC. The emission control lines ECL1-ECLm may extend in the first direction DR1 and be electrically connected to the emission driving part EDV.

[0073] The driving voltage line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be disposed on different layers from each other. The driving voltage line PL may provide a driving voltage to the pixel PX.

[0074] The first control line CSL1 may be connected to the scan driving part SDV, and the second control line CSL2 may be connected to the light emitting driving part EDV.

[0075] The driving chip DIC, the driving voltage line PL, the first control line CSL1, and the second control line CSL2 may be electrically connected to the pad PD. The flexible circuit film FCB may be electrically connected to the pad PD through an anisotropic conductive adhesive layer. The pad PD may be a pad for connecting the flexible circuit film FCB to the display panel DP. The pad PD may be connected to the corresponding pixel PX through the driving voltage line PL, the first control line CSL1, and the second control line CSL2.

[0076] Furthermore, the pad PD may further include an input pad. The input pad may be used to connect the flexible circuit film FCB with the input sensor INS (refer to Figure 2 ) is connected to the pad. However, it is not limited thereto, and the input pad may be configured in the input sensor INS and connected to a circuit board configured separately from the pad PD. Alternatively, the input sensor INS may be omitted and no longer include the input pad.

[0077] Figure 4 FIG. 4 is an equivalent circuit diagram of a pixel PXij according to an embodiment of the present invention.

[0078] Figure 4 A plurality of pixels PX are exemplarily shown in FIG. Figure 3) is an equivalent circuit diagram of a pixel PXij in FIG. Since each pixel in the plurality of pixels PX has the same circuit structure, the circuit structure related to the pixel PXij is described, and the specific description of the remaining pixels PX is omitted.

[0079] Reference Figure 3 and Figure 4 , the pixel PXij is connected to the i-th data line DLi among the data lines DL1-DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1-GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1-GCLm, the j-th write scan line GWLj among the write scan lines GWL1-GWLm, the j-th black scan line GBLj among the black scan lines GBL1-GBLm, the j-th light emission control line ECLj among the light emission control lines ECL1-ECLm, the first and second driving voltage lines VL1, VL2, and the first and second initialization voltage lines VL3, VL4. i is an integer greater than 1 and less than n, and j is an integer greater than 1 and less than m.

[0080] The pixel PXij includes a light emitting element ED and a pixel circuit PDC. The light emitting element ED may be a light emitting diode. As an example of the present invention, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer, but is not particularly limited thereto. The pixel circuit PDC may control the amount of current flowing through the light emitting element ED in accordance with the data signal Di. The light emitting element ED may emit light at a specified brightness in accordance with the amount of current provided from the pixel circuit PDC.

[0081] The pixel circuit PDC may include first to seventh transistors T1, T2, T3, T4, T5, T6, T7 and first to third capacitors Cst, Cbst, Nbst. According to the present invention, the structure of the pixel circuit PDC is not limited to Figure 4 The embodiment shown. Figure 4 The pixel circuit PDC shown is only an example, and the structure of the pixel circuit PDC may be modified for implementation.

[0082] At least one of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be a transistor having an oxide semiconductor layer. For example, the third and fourth transistors T3 and T4 may be oxide semiconductor transistors, and the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 may be LTPS transistors.

[0083] Specifically, with respect to the first transistor T1 that directly affects the brightness of the light-emitting element ED, it is constituted in a manner that includes a semiconductor layer composed of highly reliable polycrystalline silicon, thereby realizing a high-resolution display device. In addition, since the oxide semiconductor has high carrier mobility and low leakage current, the voltage drop will not be large even if the driving time is long. That is, even in the case of low-frequency driving, the color change of the image caused by the voltage drop will not be large, so low-frequency driving can be achieved. As described above, in the case of an oxide semiconductor, due to the advantage of less leakage current, at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 can be adopted as an oxide semiconductor, thereby preventing leakage current that may flow to the gate electrode and reducing power consumption.

[0084] Some of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be P-type transistors, and the rest may be N-type transistors. For example, the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 may be P-type transistors, and the third and fourth transistors T3 and T4 may be N-type transistors.

[0085] The structure of the pixel circuit PDC of the present invention is not limited to Figure 4 The embodiment shown. Figure 4 The pixel circuit PDC shown is only an example, and the structure of the pixel circuit PDC can be modified to implement. For example, the first to seventh transistors T1, T2, T3, T4, T5, T6, T7 can all be P-type transistors or N-type transistors. Alternatively, the first, second, fifth, and sixth transistors T1, T2, T5, and T6 can be P-type transistors, and the third, fourth, and seventh transistors T3, T4, and T7 can be N-type transistors.

[0086] The jth initialization scan line GILj, the jth compensation scan line GCLj, the jth write scan line GWLj, the jth black scan line GBLj, and the jth emission control line ECLj can respectively transmit the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj, the jth black scan signal GBj, and the jth emission control signal EMj to the pixel PXij. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di can have the same value as that input to the display device DD (refer to Figure 1A , Figure 1B )’s image signal corresponding to the voltage level.

[0087] The first and second driving voltage lines VL1 and VL2 can transmit the first driving voltage ELVDD and the second driving voltage ELVSS to the pixel PXij, respectively. Also, the first and second initialization voltage lines VL3 and VL4 can transmit the first initialization voltage VINT and the second initialization voltage VAINT to the pixel PXij, respectively.

[0088] The first transistor T1 may be connected between a first driving voltage line VL1 receiving a first driving voltage ELVDD and the light emitting element ED. The first transistor T1 includes: a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5; a second electrode connected to a pixel electrode (or, referred to as an anode) of the light emitting element ED via a sixth transistor T6; and a third electrode (e.g., a gate electrode) connected to one end of the first capacitor Cst (e.g., a first node N1). The first transistor T1 may receive the i-th data signal Di transmitted by the i-th data line DLi according to the switching action of the second transistor T2, and supply a driving current to the light emitting element ED.

[0089] The second transistor T2 is connected between the data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes: a first electrode connected to the data line DLi; a second electrode connected to the first electrode of the first transistor T1; and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 can be turned on according to the write scan signal GWj received through the j-th write scan line GWLj, and transmits the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1. One end of the second capacitor Cbst can be connected to the third electrode of the second transistor T2, and the other end of the second capacitor Cbst is connected to the first node N1.

[0090] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes: a first electrode connected to the third electrode of the first transistor T1; a second electrode connected to the second electrode of the first transistor T1; and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line GCLj. The third transistor T3 can be turned on according to the j-th compensation scan signal GCj received through the j-th compensation scan line GCLj, and the third electrode of the first transistor T1 and the second electrode of the first transistor T1 are connected to each other, so that the first transistor T1 is diode-connected. One end of the third capacitor Nbst can be connected to the third electrode of the third transistor T3, and the other end of the third capacitor Nbst is connected to the first node N1.

[0091] The fourth transistor T4 is connected between the first initialization voltage line VL3 to which the first initialization voltage VINT is applied and the first node N1. The fourth transistor T4 includes: a first electrode connected to the first initialization voltage line VL3 to which the first initialization voltage VINT is transmitted; a second electrode connected to the first node N1; and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line GILj. The fourth transistor T4 is turned on according to the j-th initialization scan signal GIj received through the j-th initialization scan line GILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT to the first node N1, thereby initializing the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0092] The fifth transistor T5 includes: a first electrode connected to the first driving voltage line VL1; a second electrode connected to the first electrode of the first transistor T1; and a third electrode (for example, a gate electrode) connected to the j-th light emitting control line ECLj. The sixth transistor T6 includes: a first electrode connected to the second electrode of the first transistor T1; a second electrode connected to the pixel electrode of the light emitting element ED; and a third electrode (for example, a gate electrode) connected to the j-th light emitting control line ECLj.

[0093] The fifth and sixth transistors T5 and T6 are simultaneously turned on according to the jth light emitting control signal EMj received through the jth light emitting control line ECLj. The first driving voltage ELVDD applied by the turned-on fifth transistor T5 can be compensated by the first transistor T1 connected in a diode manner and then transmitted to the light emitting element ED through the sixth transistor T6.

[0094] The seventh transistor T7 includes: a first electrode connected to the second initialization voltage line VL4 to which the second initialization voltage VAINT is transmitted; a second electrode connected to the second electrode of the sixth transistor T6; and a third electrode (e.g., a gate electrode) connected to the j-th black scan line GBLj. The second initialization voltage VAINT may have a voltage level lower than or equal to the first initialization voltage VINT.

[0095] One end of the first capacitor Cst is connected to the third electrode of the first transistor T1, and the other end of the first capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than the first driving voltage ELVDD.

[0096] Figure 5 The display panel DP (refer to Figure 2 ) display area DA (refer to Figure 2) is an enlarged top view of a portion of the FIG. Figure 5 The display module DM (refer to Figure 1B ) display surface IS (refer to Figure 1B ) is a plane of the display module DM observed from above, which shows the arrangement of the light-emitting areas PXA-R, PXA-G, and PXA-B.

[0097] Reference Figure 5 , the display area DA may include first to third light emitting areas PXA-R, PXA-G, PXA-B and a peripheral area NPXA surrounding the first to third light emitting areas PXA-R, PXA-G, PXA-B. The first to third light emitting areas PXA-R, PXA-G, PXA-B may correspond to areas where light provided by the light emitting element is emitted, respectively. The first to third light emitting areas PXA-R, PXA-G, PXA-B may be arranged according to the direction of the display module DM (refer to Figure 2 ) is divided by the color of the light emitted from the outside.

[0098] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may respectively provide first to third colored lights having different colors. For example, the first colored light may be red light, the second colored light may be green light, and the third colored light may be blue light. However, the examples of the first to third colored lights are not necessarily limited to the examples.

[0099] Each of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B can be defined as a region where the upper surface of the anode is exposed by a light-emitting opening described later. The peripheral region NPXA can set the boundaries of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B and prevent color mixing between the first to third light-emitting regions PXA-R, PXA-G, and PXA-B.

[0100] Each of the first to third light emitting regions PXA-R, PXA-G, and PXA-B may be provided in plurality, and have a prescribed arrangement shape and are repeatedly arranged in the display area DA. For example, the first and third light emitting regions PXA-R and PXA-B may be alternately arranged along the first direction DR1 and constitute a "first group". The second light emitting region PXA-G may be arranged along the first direction DR1 and constitute a "second group". Each of the "first group" and the "second group" may be provided in plurality, and the "first group" and the "second group" may be alternately arranged with each other along the second direction DR2.

[0101] One second light emitting region PXA-G may be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first and second directions DR1 and DR2.

[0102] in addition, Figure 5 The arrangement shape of the first to third light emitting regions PXA-R, PXA-G, and PXA-B is exemplarily shown in FIG. 1 , but the arrangement shape is not limited thereto and the first to third light emitting regions PXA-R, PXA-G, and PXA-B may be arranged in various shapes. Figure 5 Alternatively, the first to third light emitting regions PXA-R, PXA-G, and PXA-B may also have a stripe arrangement shape or a diamond pixel arrangement shape.

[0103] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may have various shapes on a plane, for example, polygonal, circular, or elliptical shapes. Figure 5 The first and third light emitting regions PXA-R and PXA-B having a quadrangular shape (or a diamond shape) on a plane and the second light emitting region PXA-G having an octagonal shape are exemplarily shown.

[0104] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may have the same shape as each other on a plane, or at least a part thereof may have a different shape from each other. Figure 5 illustratively show first and third light emitting regions PXA-R and PXA-B having the same shape as each other on a plane and a second light emitting region PXA-G having a shape different from the first and third light emitting regions PXA-R and PXA-B.

[0105] At least a portion of the first to third light emitting regions PXA-R, PXA-G, and PXA-B may have different areas on a plane. In one embodiment, the area of ​​the first light emitting region PXA-R emitting red light may be larger than the area of ​​the second light emitting region PXA-G emitting green light, and smaller than the area of ​​the third light emitting region PXA-B emitting blue light. However, the size relationship between the first to third light emitting regions PXA-R, PXA-G, and PXA-B corresponding to the light emitting colors is not limited thereto, but is determined according to the display module DM (refer to Figure 2 ) can be designed in various ways. Moreover, it is not limited thereto, and the first to third light emitting regions PXA-R, PXA-G, and PXA-B can also have the same area as each other on a plane.

[0106] In addition, the display module DM of the present invention (refer to Figure 2The shapes, areas, and arrangements of the first to third light emitting regions PXA-R, PXA-G, and PXA-B can be determined according to the color of the light emitted or the display module DM (see Figure 2 ) has a variety of sizes and structures, and is not limited to Figure 5 The embodiment shown.

[0107] Figure 6 It is along Figure 3 A cross-sectional view of a display panel of an embodiment of the present invention taken along line II'. Figure 6 In the course of the description, reference will be made to Figure 2 The description will be given below, and the description of the same figure numerals will be omitted.

[0108] Figure 6 The display area DA (refer to Figure 5 ) is enlarged to show a light emitting area PXA in the Figure 6 The light emitting area PXA can be Figure 5 corresponds to one of the first to third light emitting regions PXA-R, PXA-G, PXA-B. Figure 6 The display panel DP may include: a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0109] The display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers are formed by coating, deposition, etc. Subsequently, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and etching. In this way, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed.

[0110] The circuit element layer DP-CL may be disposed on the base layer BL and may include a buffer layer BFL, a transistor TR1, a signal transmission region SCL, first to fifth insulating layers 10, 20, 30, 40, 50, an electrode EE, and a plurality of connection electrodes CNE1, CNE2.

[0111] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0112] A semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, the present invention is not limited thereto, and the semiconductor pattern may also include amorphous silicon or metal oxide. Figure 6Only a part of the semiconductor pattern is shown by way of example. In the plurality of light emitting regions PXA-R, PXA-G, PXA-B (see Figure 5 ) may be further configured with a semiconductor pattern. The semiconductor pattern may be arranged according to a specific rule within the range of the plurality of light emitting regions PXA-R, PXA-G, and PXA-B. The semiconductor pattern may have different electrical properties depending on whether it is doped or not. The semiconductor pattern may include a first region with a large doping concentration and a second region with a small doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0113] The first region is more conductive than the second region, and the first region substantially functions as an electrode or a signal line. The second region substantially corresponds to the active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern may be the active region of a transistor, another portion may be the source or drain of the transistor, and another portion may be a conductive region.

[0114] The source S, the active electrode A, and the drain D of the transistor TR1 may be formed from a semiconductor pattern. Figure 6 A portion of a signal transmission region SCL formed from a semiconductor pattern is shown in . Although not shown separately, the signal transmission region SCL may be connected to the drain D of the transistor TR1 in a plane.

[0115] The first to fifth insulating layers 10, 20, 30, 40, 50 may be disposed on the buffer layer BFL. The first to fifth insulating layers 10, 20, 30, 40, 50 may be inorganic layers or organic layers.

[0116] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source S, active A, drain D, and signal transmission region SCL of the transistor TR1 disposed on the buffer layer BFL. The gate G of the transistor TR1 may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 and cover the gate G. An electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 and cover the electrode EE.

[0117] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transfer region SCL through a contact hole CNT-1 penetrating the first to third insulating layers 10, 20, 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 and cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0118] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 penetrating the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0119] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include: a light emitting element ED, a sacrificial pattern SP, a pixel definition film PDL, and a partition wall PW.

[0120] The light emitting element ED may include an anode AE ​​(or a first electrode), a light emitting pattern EP, and a cathode CE (or a second electrode).

[0121] The anode AE ​​may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 through a contact hole CNT-3 defined by penetrating the fifth insulating layer 50. Therefore, the anode AE ​​may be electrically connected to the signal transfer region SCL through the first and second connection electrodes CNE1 and CNE2, thereby being electrically connected to the corresponding circuit element. The anode AE ​​may include a single-layer or multi-layer structure. The anode AE ​​may include a plurality of layers including ITO and Ag. For example, the anode AE ​​may include a layer including ITO (hereinafter referred to as the lower ITO layer), a layer including Ag disposed on the lower ITO layer (hereinafter referred to as the Ag layer), and a layer including ITO disposed on the Ag layer (hereinafter referred to as the upper ITO layer).

[0122] The sacrificial pattern SP may be disposed between the anode AE ​​and the pixel definition layer PDL. A sacrificial opening OP-S exposing a portion of the upper surface of the anode AE ​​may be defined in the sacrificial pattern SP. The sacrificial opening OP-S may overlap with a light emitting opening OP-E described later.

[0123] The pixel definition film PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. A light emitting opening OP-E may be defined in the pixel definition film PDL. The light emitting opening OP-E may correspond to the anode AE, and the pixel definition film PDL may expose at least a portion of the anode AE ​​through the light emitting opening OP-E.

[0124] Furthermore, the light emitting opening OP-E may correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to the present embodiment, the sacrificial pattern SP may be interposed between the upper surface of the anode AE ​​and the pixel definition film PDL so that the upper surface of the anode AE ​​is separated from the pixel definition film PDL in a cross section, thereby protecting the anode AE ​​from damage during the formation process of the light emitting opening OP-E.

[0125] On a plane, the area of ​​the light-emitting opening OP-E may be smaller than the area of ​​the sacrificial opening OP-S. That is, the inner side surface of the pixel definition film PDL defining the light-emitting opening OP-E may be closer to the center of the anode AE ​​than the inner side surface of the sacrificial pattern SP defining the sacrificial opening OP-S. However, this is not limited to this, and the inner side surface of the sacrificial pattern SP defining the sacrificial opening OP-S may be substantially aligned with the inner side surface of the pixel definition film PDL defining the light-emitting opening OP-E. In this case, the light-emitting area PXA may also be regarded as the area of ​​the anode AE ​​exposed from the corresponding sacrificial opening OP-S.

[0126] The pixel definition film PDL may include an inorganic insulating material, such as silicon nitride (SiNx or silicon nitride). The pixel definition film PDL may be disposed between the anode AE ​​and the partition wall PW to block the anode AE ​​and the partition wall PW from being electrically connected to each other.

[0127] The light-emitting pattern EP may be arranged on the anode AE. The light-emitting pattern EP may include a light-emitting layer including a light-emitting substance. The light-emitting pattern EP may also include a hole injection layer (HIL) and a hole transport layer (HTL) arranged between the anode AE ​​and the light-emitting layer, and may also include an electron transport layer (ETL) and an electron injection layer (EIL) arranged on the light-emitting layer. The light-emitting pattern EP may also be referred to as an "organic layer" or an "intermediate layer".

[0128] The light emitting pattern EP may be patterned by being defined at the tip of the partition wall PW. The light emitting pattern EP may be disposed inside the sacrificial opening OP-S, the light emitting opening OP-E, and the partition wall opening OP-P. The light emitting pattern EP may cover a portion of the upper surface of the pixel definition film PDL exposed from the partition wall opening OP-P.

[0129] The cathode CE may be disposed on the light emitting pattern EP. The cathode CE may be patterned by being defined at the tip of the partition wall PW. At least a portion of the cathode CE may be disposed at the partition wall opening OP-P. The cathode CE may be in contact with the first inner side surface S-LS1 and S-LS2 of the first partition wall layer L1. For example, the cathode CE may extend along the inner side surface S-LS1 of the first sub-layer LS1 and the inner side surface S-LS2 of the second sub-layer LS2 described later, and the end of the cathode CE may be in contact with the second sub-layer LS2.

[0130] The cathode CE may be conductive. As long as it is conductive, the cathode CE may be formed of a variety of materials, such as metal, transparent conductive oxide (TCO) or conductive polymer material. For example, the cathode CE may contain silver (Ag), magnesium (Mg), lead (Pb), copper (Cu) or a compound thereof.

[0131] In one embodiment of the present invention, the display element layer DP-OLED may further include a capping pattern. The capping pattern may be disposed in the partition wall opening OP-P and disposed on the cathode CE. The capping pattern may be patterned by being formed at the tip of the partition wall PW.

[0132] The partition wall PW may be disposed on the pixel definition film PDL. A partition wall opening OP-P may be defined in the partition wall PW. The partition wall opening OP-P may correspond to the light emitting opening OP-E and expose at least a portion of the anode AE.

[0133] The partition wall PW may have an undercut shape in cross section. The partition wall PW may include a plurality of layers stacked in sequence, and at least one of the plurality of layers may be recessed than the other layers. Thus, the partition wall PW may include a tip portion.

[0134] The partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 may be disposed on the pixel definition layer PDL, and the second partition wall layer L2 may be disposed on the first partition wall layer L1. Figure 6 As shown, the thickness of the first partition wall layer L1 may be greater than the thickness of the second partition wall layer L2 , but is not limited thereto.

[0135] For the light emitting region PXA, the first partition wall layer L1 may be relatively more recessed than the second partition wall layer L2. The first partition wall layer L1 may be formed by undercutting the second partition wall layer L2. A portion of the second partition wall layer L2 that protrudes from the first partition wall layer L1 toward the light emitting region PXA may be defined as a tip portion within the partition wall PW.

[0136] The partition wall opening OP-P defined in the partition wall PW may include a first area A1 and a second area A2. The width of the first area A1 may be different from the width of the second area A2. The width of the first area A1 in the first direction DR1 may be greater than the width of the second area A2 in the first direction DR1. In this case, the second area A2 of the partition wall opening OP-P may be an area defining a tip portion. That is, due to the protruding tip portion, the second area A2 may have a narrower width than the first area A1.

[0137] The first partition wall layer L1 may include first inner side surfaces S-LS1 and S-LS2 defining the first area A1 of the partition wall opening OP-P, and the second partition wall layer L2 may include a second inner side surface S-L2 defining the second area A2. In cross section, the second inner side surface S-L2 of the second partition wall layer L2 may be closer to the center of the anode AE ​​than the first inner side surfaces S-LS1 and S-LS2 of the first partition wall layer L1. The first inner side surfaces S-LS1 and S-LS2 may be more recessed in a direction away from the center of the anode AE ​​than the second inner side surface S-L2. Thus, the second partition wall layer L2 protruding toward the light emitting area PXA may include a tip portion.

[0138] The first partition wall layer L1 may include a first sub-layer LS1 and a second sub-layer LS2. The first sub-layer LS1 may be disposed on the pixel definition film PDL, and the second sub-layer LS2 may be disposed on the first sub-layer LS1. The first inner side surfaces S-LS1 and S-LS2 of the first partition wall layer L1 may include the inner side surface S-LS1 of the first sub-layer LS1 and the inner side surface S-LS2 of the second sub-layer LS2. The inner side surface S-LS1 of the first sub-layer LS1 and the inner side surface S-LS2 of the second sub-layer LS2 may be aligned. The thickness T-LS1 of the first sub-layer LS1 may be (Angstroms) or more and The thickness T-LS2 of the second sub-layer LS2 can be (Angstroms) or more and The thickness T-L2 of the second partition wall layer L2 can be (Angstroms) or more and (Angstroms) or less.

[0139] Each of the first partition wall layer L1 and the second partition wall layer L2 may contain a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (Transparent Conductive Oxide, TCO) or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or an alloy thereof. The transparent conductive oxide may include indium tin oxide (IndiumTin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), zinc oxide (Zinc Oxide), indium oxide (IndiumOxide), indium gallium oxide (Indium Gallium Oxide), indium gallium zinc oxide (Indium Gallium ZincOxide, IGZO) or aluminum zinc oxide (Aluminum Zinc Oxide).

[0140] In particular, the first partition wall layer L1 may include an amorphous alloy. In detail, the second sublayer LS2 of the first partition wall layer L1 may include an amorphous alloy. The amorphous alloy may include at least one of an amorphous molybdenum alloy and an amorphous tungsten alloy. For example, the second sublayer LS2 may be an alloy in which nickel (Ni) and titanium (Ti) are combined in a ratio of 20 to 30% in molybdenum (Mo), or an alloy in which nickel (Ni) and tantalum (Ta) are combined in a ratio of 20 to 30% in molybdenum (Mo). However, this is merely illustrative, and the metal and ratio of the second sublayer LS2 are not limited to the examples.

[0141] exist Figure 6 The first inner side surface S-LS1, S-LS2 and the second inner side surface S-L2 are exemplarily shown as being perpendicular to the upper surface of the pixel definition film PDL, but the present invention is not limited thereto. For example, the partition wall PW may also have a tapered shape or an inverted tapered shape.

[0142] The partition wall PW may receive the second driving voltage ELVSS (refer to Figure 4 ), thus, since the cathode CE is electrically connected to the partition wall PW, it can receive the second driving voltage ELVSS (refer to Figure 4 ).

[0143] A dummy area DMA may be formed on the partition wall PW. Specifically, the dummy area DMA may be formed between the partition wall PW and the lower package inorganic pattern LIL in a cross section. The dummy area DMA may be defined as a first dummy layer D1, D2 formed in the display panel manufacturing process described later (see Figure 9G ) is the area that is removed.

[0144] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include: a lower encapsulation inorganic pattern LIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0145] The lower encapsulation inorganic pattern LIL may be formed corresponding to the light emitting opening OP-E. The lower encapsulation inorganic pattern LIL may be disposed on the cathode CE and cover the light emitting element ED. In detail, a portion of the lower encapsulation inorganic pattern LIL may be formed in the partition wall opening OP-P, and another portion of the lower encapsulation inorganic pattern LIL may be formed on the partition wall PW.

[0146] The encapsulation organic film OL may be disposed on and cover the lower encapsulation inorganic pattern LIL and may provide a flat upper surface. A portion of the encapsulation organic film OL may fill the dummy area DMA. The upper encapsulation inorganic film UIL may be disposed on the encapsulation organic film OL.

[0147] The lower encapsulation inorganic pattern LIL and the upper encapsulation inorganic film UIL may protect the display element layer DP-OLED from moisture / oxygen, and the encapsulation organic film OL may protect the display element layer DP-OLED from impurities such as dust particles.

[0148] Figure 7 It is along Figure 5 A cross-sectional view taken along line II-II'. Figure 7 A first light emitting region PXA-R, a second light emitting region PXA-G, and a third light emitting region PXA-B are shown in an enlarged manner. Figure 6 The description for a light emitting area PXA can also be applied to Figure 7 Each light-emitting area in the first to third light-emitting areas PXA-R, PXA-G, and PXA-B.

[0149] Reference Figure 7 The display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED may include light emitting elements ED1, ED2, ED3, sacrificial patterns SP1, SP2, SP3, a pixel definition film PDL, and a partition wall PW.

[0150] The light emitting elements ED1, ED2, ED3 may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3. The first light emitting element ED1 may include a first anode AE1, a first light emitting pattern EP1, and a first cathode CE1. The second light emitting element ED2 may include a second anode AE2, a second light emitting pattern EP2, and a second cathode CE2. The third light emitting element ED3 may include a third anode AE3, a third light emitting pattern EP3, and a third cathode CE3. The first to third anodes AE1, AE2, AE3 may be provided in a plurality of patterns. In one embodiment, the first light emitting pattern EP1 may provide red light, the second light emitting pattern EP2 may provide green light, and the third light emitting pattern EP3 may provide blue light.

[0151] The pixel definition film PDL may define first to third light emitting openings OP1-E, OP2-E, and OP3-E. The first light emitting opening OP1-E may expose at least a portion of the first anode AE1. The second light emitting opening OP2-E may expose at least a portion of the second anode AE2. The third light emitting opening OP3-E may expose at least a portion of the third anode AE3.

[0152] In the present embodiment, the first light emitting region PXA-R may be defined as a region of the upper surface of the first anode AE1 exposed through the first light emitting opening portion OP1-E. The second light emitting region PXA-G may be defined as a region of the upper surface of the second anode AE2 exposed through the second light emitting opening portion OP2-E. The third light emitting region PXA-B may be defined as a region of the upper surface of the third anode AE3 exposed through the third light emitting opening portion OP3-E.

[0153] The sacrificial patterns SP1, SP2, SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first to third sacrificial patterns SP1, SP2, SP3 may be disposed on the upper surfaces of the first to third anodes AE1, AE2, AE3, respectively. The first to third sacrificial openings OP1-S, OP2-S, OP3-S may be defined in the first to third sacrificial patterns SP1, SP2, SP3 and overlap the first to third light emitting openings OP1-E, OP2-E, OP3-E, respectively.

[0154] In this embodiment, the partition wall PW may define first to third partition wall openings OP1-P, OP2-P, OP3-P that overlap the first to third light emitting openings OP1-E, OP2-E, OP3-E, respectively. Each of the first to third partition wall openings OP1-P, OP2-P, OP3-P may include Figure 6 The first area A1 (see Figure 6 ) and the second area A2 (refer to Figure 6 The first partition wall layer L1 may include first inner side surfaces S-LS1, S-LS2 (see FIG. 2 ) defining first to third partition wall openings OP1-P, OP2-P, OP3-P in a first area A1. Figure 6 ), the second partition wall layer L2 may include a second inner side surface S-L2 (refer to Figure 6 ).

[0155] A first light emitting pattern EP1 and a first cathode CE1 may be disposed in the first partition wall opening OP1-P, a second light emitting pattern EP2 and a second cathode CE2 may be disposed in the second partition wall opening OP2-P, and a third light emitting pattern EP3 and a third cathode CE3 may be disposed in the third partition wall opening OP3-P.

[0156] In this embodiment, the first to third light-emitting patterns EP1, EP2, EP3 and the first to third cathodes CE1, CE2, CE3 can be physically separated by the second partition wall layer L2 forming the tip portion and formed in each light-emitting opening portion OP1-E, OP2-E, OP3-E or the partition wall opening portion OP1-P, OP2-P, OP3-P.

[0157] According to the present invention, a plurality of first emission patterns EP1 can be patterned and deposited in pixel units by defining the tip portion of the partition wall PW. That is, the first emission patterns EP1 can be formed collectively using an open mask, but can be easily divided in pixel units by the partition wall PW.

[0158] On the other hand, when the first light-emitting pattern EP1 is patterned using a fine metal mask (FMM), a supporting spacer protruding from the conductive partition wall is required to support the fine metal mask. In addition, since the fine metal mask is separated from the substrate surface for patterning by the height of the partition wall and the spacer, it has limitations in achieving high resolution. In addition, since the fine metal mask is in contact with the spacer, after the patterning process of the first light-emitting pattern EP1, impurities may remain in the spacer or the spacer may be punctured by the fine metal mask and damaged. As a result, a poor display panel may be formed.

[0159] According to this embodiment, since the partition wall PW is included, physical separation between the light emitting elements ED1, ED2, and ED3 can be easily achieved. Therefore, leakage or erroneous driving between adjacent light emitting regions PXA-R, PXA-G, and PXA-B can be prevented, and each light emitting element ED1, ED2, and ED3 can be driven independently.

[0160] In particular, in the unused and display area DA (refer to Figure 1B ), the plurality of first light emitting patterns EP1 are patterned in the case of a mask that contacts the internal structure in the partition wall PW, thereby reducing the defect rate and providing a display panel DP with improved process reliability. Since patterning can be performed even without providing an additional supporting spacer protruding from the partition wall PW, the areas of the light emitting regions PXA-R, PXA-G, and PXA-B can be refined, thereby providing a display panel DP that can easily achieve high resolution.

[0161] Furthermore, when manufacturing a large-area display panel DP, the process cost can be saved by omitting the large-area mask production, and the display panel DP with improved process reliability can be provided without being affected by the adverse effects that may occur in the large-area mask. The description of the plurality of first light emitting patterns EP1 can also be applied to the plurality of second and third light emitting patterns EP2 and EP3.

[0162] The thin film encapsulation layer TFE may include lower encapsulation inorganic patterns LIL1 , LIL2 , LIL3 , an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0163] In the present embodiment, the lower encapsulation inorganic patterns LIL1, LIL2, LIL3 may include a first lower encapsulation inorganic pattern LIL1, a second lower encapsulation inorganic pattern LIL2, and a third lower encapsulation inorganic pattern LIL3. The first to third lower encapsulation inorganic patterns LIL1, LIL2, LIL3 may overlap with the first to third light emitting opening portions OP1-E, OP2-E, OP3-E, respectively. The first to third lower encapsulation inorganic patterns LIL1, LIL2, LIL3 may be provided in pattern shapes spaced apart from each other.

[0164] The first lower encapsulation inorganic pattern LIL1 may cover the first light emitting element ED1. A portion of the first lower encapsulation inorganic pattern LIL1 may be formed in the first partition wall opening OP1-P, and another portion of the first lower encapsulation inorganic pattern LIL1 may be formed on the partition wall PW. In a cross section, a first dummy area DMA1 may be formed between the partition wall PW defining the first partition wall opening OP1-P and the first lower encapsulation inorganic pattern LIL1.

[0165] The second lower encapsulation inorganic pattern LIL2 may cover the second light emitting element ED2. A portion of the second lower encapsulation inorganic pattern LIL2 may be formed within the second partition wall opening OP2-P, and another portion of the second lower encapsulation inorganic pattern LIL2 may be formed on the partition wall PW. In cross section, a second dummy area DMA2 may be formed between the partition wall PW defining the second partition wall opening OP2-P and the second lower encapsulation inorganic pattern LIL2.

[0166] The third lower encapsulation inorganic pattern LIL3 may cover the third light emitting element ED3. A portion of the third lower encapsulation inorganic pattern LIL3 may be formed in the third partition wall opening OP3-P, and another portion of the third lower encapsulation inorganic pattern LIL3 may be formed on the partition wall PW. In cross section, a third dummy area DMA3 may be formed between the partition wall PW defining the third partition wall opening OP3-P and the third lower encapsulation inorganic pattern LIL3.

[0167] Fig. 8A is a cross-sectional view of the second sub-layer of the comparative example. Figure 8B It is the second sub-layer LS2 of one embodiment of the present invention (refer to Figure 6 ) cross-sectional view.

[0168] Reference Fig. 8A A portion of the partition wall containing a conductive material in the prior art (for example, a portion corresponding to the second sub-layer LS2) may have a columnar crystal structure. Therefore, it may be susceptible to moisture permeation from the side of the partition wall.

[0169] Reference Figure 6 and Figure 8B The second sublayer LS2 of the first partition wall layer L1 of the present invention may include at least one of an amorphous molybdenum alloy and an amorphous tungsten alloy. The second sublayer LS2 may not have a columnar crystal structure. Thus, the bonding force between the second sublayer LS2 and the cathode CE can be improved, and the moisture permeability reliability can be improved. Thus, the display panel DP (refer to Figure 6 ) pixel defects (dark spots, pixel shrinkage, etc.).

[0170] Furthermore, the first partition wall layer L1 may include a first sublayer LS1 and a second sublayer LS2 including molybdenum or tungsten. Since the first partition wall layer L1 includes molybdenum or tungsten, the phenomenon of increased resistance due to the formation of an oxide film on the first partition wall layer L1 can be reduced or eliminated. That is, the partition wall PW of the present invention may have low resistance because no interface oxide film is formed, so the electrical reliability of the display panel DP can be improved.

[0171] FIG. 9A to FIG. 9KFIG. 1 is a cross-sectional view showing a portion of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. FIG. 9A to FIG. 9K In the course of the description, reference will be made to Figures 1A to 7 The same or similar structures are described using the same or similar reference numerals, and repeated description is omitted.

[0172] The manufacturing method of the display panel of the present invention may include: a step of providing a preliminary display panel, wherein the preliminary display panel includes a base layer and a pixel definition film arranged on the base layer; a step of forming a first preliminary partition wall layer containing an amorphous alloy on the preliminary display panel; a step of forming a second preliminary partition wall layer on the first preliminary partition wall layer; a step of etching the second preliminary partition wall layer to form a second partition wall layer defining a first opening portion; and a step of etching the first preliminary partition wall layer to form a first partition wall layer defining a second opening portion.

[0173] Below, through FIG. 9A to FIG. 9K For forming a light emitting element (for example, the first light emitting element ED1 (refer to Figure 7 )) and a lower package inorganic pattern (eg, a first lower package inorganic pattern LIL1 (refer to Figure 7 )) and the method of encapsulating the organic film OL and the upper encapsulating inorganic film UIL are described. FIG. 9A to FIG. 9K The display panel formed can be Figure 6 Corresponding to the display panel DP.

[0174] Reference Fig. 9A The manufacturing method of the display panel of the present invention may include the step of providing a preliminary display panel DP-I. The preliminary display panel DP-I provided in this embodiment may include a base layer BL, a circuit element layer DP-CL, an anode AE, a preliminary sacrificial pattern SP-I and a pixel definition film PDL.

[0175] The circuit element layer DP-CL can be formed by a conventional circuit element manufacturing process, which is as follows: an insulating layer, a semiconductor layer and a conductive layer are formed by coating, deposition, etc., and the insulating layer, the semiconductor layer and the conductive layer are selectively patterned by photolithography and etching processes to form semiconductor patterns, conductive patterns and signal lines, etc.

[0176] The anode AE ​​and the preliminary sacrificial pattern SP-I may be formed by the same patterning process. The pixel definition film PDL may be formed on the circuit element layer DP-CL. The pixel definition film PDL may cover both the anode AE ​​and the preliminary sacrificial pattern SP-I.

[0177] Then, refer to Fig. 9B The manufacturing method of the display panel of the present invention may include: preparing a display panel DP-I (referring to Fig. 9A ) on the first preliminary partition wall layer L1-I containing an amorphous alloy; and on the first preliminary partition wall layer L1-I on the second preliminary partition wall layer L2-I.

[0178] In the preparation display panel DP-I (refer to Fig. 9A The step of forming a first preliminary partition wall layer L1-I including an amorphous alloy on the pixel definition film PDL may include: forming a first preliminary sub-layer LS1-I on the pixel definition film PDL; and forming a second preliminary sub-layer LS2-I on the first preliminary sub-layer LS1-I. The first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may form a preliminary partition wall PW-I.

[0179] The step of forming the first preliminary sub-layer LS1-I may include: (Angstrom) to (Angstrom) thickness for deposition. That is, the step of forming the first preliminary sub-layer LS1-I can be formed by a deposition process of a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (Transparent Conductive Oxide, TCO) or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or an alloy thereof. The transparent conductive oxide may include indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), zinc oxide (Zinc Oxide), indium oxide (Indium Oxide), indium gallium oxide (Indium Gallium Oxide), indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) or aluminum zinc oxide (Aluminum Zinc Oxide). In this embodiment, the first preliminary sub-layer LS1-I may be aluminum (Al).

[0180] The step of forming the second preliminary sub-layer LS2-I may include forming an amorphous alloy with (Angstrom) to For example, the second preliminary sub-layer LS2-I may include at least one of an amorphous molybdenum alloy and an amorphous tungsten alloy.

[0181] The step of forming the second preliminary partition wall layer L2-I may include: (Angstrom) to The step of depositing a thickness of (angstroms). That is, the step of forming the second preliminary partition wall layer L2-I can be formed by a deposition process of a conductive material. For example, the conductive material may include a metal, a transparent conductive oxide (Transparent Conductive Oxide, TCO) or a combination thereof. For example, the metal may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or an alloy thereof. The transparent conductive oxide may include indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO), zinc oxide (Zinc Oxide), indium oxide (Indium Oxide), indium gallium oxide (Indium Gallium Oxide), indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO) or aluminum zinc oxide (Aluminum Zinc Oxide). In the present embodiment, the second preliminary partition wall layer L2-I may be titanium (Ti).

[0182] Then, refer to Fig. 9C The manufacturing method of the display panel of the present invention may include the step of forming a first photoresist layer PR1 on the preliminary partition wall PW-I. The first photoresist layer PR1 may be formed in the following manner: after forming the preliminary photoresist layer on the preliminary partition wall PW-I, the preliminary photoresist layer is patterned using a photomask. Through the patterning process, an optical opening OP-PR overlapping with the anode AE ​​may be formed in the first photoresist layer PR1.

[0183] Then, refer to Fig.9D and Fig.9E , in order to Fig. 9C ) forms a partition wall PW, the manufacturing method of the display panel of the present invention may include: a step of etching the second preliminary partition wall layer L2-I to form a second partition wall layer L2; and a step of etching the first preliminary partition wall layer L1-I to form a first partition wall layer L1.

[0184] First, if Fig.9D As shown, in the step of etching the second preliminary partition wall layer L2-I, the first photoresist layer PR1 can be used as a mask to perform dry etching on the second preliminary partition wall layer L2-I. The etched portion of the second preliminary partition wall layer L2-I is removed, so that the first opening OP1 can be formed in the second preliminary partition wall layer L2-I, and the second partition wall layer L2 having the first opening OP1 defined therein can be formed from the second preliminary partition wall layer L2-I.

[0185] Then, if Fig.9E As shown, in the step of etching the first preliminary partition wall layer L1-I, the first photoresist layer PR1 can be used as a mask to wet etch the first preliminary partition wall layer L1-I. The etched portion of the first preliminary partition wall layer L1-I is removed, so that the second opening OP2 can be formed in the first preliminary partition wall layer L1-I, and the first partition wall layer L1 with the second opening OP2 defined can be formed from the first preliminary partition wall layer L1-I. The first opening OP1 and the second opening OP2 can form a partition wall opening OP-P. The first opening OP1 and the second opening OP2 of the partition wall opening OP-P can be openings formed integrally.

[0186] The partition wall opening OP-P may include first regions A1 (see Figure 6 ) and the second area A2 (refer to Figure 6 ). The first area A1 may correspond to the second opening OP2, and the second area A2 may correspond to the first opening OP1. A width D-L2 of the first opening OP1 in the first direction DR1 may be smaller than a width D-L1 of the second opening OP2 in the first direction DR1.

[0187] In detail, the step of etching the first preliminary partition wall layer L1-I to form the first partition wall layer L1 may include: etching the second preliminary sub-layer LS2-I to form the second sub-layer LS2; and etching the first preliminary sub-layer LS1-I to form the first sub-layer LS1.

[0188] The first photoresist layer PR1 can be used as a mask to perform wet etching on the second preliminary sub-layer LS2-I. The etched portion of the second preliminary sub-layer LS2-I is removed, so that an inner side surface S-LS2 defining the second opening OP2 can be formed in the second preliminary sub-layer LS2-I (refer to Figure 6 ), and the second sub-layer LS2 can be formed from the second preliminary sub-layer LS2-I. Furthermore, the first photoresist layer PR1 can be used as a mask to perform wet etching on the first preliminary sub-layer LS1-I. The etched portion of the first preliminary sub-layer LS1-I is removed, so that the inner side surface S-LS1 defining the second opening OP2 can be formed in the first preliminary sub-layer LS1-I (refer to Figure 6 ), and the first sub-layer LS1 may be formed from the first preliminary sub-layer LS1-1. The inner side surface S-LS1 of the first sub-layer LS1 may be aligned with the inner side surface S-LS2 of the second sub-layer LS2.

[0189] The first partition wall layer L1 may include first inner side surfaces S-LS1 and S-LS2 defining the first area A1 of the partition wall opening OP-P, and the second partition wall layer L2 may include a second inner side surface S-L2 defining the second area A2 (see Figure 6 ).

[0190] The wet etching process in this embodiment can be performed in an environment where the etching selectivity of the first partition wall layer L1 to the second partition wall layer L2 is high. Thus, the inner side surface of the partition wall PW defining the partition wall opening OP-P can have an undercut shape in cross section. Specifically, for the etching solution, the etching rate of the first partition wall layer L1 is greater than the etching rate of the second partition wall layer L2, so the first partition wall layer L1 can be mainly etched. Thus, the first inner side surface S-LS1 and S-LS2 of the first partition wall layer L1 can be formed more recessed inward than the second inner side surface S-L2 of the second partition wall layer L2. A tip portion can be formed on the partition wall PW based on a portion of the second partition wall layer L2 that protrudes more than the first partition wall layer L1.

[0191] According to the present invention, after the second partition wall layer L2 is dry-etched, the first partition wall layer L1 is wet-etched to form an undercut, thereby facilitating the process of forming the partition wall PW. Therefore, the process reliability and efficiency of the display panel DP can be improved.

[0192] Although Fig.9D and Fig.9E The example of forming a partition wall opening OP-P is shown in FIG. 1 , but the present invention is not limited thereto. In one embodiment of the present invention, the step of forming the partition wall opening OP-P may include: simultaneously forming the first to third light emitting regions PXA-R, PXA-G, PXA-B (refer to FIG. 1 ); Figure 7 ) corresponding to the partition wall openings OP1-P, OP2-P, OP3-P (refer to Figure 7 In another embodiment of the present invention, the step of forming the partition wall opening OP-P may include: forming only the first partition wall opening OP1-P corresponding to the first light emitting region PXA-R. For example, after forming the first partition wall opening OP1-P corresponding to the first light emitting region PXA-R, and forming the first light emitting element ED1 (refer to Figure 7 ) After that, the second partition wall opening OP2-P corresponding to the second light emitting region PXA-G can be formed. In addition, the second light emitting element ED2 can be formed by a subsequent process (refer to Figure 7 ) and form a third partition wall opening OP3-P corresponding to the third light emitting area PXA-B.

[0193] Then, refer to Fig.9F The manufacturing method of the display panel of the present invention may include: etching the pixel definition film PDL; and etching the preliminary sacrificial pattern SP-I (refer to Fig.9E ). The etching process of the pixel definition film PDL can be performed by dry etching, and the first photoresist layer PR1 and the partition wall PW (for example, the second partition wall layer L2) can be used as masks for etching. A light emitting opening OP-E corresponding to the partition wall opening OP-P can be formed in the pixel definition film PDL.

[0194] The etching process of the preliminary sacrificial pattern SP-I can be performed by wet etching, and the first photoresist layer PR1 and the partition wall PW (for example, the second partition wall layer L2) can be used as masks for etching. In the sacrificial pattern SP formed by etching the preliminary sacrificial pattern SP-I, a sacrificial opening OP-S overlapping with the light-emitting opening OP-E can be formed. Through the sacrificial opening OP-S and the light-emitting opening OP-E, at least a portion of the anode AE ​​can be exposed from the sacrificial pattern SP and the pixel definition film PDL.

[0195] The etching process of the sacrificial pattern SP can be performed in an environment where the etching selectivity ratio of the sacrificial pattern SP to the anode AE ​​is high, thereby preventing the anode AE ​​from being etched together. That is, by arranging the sacrificial pattern SP having a higher etching rate than the anode AE ​​between the pixel definition film PDL and the anode AE, the anode AE ​​can be prevented from being etched together and damaged during the etching process.

[0196] Then, refer to Figure 9G The manufacturing method of the display panel of the present invention may include: removing the first photoresist layer PR1 (refer to Fig.9F ), and then forming a light emitting element ED in the partition wall opening OP-P. The step of forming the light emitting element ED may include: forming a light emitting pattern EP; and forming a cathode CE.

[0197] The step of forming the light-emitting pattern EP may include a deposition process of the light-emitting layer. In one embodiment, the deposition process of the light-emitting layer may be a thermal evaporation process. However, it is merely illustrative, and the deposition process of the light-emitting layer is not limited to the example. The light-emitting layer may be formed separately at the tip of the partition wall PW, so as to form the light-emitting pattern EP and the first dummy layer D1. The light-emitting pattern EP may be formed on the anode AE ​​in the light-emitting opening portion OP-E and the partition wall opening portion OP-P. A portion of the first dummy layer D1 may be formed in the second and third partition wall opening portions OP2-P, OP3-P (or the second and third light-emitting opening portions OP2-E, OP3-E, refer to Figure 7 ), another portion of the first dummy layer D1 may be formed on the partition wall PW.

[0198] That is, in the step of forming the light emitting pattern EP, a first dummy layer D1 spaced apart from the light emitting pattern EP may be formed together. The first dummy layer D1 may contain an organic substance. For example, the first dummy layer D1 may contain the same substance as the light emitting pattern EP. The first dummy layer D1 may be formed simultaneously with the light emitting pattern EP through one process, and may be formed by being separated from the light emitting pattern EP by the undercut shape of the partition wall PW.

[0199] The step of forming the cathode CE may include a deposition process of the cathode layer. In one embodiment, the deposition process of the cathode layer may be a sputtering process. However, this is merely illustrative, and the deposition process of the cathode layer is not limited to the example. The cathode layer may be formed at the tip of the partition wall PW to separate, thereby forming the cathode CE and the second dummy layer D2. The cathode CE may be formed on the light-emitting pattern EP in the light-emitting opening OP-E and the partition wall opening OP-P. A portion of the second dummy layer D2 may be formed on the inner side of the second and third partition wall openings OP2-P, OP3-P (or the second and third light-emitting openings OP2-E, OP3-E), and another portion of the second dummy layer D2 may be formed on the partition wall PW.

[0200] That is, in the step of forming the cathode CE, a second dummy layer D2 spaced apart from the cathode CE may be formed together. The second dummy layer D2 may include a conductive material. For example, the second dummy layer D2 may include the same material as the cathode CE. The second dummy layer D2 may be formed simultaneously with the cathode CE through one process, and may be formed by being separated from the cathode CE by the undercut shape of the partition wall PW.

[0201] The anode AE, the light emitting pattern EP and the cathode CE may be sequentially stacked along the third direction DR3. The anode AE, the light emitting pattern EP and the cathode CE may form a light emitting element ED. The first dummy layer D1 and the second dummy layer D2 may be sequentially stacked along the third direction DR3. A dummy opening OP-D may be formed in the first dummy layer D1 and the second dummy layer D2.

[0202] In one embodiment of the present invention, the manufacturing method of the display panel may further include the step of forming a covering pattern. The step of forming the covering pattern may include a deposition process of a covering pattern layer. The deposition process of the covering pattern layer may be a thermal evaporation process. The covering pattern layer may be separated by the tip portion of the partition wall PW, thereby forming a covering pattern and a third dummy layer. The covering pattern may be formed on the cathode CE in the partition wall opening OP-P. A portion of the third dummy layer may be formed on the inner side of the second and third partition wall openings OP2-P and OP3-P, and another portion of the third dummy layer may be formed on the partition wall PW.

[0203] That is, in the step of forming the covering pattern, a third dummy layer spaced apart from the covering pattern may be formed together. The third dummy layer may contain a conductive material. For example, the third dummy layer may contain the same material as the covering pattern. The third dummy layer may be formed simultaneously with the covering pattern through one process, and may be formed by being separated from the covering pattern by the undercut shape of the partition wall PW.

[0204] Then, refer to Figure 9H and Fig.9I The manufacturing method of the display panel of the present invention may include the step of forming a lower encapsulation inorganic pattern LIL covering the light emitting element ED. The step of forming the lower encapsulation inorganic pattern LIL may include: a step of depositing a lower encapsulation inorganic layer LIL-I; and a step of removing a portion of the lower encapsulation inorganic layer LIL-I that does not overlap with the light emitting element ED.

[0205] First, refer to Figure 9H , the step of forming the lower encapsulation inorganic pattern LIL may include the step of depositing the lower encapsulation inorganic layer LIL-I. The lower encapsulation inorganic layer LIL-I may be formed by a deposition process. In one embodiment, the lower encapsulation inorganic layer LIL-I may be formed by a chemical vapor deposition (CVD, Chemical Vapor Deposition) process. The lower encapsulation inorganic layer LIL-I may be formed to cover the partition wall opening OP-P and the partition wall PW.

[0206] Then, refer to Fig.9IThe step of forming the lower encapsulation inorganic pattern LIL may include: a step of forming a second photoresist layer PR2; and a step of removing a portion of the lower encapsulation inorganic layer LIL-I that does not overlap with the light emitting element ED.

[0207] In the step of forming the second photoresist layer PR2, the second photoresist layer PR2 can be formed in the following manner: after forming a preliminary photoresist layer, the preliminary photoresist layer is patterned using a photomask. Through the patterning process, the second photoresist layer PR2 can be formed into a pattern shape corresponding to the light emitting element ED.

[0208] In the step of removing the portion of the lower encapsulation inorganic layer LIL-I that does not overlap with the light-emitting element ED, the second photoresist layer PR2 can be used as a mask to perform dry etching on the lower encapsulation inorganic layer LIL-I, so as to pattern the portion of the lower encapsulation inorganic layer LIL-I that does not overlap with the light-emitting element ED (for example, the second and third light-emitting elements ED2, ED3 (see Figure 7 )). A lower encapsulation inorganic pattern LIL overlapping with the light emitting element ED may be formed from the patterned lower encapsulation inorganic layer LIL-I.

[0209] Then, refer to Figure 9J The manufacturing method of the display panel of the present invention may include removing the dummy layers D1 and D2 (refer to Figure 9G The second dummy layer D2 of the dummy layers D1 and D2 may be removed by wet etching, and the first dummy layer D1 of the dummy layers D1 and D2 may be removed by a splitter.

[0210] At this time, by removing the dummy layers D1 and D2, a dummy area DMA may be formed between the partition wall PW and the lower encapsulation inorganic pattern LIL. The height of the dummy area DMA may correspond to the thickness of the dummy layers D1 and D2, and the thickness of the dummy layers D1 and D2 may correspond to the thickness of the light emitting pattern EP and the cathode CE.

[0211] Then, refer to Figure 9K The manufacturing method of the display panel of the present invention may include: removing the second photoresist layer PR2 (refer to Figure 9J), an encapsulation organic film OL and an upper encapsulation inorganic film UIL are formed to complete the step of display panel DP. The encapsulation organic film OL can be formed by applying organic matter by inkjet method, but it is not limited to this. The encapsulation organic film OL provides a flattened upper surface. Subsequently, an upper encapsulation inorganic film UIL can be formed by depositing inorganic matter. Accordingly, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE can be formed.

[0212] Between the step of forming the lower encapsulation inorganic pattern LIL and the step of completing the display panel DP, the following steps may be performed: forming a partition wall opening and a light-emitting opening corresponding to the light-emitting area of ​​other colors on the partition wall PW and the pixel definition film PDL; forming a light-emitting element for providing other colors; and forming a lower encapsulation inorganic pattern covering the light-emitting element for providing other colors. Figure 7 The display panel DP shows a plurality of first to third light emitting elements ED1, ED2, ED3, first to third dummy areas DMA1, DMA2, DMA3, and first to third lower encapsulation inorganic patterns LIL1, LIL2, LIL3.

[0213] Although the above description is made with reference to the preferred embodiments of the present invention, it is understood by those skilled in the art or those of ordinary skill in the art that various modifications and changes may be made to the present invention without departing from the concept of the present invention and the technical scope of the present invention as described in the attached claims. Therefore, the technical scope of the present invention should not be limited to the contents described in the specific embodiments of the specification, but should be defined by the attached claims.

Claims

1. A display panel, in, include: Basal layer, The pixel definition film is disposed on the base layer and defines a light-emitting opening. a partition wall having a partition wall opening portion overlapping the light emitting opening portion and including a first partition wall layer disposed on the pixel definition film and a second partition wall layer disposed on the first partition wall layer, and A light emitting element, arranged in the partition wall opening, and comprising an anode, an intermediate layer, and a cathode in contact with the partition wall; The first partition wall layer includes an amorphous alloy.

2. The display panel according to claim 1, wherein: The first partition wall layer defines a first region of the partition wall opening, and the second partition wall layer defines a second region of the partition wall opening. The width of the first region in the first direction is greater than the width of the second region in the first direction.

3. The display panel according to claim 1, wherein: The first partition wall layer includes a first sub-layer disposed on the pixel definition film and a second sub-layer disposed on the first sub-layer. The second sub-layer includes an amorphous alloy.

4. The display panel according to claim 3, wherein: The inner side surface of the first sub-layer is aligned with the inner side surface of the second sub-layer.

5. The display panel according to claim 4, wherein: The cathode extends along the inner side surface of the first sub-layer and the inner side surface of the second sub-layer, and an end of the cathode contacts the second sub-layer.

6. The display panel according to claim 3, wherein: The thickness of the first sub-layer is Above and the following.

7. The display panel according to claim 3, wherein: The thickness of the second sub-layer is Above and the following.

8. The display panel according to claim 1, wherein: The thickness of the second partition wall layer is Above and the following.

9. The display panel according to claim 1, wherein: The amorphous alloy includes at least one of an amorphous molybdenum alloy and an amorphous tungsten alloy.

10. The display panel according to claim 1, wherein: It also includes a lower encapsulation inorganic pattern covering the light emitting element, A dummy region is defined between the partition wall and the lower encapsulation inorganic pattern.

11. The display panel according to claim 10, wherein: It also includes an encapsulation organic film disposed on the lower encapsulation inorganic pattern, A portion of the encapsulation organic film fills the dummy region.

12. A method for manufacturing a display panel, wherein: include: The step of providing a preliminary display panel, wherein the preliminary display panel comprises a base layer and a pixel definition film disposed on the base layer, forming a first preliminary partition wall layer including an amorphous alloy on the preliminary display panel, forming a second preliminary partition wall layer on the first preliminary partition wall layer, a step of etching the second preliminary partition wall layer to form a second partition wall layer defining a first opening, and a step of etching the first preliminary partition wall layer to form a first partition wall layer defining a second opening; A width of the first opening in the first direction is smaller than a width of the second opening in the first direction.

13. The method for manufacturing a display panel according to claim 12, wherein: The step of forming the first preliminary partition wall layer comprises: forming a first preliminary sub-layer on the pixel definition film; and The step of forming a second preliminary sub-layer on the first preliminary sub-layer.

14. The method for manufacturing a display panel according to claim 13, wherein: The step of forming the first preliminary sub-layer comprises: The conductive material to The step of depositing a thickness of 1000 nm is performed.

15. The method for manufacturing a display panel according to claim 13, wherein: The step of forming the second preliminary sub-layer comprises: The amorphous alloy to The step of depositing a thickness of 1000 nm is performed.

16. The method for manufacturing a display panel according to claim 13, wherein: The second preliminary sub-layer includes at least one of an amorphous molybdenum alloy and an amorphous tungsten alloy.

17. The method for manufacturing a display panel according to claim 13, wherein: The step of etching the first preliminary partition wall layer to form the first partition wall layer defining the second opening portion includes: a step of etching the second preliminary sub-layer to form a second sub-layer; and The step of etching the first preliminary sub-layer to form a first sub-layer.

18. The method for manufacturing a display panel according to claim 17, wherein: The inner side surface of the first sub-layer is aligned with the inner side surface of the second sub-layer.

19. The method for manufacturing a display panel according to claim 12, wherein: The step of forming the second preliminary partition wall layer includes: The conductive material to The step of depositing a thickness of 1000 nm is performed.

20. The method for manufacturing a display panel according to claim 12, wherein: Also includes: forming a light emitting element in the second opening; and The step of forming a lower encapsulation inorganic pattern covering the light emitting element.

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