EC-based sequential control method and industrial personal computer

Abstract

The invention relates to an EC-based sequential control method and an industrial personal computer. The method comprises the following steps of: performing startup time sequence control on the core processor based on the ARM architecture through the embedded controller; performing shutdown time sequence control on the core processor based on the ARM architecture through the embedded controller; performing sleep time sequence control on the core processor based on the ARM architecture through the embedded controller; and performing dormancy time sequence control on the core processor based on the ARM architecture through the embedded controller. At least it can be ensured that time sequence control of the industrial personal computer follows a peripheral time sequence specification, and the stability of the industrial personal computer and the core processor of the ARM architecture is ensured.

Description

Technical Field

[0001] The present application relates to the technical field of industrial computers, and in particular to an EC-based timing control method and an industrial computer. Background Art

[0002] Industrial computers are industrial control computers that have important computer properties and features, such as CPU, hard disk, memory, peripherals and interfaces, operating system, control network and protocol, computing power, etc. Industrial computers are intermediate products that provide safe, reliable and intelligent technical support for other industries and are important control equipment in the field of industrial automation.

[0003] However, due to the limitations of technical level and production process, the industrial control touch all-in-one computers on the market are mainly based on x86 architecture and embedded ARM chips. In some industrial control application fields, due to project security considerations, it is necessary to use the ARM platform. However, the current ARM platform, for example, the Feiteng Tenglong E2000Q platform itself does not have a matching timing control chip. Under normal circumstances, it can only control the power-on and power-off timing through hardware gate circuits and RC delays. Although it can be controlled based on FPGA, it has limitations, and there will be poor stability problems in some application scenarios. Summary of the invention

[0004] Based on this, it is necessary to provide a timing control method and industrial computer based on an embedded controller to address the above technical problems, which can at least control the timing of the core processor through the embedded controller, follow the peripheral timing specifications, and ensure the stability of the core processor of the industrial computer and the ARM architecture.

[0005] In the first aspect, the present application provides a timing control method based on an embedded controller, which is applied to an industrial computer, wherein the industrial computer includes a core processor based on an ARM architecture and an embedded controller, and the core processor based on the ARM architecture is connected to the embedded controller via an LPC bus; wherein the method includes: performing power-on timing control on the core processor based on the ARM architecture through the embedded controller; performing power-off timing control on the core processor based on the ARM architecture through the embedded controller; performing sleep timing control on the core processor based on the ARM architecture through the embedded controller; and performing hibernation timing control on the core processor based on the ARM architecture through the embedded controller.

[0006] In one of the embodiments, the step of controlling the power-on timing of the core processor based on the ARM architecture through the embedded controller includes: determining whether multiple input power supplies are normal according to a power-on signal; if the multiple input power supplies are all normal, controlling the embedded controller to execute the power-on action according to a pre-set power-on timing to power on the core processor based on the ARM architecture.

[0007] In one embodiment, the step of controlling the shutdown timing of the core processor based on the ARM architecture through the embedded controller includes: controlling the embedded controller to perform a shutdown action according to a shutdown signal and a preset shutdown timing to shut down the core processor based on the ARM architecture.

[0008] In one of the embodiments, according to a pre-set power-on timing, the step of controlling the embedded controller to perform a power-on action includes: controlling a buzzer pin to output a power-on target level; controlling multiple power output pins to output multiple power-on target voltages; controlling multiple reset pins to output multiple power-on target levels; and controlling a CPU reset pin to output a power-on target level.

[0009] In one embodiment, the step of controlling the embedded controller to perform a shutdown action includes: controlling a CPU reset pin to output a shutdown target level; controlling multiple reset pins to output multiple shutdown target levels; and controlling multiple power output pins to output multiple shutdown target voltages.

[0010] In one embodiment, the step of controlling the sleep timing of the ARM architecture-based core processor through the embedded controller includes: obtaining a flag value of a target storage address of the embedded controller; if the flag value is a preset target flag value, determining that the ARM architecture-based core processor is allowed to recover from a sleep state to a working state.

[0011] In one of the embodiments, the method further includes: if the flag value is a preset target flag value, determining that an abnormality exists in the core processor based on the ARM architecture, and controlling the core processor based on the ARM architecture to restart.

[0012] In one of the embodiments, the step of controlling the sleep timing of the core processor based on the ARM architecture through the embedded controller includes: controlling multiple device interfaces to output sleep levels to reset multiple devices; turning off the main power supply; turning off multiple CPU voltages to put the core processor based on the ARM architecture into a sleep state.

[0013] In one embodiment, the method further includes: maintaining multiple CPU voltages; and controlling multiple device interfaces to output wake-up levels to reset multiple devices.

[0014] In a second aspect, the present application further provides an industrial computer, comprising a core processor based on an ARM architecture and an embedded controller, wherein the core processor based on the ARM architecture is connected to the embedded controller via an LPC bus.

[0015] The EC-based timing control method and industrial computer, through the connection structure in which the core processor based on the ARM architecture is connected to the embedded controller through the LPC bus, controls the startup, shutdown, wake-up and other timings of the core processor based on the ARM architecture through the embedded controller, thereby ensuring that the timing control of the industrial computer follows the peripheral timing specifications and ensuring the stability of the industrial computer and the core processor of the ARM architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 is a flow chart of a timing control method based on EC in one embodiment;

[0018] Figure 2 A structural block diagram of an industrial computer in an embodiment;

[0019] Figure 3 It is a structural block diagram of an industrial computer in another embodiment.

[0020] Reference numerals and descriptions:

[0021] 101. Core processor; 102. Embedded controller; 301. PCIE; 302. HDA; 303. LAN; 304. HDMI; 305. LVDS; 306. VGA; 307. GPIO; 308. DDR4; 309. M.2 WIFI&BT; 310. M.2 SSD; 311. SATA; 312. USB2.0; 313. USB3.0; 314. SPI; 315. FAN CONN; 316. COM. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0023] Please refer to Figure 1 In an exemplary embodiment, a timing control method based on EC is provided, comprising the following steps S101 to S104. Wherein:

[0024] Step S101 , controlling the startup timing of the core processor 101 based on the ARM architecture through the embedded controller 102 .

[0025] It should be noted that, in the industrial computer, the industrial computer includes a core processor 101 based on the ARM architecture and an embedded controller 102 , and the core processor 101 based on the ARM architecture is connected to the embedded controller 102 via an LPC bus.

[0026] As an example, see Figure 2 In an exemplary embodiment, a structural block diagram of an industrial computer is provided, including: a core processor 101 and an embedded controller 102.

[0027] Specifically, the core processor 101 may be a core processor 101 based on an ARM architecture, and the core processor 101 is connected to the embedded controller 102 via an LPC bus.

[0028] Here, the LPC bus (Low Pin Count Bus), as a low-pin-count, high-speed computer bus, plays an important role in connecting low-bandwidth devices and industrial computer devices.

[0029] As an example, see Figure 3 In an exemplary embodiment, an industrial computer is provided, including: a core processor 101 and an embedded controller 102, PCIE301, HDA302, LAN303, HDMI304, LVDS305, VGA306, GPIO307, DDR4308, M.2 WIFI&BT, M.2 SSD, SATA311, USB2.0312, USB3.0313, SPI314, FANCONN, and COM316.

[0030] like Figure 3 As shown in the figure, PCIE301, HDA302, LAN303, HDMI304, LVDS305, VGA306, GPIO307, DDR4308, M.2 WIFI&BT, M.2 SSD, SATA311, USB2.0312, and USB3.0313 interfaces are respectively connected to the core controller, and SPI314, FAN CONN, and COM316 interfaces are respectively connected to the embedded controller 102.

[0031] In this way, multiple display output supports are provided through the setting of multiple interfaces, and multiple serial port communications are supported, which has strong applicability and high scalability.

[0032] Here, it should be noted that this application does not limit the number. The number of interfaces such as PCIE301, HDA302, LAN303, HDMI304, LVDS305, VGA306, GPIO307, DDR4308, M.2 WIFI&BT, M.2 SSD, SATA311, USB2.0312, USB3.0313, SPI314, FAN CONN, COM316, etc. can be matched by technical personnel in this field.

[0033] In a possible embodiment, PCIE301 can be two PCIE301 Slot interfaces, the model of HAD can be ALC897 CODEC / CX20632, LAN303 can be two RJ45LAN303 with model YT8521, HDMI304 can be connected to the core controller through the CS5211 adapter interface, VGA306 can be connected to the core controller through the CS5212 adapter interface, 8 GPIO307 can be set, and each GPIO307 interface is connected to the core controller respectively, USB2.0312 can be eight USB2.0312 interfaces, and each USB2.0312 is connected to the core controller through a USB2.0312 Hub adapter unit, USB3.0313 can be two USB3.0313 interfaces, and each USB3.0313 is connected to the core controller through a μPD720202 adapter unit, COM316 can be six COM316 interfaces connected to the embedded controller 102, and SPI314 can be SPI314Flash. The ROM is connected to the embedded controller 102 .

[0034] Specifically, the step of controlling the power-on timing of the core processor 101 based on the ARM architecture through the embedded controller 102 includes: determining whether multiple input power supplies are normal according to a power-on signal; if the multiple input power supplies are normal, controlling the embedded controller 102 to perform the power-on action according to a pre-set power-on timing, so that the core processor 101 based on the ARM architecture is powered on.

[0035] As an example, the core processor 101 based on the ARM architecture can be a Feiteng Tenglong E2000Q processor, which communicates with an embedded controller 102 of model LS1011EID through the LPC bus. The LS1011EID can control the startup timing, shutdown timing, sleep timing and hibernation timing of the E2000Q.

[0036] Specifically, according to the pre-set power-on timing, the steps of controlling the embedded controller 102 to perform the power-on action include: controlling the buzzer pin to output a power-on target level; controlling multiple power output pins to output multiple power-on target voltages; controlling multiple reset pins to output multiple power-on target levels; and controlling the CPU reset pin to output a power-on target level.

[0037] As an example, taking the Feiteng E2000Q processor and the embedded controller 102 of model LS1011EID as an example, the embedded controller 102 can receive key input through the GPB11 / 32K_OUT pin. After the key is pressed, a high level is detected to trigger the power on; the GPB03 pin is used to detect whether the 3.3V and 5V power supplies are stable. When a high level is detected, it indicates that the power supply is normal; after setting a delay of 10ms and 20ms, the GPE16 pin controls the buzzer output, outputting high and low levels respectively, for outputting prompt sound effects; based on different pins (such as GPE07, GPA03, etc.), the power supply channels of different CPU voltages are controlled, such as EC_P0V8_EN and EC_P1V8_EN control 0.8V and 1.8V voltages; multiple pins are controlled to output reset levels, such as EC_LVDS305_RST_EN (pin 123) for LVDS305 reset control, and CPU_Reset_N (pin 85) for CPU reset. In this way, the correctness of the power-on and reset processes is ensured by controlling the delay time and the order of signal output.

[0038] Step S102 , performing shutdown timing control on the ARM architecture-based core processor 101 through the embedded controller 102 .

[0039] Specifically, the step of controlling the shutdown timing of the ARM architecture-based core processor 101 through the embedded controller 102 includes: controlling the embedded controller 102 to perform a shutdown action according to a shutdown signal and a preset shutdown timing to shut down the ARM architecture-based core processor 101.

[0040] The step of controlling the embedded controller 102 to perform a shutdown action includes: controlling a CPU reset pin to output a shutdown target level; controlling multiple reset pins to output multiple shutdown target levels; and controlling multiple power output pins to output multiple shutdown target voltages.

[0041] Here, the shutdown sequence is opposite to the startup sequence, and the specific control content of the shutdown sequence will not be repeated here.

[0042] Step S103 , controlling the sleep timing of the ARM architecture-based core processor 101 through the embedded controller 102 .

[0043] As an example, the steps of performing sleep timing control on the ARM architecture-based core processor 101 through the embedded controller 102 include: obtaining the flag value of the target storage address of the embedded controller 102; if the flag value is a preset target flag value, determining that the ARM architecture-based core processor 101 is allowed to recover from the sleep state to the working state.

[0044] The method further includes: if the flag value is a preset target flag value, determining that an abnormality exists in the core processor 101 based on the ARM architecture, and controlling the core processor 101 based on the ARM architecture to restart.

[0045] Here, taking the Feiteng E2000Q processor as an example, when the core processor 101 recovers from sleep state to working state, the EC (embedded controller 102) writes the flag indicating whether it wakes up normally to the space at address 0x08 in EC-RAM (hereinafter referred to as EC-0B) in advance. For detailed operations, please refer to the overview of the Feiteng Platform EC Interface Specification. When EC-0B is 0x55 or 0xAA, it means that it can recover to S0 normally. When EC-0B is other values, it is known that the CPU motherboard is in an abnormal state (memory power failure, etc.), and the system will restart instead of recovering from sleep state.

[0046] As an example, the steps of performing sleep timing control on the ARM architecture-based core processor 101 through the embedded controller 102 include: controlling multiple device interfaces to output sleep levels to reset multiple devices; turning off the main power supply; turning off multiple CPU voltages to put the ARM architecture-based core processor 101 into a sleep state.

[0047] As an example, taking the Feiteng Tenglong E2000Q processor and the embedded controller 102 of model LS1011EID as an example, the PCIE301_RST reset output can be controlled first, the pin is GPE02 / SPI314S_MOSI, the signal name is PCIE301_RST_N, and it can output a low level to turn off the PCIe device reset; then control the EC_M2_X16_RST_N reset output, the pin is GPA07, the signal name is EC_M2_X16_RST_N, it can output a low level to reset the M.2 expansion device; then control the 720202_RST_N reset output, the pin is GPG05, the signal name is 720202_RST_N, it can output a low level to reset the specified device (which can be a peripheral device); then control EC_LVDS305_ RST_EN reset output, pin is GPC09, signal name is EC_LVDS305_RST_EN, can output low level, reset LVDS305 interface (for display device); then control EC_PHY_Reset reset output, pin is GPB04, signal name is EC_PHY_Reset, can output low level, reset PHY module (network interface); then control EC_LT8711HE_RST_N reset output, pin is GPC02, signal name is EC_LT8711HE_RST_N, can output low level, reset LT8711HE module (may be used for display or other devices); then control PWR_S3 power signal output, pin is GPE04, signal name is PWR_S3, can output low level, cut off 3.3V / 5V power supply; then control the VDD_IO_EN (CPU1.8V) output, the pin is GPA02, the signal name is EC_P1V8_EN, it can output a low level to turn off the CPU's I / O voltage power supply; then control the EC_P0V8_EN (CPU 0.8V) output, the pin is GPA03, the signal name is EC_P0V8_EN, it can output a low level to turn off the CPU core voltage power supply; then control the EC_CORE_EN (CPU 0.8V) output, the pin is GPE07, the signal name is EC_CORE_EN, it can output a low level to turn off the CPU power control signal.

[0048] In this way, the Feiteng Tenglong E2000Q processor completes the reset signal output through the control of the embedded controller 102, shuts down the device, ensures safe entry into the sleep mode, and shuts down the power in sequence from the periphery to the core circuit to avoid sudden power outages that cause data loss or equipment damage, and controls the stability of the entire system through phased actions.

[0049] In one of the embodiments, the method further includes: maintaining multiple CPU voltages; and controlling multiple device interfaces to output wake-up levels to reset multiple devices.

[0050] As an example, the signal startup sequence in the wake-up phase includes: T1, CPU_Reset_N (CPU reset signal), the signal is CPU_Reset_N (GPEA09 pin), to ensure that the CPU is initialized and reset, and the specific action is to pull down the reset signal to prepare to wake up the CPU; T2, EC_CORE_EN (CPU core voltage start), the signal is EC_CORE_EN (GPE07 pin), to start the CPU's core power supply circuit (such as 0.8V core voltage), the specific action is to output a high level; T3: EC_P0V8_EN (CPU 0.8V voltage start), the signal is EC_P0V8_EN` (GPA03 pin), to start 0.8V power supply, to provide power to the key modules of the CPU; T4: VDD_IO_EN (CPU 1.8V IO voltage start), the signal is VDD_IO_EN (GPA02 pin), to turn on the CPU IO power supply, activate the peripheral interface module; T5: PWR_S3 (3.3V / 5V voltage on), the signal is PWR_S3 (GPE04 pin) to activate the S3 power supply (3.3V and 5V); T6: EC_PHY_Reset, the signal is EC_PHY_Reset (GPB04 pin) to initialize the network PHY module; T7: EC_LVDS305_RST_EN, the signal is EC_LVDS305_RST_EN (GPC09 pin) to reset the LVDS305 display interface; T8: 720202_RST_N, the signal is 720202_RST_N (GPG05 pin) to reset a specific peripheral module; T9: EC_M2_X16_RST_N, the signal is EC_M 2_X16_RST_N` (GPA07 pin) to reset the M.2 module or PCIe device; T10: EC_LT8711HE_RST_N, the signal is EC_LT8711HE_RST_N` (GPC02 pin) to reset the LT8711HE device (HDMI304 / video interface controller); the signal is PCIE301_RST_N (GPE02 pin) to reset the PCIe device; T12: The signal is EC_S3_OK (GPA05 pin), which notifies the system through the signal that the recovery operation of the S3 state has been completed; T13: Confirm the CPU reset again, the signal is CPU_Reset_N (GPEA09 pin), recheck and pull up the CPU reset signal to ensure that the CPU wakes up from reset.

[0051] Here, first start the CPU core power signal (EC_CORE_EN and EC_P0V8_EN) to ensure that the core module can start working, then activate the IO interface and peripheral modules (`VDD_IO_EN` and PWR_S3) to power the peripherals, and finally gradually reset the peripheral modules and notify the system to complete the wake-up (EC_S3_OK).

[0052] In this way, it can ensure that each step is executed in a strict timing sequence to prevent power / signal conflicts. Each module must be powered and reset before proceeding to the next step.

[0053] Step S104 , performing sleep timing control on the ARM architecture-based core processor 101 through the embedded controller 102 .

[0054] As an example, taking the Feiteng Tenglong E2000Q processor and the embedded controller 102 with model LS1011EID as an example, it is necessary to first disconnect non-essential power signals (such as PLL, VDD, USB and other power supplies); then pull down the reset signal, such as the reset signal PCIE301_RST of the PCIe device, the power-on reset signal POR_N of the CPU, etc., and then maintain the core power supply, and retain the necessary S3_OK signal in the sleep state, indicating that the CPU part has entered the sleep state.

[0055] In this way, when the embedded controller 102 (EC) receives the information, it only needs to maintain the DDR / USB / RGMII_PHY related power supply and complete the power-off, reset signal and other operations in sequence according to the pre-set timing, so as to realize the wake-up of the CPU, reduce the system power consumption, and retain the power supply of key modules by turning off the peripheral devices first, gradually reducing the core power supply, and finally maintaining the sleep state, and strictly performing the reset and power-off operations according to the steps to ensure the stability of the system.

[0056] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0057] Based on the same inventive concept, the embodiment of the present application also provides an industrial computer. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in the embodiments of one or more industrial computers provided below can refer to the limitations of the EC-based timing control method above, and will not be repeated here.

[0058] Please refer to Figure 2 In an exemplary embodiment, an industrial computer is provided, including: a core processor 101 and an embedded controller 102, wherein the core processor 101 based on the ARM architecture is connected to the embedded controller 102 via an LPC bus.

[0059] The core processor 101 is a core processor 101 based on the ARM architecture.

[0060] As an example, see Figure 3 In an exemplary embodiment, an industrial computer is provided, including: a core processor 101 and an embedded controller 102, PCIE301, HDA302, LAN303, HDMI304, LVDS305, VGA306, GPIO307, DDR4308, M.2 WIFI&BT, M.2 SSD, SATA311, USB2.0312, USB3.0313, SPI314, FANCONN, and COM316.

[0061] like Figure 3 As shown in the figure, PCIE301, HDA302, LAN303, HDMI304, LVDS305, VGA306, GPIO307, DDR4308, M.2 WIFI&BT309, M.2 SSD310, SATA311, USB2.0312, and USB3.0313 interfaces are respectively connected to the core controller, and SPI314, FAN CONN315, and COM316 interfaces are respectively connected to the embedded controller 102.

[0062] In this way, multiple display output supports are provided through the setting of multiple interfaces, and multiple serial port communications are supported, which has strong applicability and high scalability.

[0063] Here, it should be noted that this application does not limit the number. The number of interfaces such as PCIE301, HDA302, LAN303, HDMI304, LVDS305, VGA306, GPIO307, DDR4308, M.2 WIFI&BT, M.2 SSD, SATA311, USB2.0312, USB3.0313, SPI314, FAN CONN, COM316, etc. can be matched by technical personnel in this field.

[0064] In a possible embodiment, PCIE301 can be two PCIE301 Slot interfaces, the model of HAD can be ALC897 CODEC / CX20632, LAN303 can be two RJ45LAN303 with model YT8521, HDMI304 can be connected to the core controller through the CS5211 adapter interface, VGA306 can be connected to the core controller through the CS5212 adapter interface, 8 GPIO307 can be set, and each GPIO307 interface is connected to the core controller respectively, USB2.0312 can be eight USB2.0312 interfaces, and each USB2.0312 is connected to the core controller through a USB2.0312 Hub adapter unit, USB3.0313 can be two USB3.0313 interfaces, and each USB3.0313 is connected to the core controller through a μPD720202 adapter unit, COM316 can be six COM316 interfaces connected to the embedded controller 102, and SPI314 can be SPI314Flash. ROM is connected to the embedded controller 102. Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM may be in various forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. The non-relational database may include a distributed database based on blockchain, etc., but is not limited thereto. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but is not limited thereto.

[0065] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0066] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A timing control method based on EC, characterized in that: Applied to an industrial computer, the industrial computer comprises a core processor based on ARM architecture and an embedded controller, the core processor based on ARM architecture and the embedded controller are connected via an LPC bus; Wherein, the method comprises: Performing power-on timing control on the core processor based on the ARM architecture through the embedded controller; Performing shutdown timing control on the core processor based on the ARM architecture through the embedded controller; Performing sleep timing control on the core processor based on the ARM architecture by means of the embedded controller; The embedded controller controls the sleep timing of the core processor based on the ARM architecture.

2. The method according to claim 1, characterized in that The step of controlling the startup timing of the core processor based on the ARM architecture by the embedded controller comprises: According to the power-on signal, determine whether multiple input power supplies are normal; If the multiple input power supplies are all normal, the embedded controller is controlled to execute a power-on action according to a preset power-on sequence, so that the core processor based on the ARM architecture is powered on.

3. The method according to claim 1, characterized in that: The step of controlling the shutdown timing of the core processor based on the ARM architecture by the embedded controller comprises: According to the shutdown signal and the preset shutdown sequence, the embedded controller is controlled to execute the shutdown action, so that the core processor based on the ARM architecture is shut down.

4. The method according to claim 2, characterized in that: According to a preset power-on sequence, the step of controlling the embedded controller to execute a power-on action comprises: Control the buzzer pin to output the power-on target level; Control multiple power output pins to output multiple power-on target voltages; Control multiple reset pins to output multiple power-on target levels; Control the CPU reset pin to output the power-on target level.

5. The method according to claim 3, characterized in that: The step of controlling the embedded controller to execute a shutdown action comprises: Control the CPU reset pin to output the shutdown target level; Control multiple reset pins to output multiple shutdown target levels; Control multiple power output pins to output multiple shutdown target voltages.

6. The method according to claim 1, characterized in that The step of controlling the sleep timing of the core processor based on the ARM architecture by the embedded controller comprises: Get the flag value of the embedded controller target storage address; If the flag value is a preset target flag value, it is determined that the ARM architecture-based core processor is allowed to recover from the sleep state to the working state.

7. The method according to claim 6, characterized in that The method further comprises: If the flag value is a preset target flag value, it is determined that an abnormality exists in the core processor based on the ARM architecture, and the core processor based on the ARM architecture is controlled to restart.

8. The method according to claim 1, characterized in that The step of controlling the sleep timing of the core processor based on the ARM architecture by the embedded controller comprises: Control multiple device interfaces to output sleep levels, and reset multiple devices; Turn off the main power supply; Multiple CPU voltages are turned off to put the core processor based on the ARM architecture into a sleep state.

9. The method according to claim 1, characterized in that: The method further comprises: Maintain multiple CPU voltages; Control multiple device interfaces to output wake-up levels to reset multiple devices.

10. An industrial computer, characterized in that: The industrial computer comprises a core processor based on an ARM architecture and an embedded controller, and the core processor based on the ARM architecture is connected to the embedded controller via an LPC bus.

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