CPU multi-core-based core TCM structure, core TCM control method and chip

Abstract

The invention discloses a core TCM structure based on multiple cores of a CPU, a core TCM control method and a chip. The core TCM structure is arranged in the CPU core, the CPU comprises N CPU cores arranged according to a first sequence, N is an integer greater than 1, the N CPU cores comprise a first CPU core and a second CPU core, the first CPU core is the ith CPU core in the N CPU cores, the second CPU core is the (i + 1) th CPU core in the N CPU cores, and i = 1, 2... N; wherein the first core TCM is connected with the first core pipe, and is arranged in the first CPU core; the second core pipe is connected with the input end of the selector, and the second core TCM is connected with the output end of the selector and is arranged in the second CPU core; the first core pipe is connected with the selector input end in the second CPU core to access the second core TCM; and the selector selects the first core pipe and the second core pipe to respectively control the first core TCM and the second core TCM according to the split-lock working mode of the CPU by receiving the pulling-up or pulling-down condition of an external control signal. According to the application, the situation of circuit resource waste of the CPU can be reduced, and the resource utilization rate is improved.

Description

Technical Field

[0001] The present application relates to the field of computing architecture technology, for example, to a core TCM structure based on CPU multi-core, a core TCM control method and a chip. Background Art

[0002] At present, the CPU (Central Processing Unit) is the core component of the chip's logical computing system and is responsible for executing instructions in the program.

[0003] In related technologies, a CPU usually integrates multiple independent CPU cores, which can process tasks in parallel to improve the performance and efficiency of the chip's logical computing system. Each CPU core is independently deployed with a tightly coupled memory (TCM) for caching and storing data. Among them, the CPU's split-lock mode can regulate the working status of different CPU cores to meet functional safety requirements.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] When the CPU works in lock mode, the tightly coupled memories of some CPU cores are in a static idle state, resulting in a waste of circuit resources and insufficient CPU resource utilization.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a core TCM structure, a core TCM control method and a chip based on CPU multi-core, which can reduce the waste of CPU circuit resources and improve the resource utilization of the CPU.

[0009] In some embodiments, a core TCM structure based on CPU multi-core is built into a CPU core, the CPU includes N CPU cores arranged in a first order, N is an integer greater than 1, the N CPU cores include a first CPU core and a second CPU core, the first CPU core is the i-th CPU core among the N CPU cores, the second CPU core is the i+1-th CPU core among the N CPU cores, i=1, 2...N; wherein, the first core TCM is connected to the first core pipeline and is built into the first CPU core; the second core pipeline is connected to the selector input end, the second core TCM is connected to the selector output end, and is built into the second CPU core; the first core pipeline accesses the second core TCM by connecting to the selector input end in the second CPU core; the selector receives an external control signal and is pulled high or low, and selects the first core pipeline and the second core pipeline to control the first core TCM and the second core TCM respectively according to the split-lock working mode of the CPU.

[0010] Optionally, the first CPU core sets a first TCM interface, the first core TCM includes multiple first sub-core TCMs, the multiple first sub-core TCMs are connected to the first TCM interface, and the first core pipeline is connected to the multiple first sub-core TCMs through the first TCM interface.

[0011] Optionally, the second CPU core sets a second TCM interface, the second core TCM includes multiple second sub-core TCMs, and the multiple second sub-core TCMs are connected to the second TCM interface; the multiple first sub-core TCMs correspond one-to-one to the multiple second sub-core TCMs; the second core pipeline is connected to the multiple second sub-core TCMs through the second TCM interface.

[0012] Optionally, the first CPU core further includes: a first data cache and a first instruction cache; the first data cache and the first instruction cache are respectively connected to the first core pipeline.

[0013] Optionally, the second CPU core further includes: a second data cache and a second instruction cache; the second data cache and the second instruction cache are respectively connected to the second core pipeline.

[0014] Optionally, the first core pipeline and the second core pipeline are connected to address buses respectively.

[0015] In some embodiments, a core TCM control method based on CPU multi-core is applied to a chip such as one provided with the above-mentioned core TCM structure, and the method includes: when the chip is configured in split-lock mode, the selector of the CPU core receives an external control signal; according to whether the external control signal is pulled high or low, the selector selects the first core pipeline and the second core pipeline to control the first core TCM and the second core TCM respectively; the address bus connects the first core pipeline and the second core pipeline respectively, and accesses the first core TCM and the second core TCM through the TCM interface.

[0016] Optionally, when the external control signal is pulled high, the CPU operates in split mode, and the selector selects the second core pipeline as the control signal of the second CPU core; when the external control signal is pulled low, the CPU operates in lock mode, and the selector selects the first core pipeline as the control signal of the second CPU core.

[0017] Optionally, the CPU operates in a lock mode, including: a clock of a second core TCM of the second CPU core is in an on state, so that the first CPU core normally uses the second core TCM of the second CPU core.

[0018] Optionally, the CPU operates in lock mode, further comprising: when the address bus is a low-order address, the first CPU core uses a first-core TCM; when the address bus is a high-order address, the first CPU core uses a second-core TCM.

[0019] Optionally, when the address bus is a high-order address, a chip select signal of a first core TCM in the first CPU core is disabled.

[0020] In some embodiments, a chip includes: a first CPU core and a second CPU core; the core TCM structure as described above is deployed in the first CPU core and the second CPU core.

[0021] The core TCM structure based on CPU multi-core, the core TCM control method and the chip provided by the embodiments of the present disclosure can achieve the following technical effects:

[0022] In the embodiment of the present disclosure, for a multi-core CPU, a core TCM structure is constructed, and the N CPU cores in the CPU are arranged in a first order, including a first CPU core and a second CPU core. The first core TCM is connected to the first core pipeline and is built into the first CPU core. The second core pipeline is connected to the selector input end, and the second core TCM is connected to the selector output end, and is built into the second CPU core; the first core pipeline accesses the second core TCM by connecting to the selector input end in the second CPU core. Among them, the selector selects the first core pipeline and the second core pipeline to control the first core TCM and the second core TCM respectively by receiving the external control signal to be pulled high or low. In this way, when the second core TCM of the second CPU core is in a static idle state, the selector can enable the first core pipeline to access the second core TCM according to the external control signal. Therefore, the embodiment of the present disclosure can reduce the waste of CPU circuit resources and improve the resource utilization of the CPU.

[0023] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0025] Figure 1 is a schematic diagram of a core TCM structure based on CPU multi-core provided by an embodiment of the present disclosure;

[0026] Figure 2 is a schematic diagram of another core TCM structure based on CPU multi-core provided by an embodiment of the present disclosure;

[0027] Figure 3 is a schematic diagram of another core TCM structure based on CPU multi-core provided by an embodiment of the present disclosure;

[0028] Figure 4 is a schematic diagram of another core TCM structure based on CPU multi-core provided by an embodiment of the present disclosure;

[0029] Figure 5 is a schematic diagram of a core TCM control method based on CPU multi-cores provided by an embodiment of the present disclosure;

[0030] Figure 6 It is a schematic diagram of a chip provided by an embodiment of the present disclosure.

[0031] Description of reference numerals:

[0032] 10. Core TCM structure based on CPU multi-core;

[0033] 100, first CPU core; 110, first core pipeline; 120, first core TCM; 121, first sub-core TCM; 130, first TCM interface; 140, first data buffer; 150, first instruction buffer;

[0034] 200, second CPU core; 210, second core pipeline; 220, selector; 230, second core TCM; 231, second sub-core TCM; 240, second TCM interface; 250, second data buffer; 260, second instruction buffer;

[0035] 600. Chip. DETAILED DESCRIPTION

[0036] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0037] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so that the embodiments of the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0038] Unless otherwise stated, the term "plurality" of a feature means two or more.

[0039] In the embodiment of the present disclosure, the character " / " feature indicates that the preceding and following objects are in an "or" relationship. For example, the A / B feature indicates: A or B.

[0040] The term "and / or" is a description of the association relationship between objects, and the characteristic indicates that there can be three relationships. For example, A and / or B, the characteristic indicates: A or B, or, A and B.

[0041] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0042] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other.

[0043] The core TCM structure 10 based on CPU multi-core provided by the embodiment of the present disclosure is as follows: Figure 1 As shown, the core TCM structure 10 is built into the CPU core, the CPU includes N CPU cores arranged in a first order, N is an integer greater than 1, the N CPU cores include a first CPU core 100 and a second CPU core 200, the first CPU core 100 is the i-th CPU core among the N CPU cores, the second CPU core 200 is the i+1-th CPU core among the N CPU cores, i=1, 2...N; wherein the first core TCM 120 is connected to the first core pipeline 110 and is built into the first CPU core 100; the second core pipeline 210 is connected to the selected The first core pipeline 110 is connected to the input end of the selector 200, and the second core TCM 230 is connected to the output end of the selector 200 and is built into the second CPU core 200; the first core pipeline 110 accesses the second core TCM 230 by connecting to the input end of the selector 200 in the second CPU core 200; the selector 200 controls the split-lock working mode of the CPU by receiving the external control signal pulled high or low, and selects the first core pipeline 110 and the second core pipeline 210 to control the first core TCM 120 and the second core TCM 230 respectively.

[0044] Specifically, Figure 1 CFGSPLIT is the input terminal of the external control signal.

[0045] Specifically, the first CPU core 100 is the i-th CPU core among the N CPU cores in the CPU. It is usually responsible for the main computing and control tasks in the CPU. In a CPU with multiple CPU cores, the number of the first CPU cores 100 can be one or more, and the first CPU core 100 undertakes most of the computing and processing work. Among them, the first CPU core 100 needs to have a higher main frequency and stronger computing power to ensure that the CPU can efficiently handle various complex tasks.

[0046] Specifically, the second CPU core 200 is the i+1th CPU core among the N CPU cores in the CPU. The second CPU core 200 is used to assist the first CPU core 100 in completing computing tasks, or to undertake part of the computing work under certain circumstances. Among them, the second CPU core 200 needs to have similar performance to the first CPU core 100, but its main frequency, cache size and other functions are reduced.

[0047] Specifically, by setting the selector 200 in the second CPU core 200, the first core pipeline 110 and the second core pipeline 210 are both connected to the input end of the selector 200, and the second core TCM 230 is connected to the output end of the selector 200. The selector 200 can control the split-lock working mode of the CPU by receiving an external control signal, and select the first core pipeline 110 and the second core pipeline 210 to respectively control the first core TCM 120 and the second core TCM 230. In this way, the first CPU core 100 can access the second core TCM 230 through the first core pipeline 110.

[0048] In the embodiment of the present disclosure, for a multi-core CPU, a core TCM structure 10 is constructed, and the N CPU cores in the CPU are arranged in a first order, including a first CPU core 100 and a second CPU core 200. The first core TCM 120 is connected to the first core pipeline 110 and is built into the first CPU core 100. The second core pipeline 210 is connected to the input end of the selector 200, and the second core TCM 230 is connected to the output end of the selector 200 and is built into the second CPU core 200; the first core pipeline 110 accesses the second core TCM 230 by connecting to the input end of the selector 200 in the second CPU core 200. Among them, the selector 200 selects the first core pipeline 110 and the second core pipeline 210 to control the first core TCM 120 and the second core TCM 230 respectively by receiving the external control signal to be pulled high or low. Thus, when the second core TCM 230 of the second CPU core 200 is in a static idle state, the selector 200 can enable the first core pipeline 110 to access the second core TCM 230 according to an external control signal. Therefore, the disclosed embodiment can reduce the waste of CPU circuit resources and improve CPU resource utilization.

[0049] like Figure 2 As shown, the first CPU core 100 is provided with a first TCM interface 130 , the first core TCM 120 includes a plurality of first sub-core TCMs 121 , the plurality of first sub-core TCMs 121 are connected to the first TCM interface 130 , and the first core pipeline 110 is connected to the plurality of first sub-core TCMs 121 through the first TCM interface 130 .

[0050] Specifically, in order to facilitate data processing, the storage space in the first core TCM120 is divided into multiple storage areas, each storage area is used to process a type of data, and each storage area is a first sub-core TCM121. Figure 2 TCMA, TCMB and TCMC in the first CPU core 100 represent the first sub-core TCM121.

[0051] Specifically, a first TCM interface 130 is provided in the first CPU core 100 , and the plurality of first sub-core TCMs 121 are connected to the first core pipeline 110 through the first TCM interface 130 , so that the first core pipeline 110 can control the plurality of first sub-core TCMs 121 separately.

[0052] like Figure 2 As shown, the second CPU core 200 is provided with a second TCM interface 240, the second core TCM230 includes multiple second sub-cores TCM231, and the multiple second sub-cores TCM231 are connected to the second TCM interface 240; the multiple first sub-cores TCM121 correspond one to one with the multiple second sub-cores TCM231; the second core pipeline210 is connected to the multiple second sub-cores TCM231 through the second TCM interface 240.

[0053] Specifically, in order to facilitate data processing, the storage space in the second core TCM230 is divided into multiple storage areas, each storage area is used to process a type of data, and each storage area is a second sub-core TCM231. Figure 2 TCMA, TCMB and TCMC in the second CPU core 200 represent the second sub-core TCM231.

[0054] Specifically, since the second core TCM 230 needs to be used by the first CPU core 100 , the plurality of second sub-cores TCM 231 need to correspond one-to-one to the plurality of first sub-cores TCM 121 .

[0055] Specifically, a second TCM interface 240 is provided in the second CPU core 200 , and the plurality of second sub-core TCMs 231 are connected to the second core pipeline 210 via the second TCM interface 240 , so that the second core pipeline 210 can control the plurality of second sub-core TCMs 231 separately.

[0056] It should be noted that the second core pipeline 210 is connected to the second TCM interface 240 through the output end of the selector 200 .

[0057] like Figure 3 As shown, the first CPU core 100 further includes: a first data buffer 140 and a first instruction buffer 150. The first data buffer 140 and the first instruction buffer 150 are connected to the first core pipeline 110 respectively.

[0058] Specifically, by setting a first data buffer 140 connected to the first core pipeline 110 in the first CPU core 100, the number of times the first core pipeline 110 accesses the first core TCM 120 can be effectively reduced. Specifically, the access frequency of the first core pipeline 110 is relatively high, while the access speed of the first core TCM 120 is relatively slow. By setting a first data buffer 140 electrically connected to the first core pipeline 110 and storing frequently used data, the number of times the first core pipeline 110 directly accesses the first core TCM 120 can be significantly reduced, and the performance of the first CPU core 100 in processing data can be improved. In addition, since the operation speed of the first core pipeline 110 is much higher than the read and write speed of the first core TCM 120, this will cause the first core pipeline 110 to spend a long time waiting for data to arrive or writing data to the first core TCM 120. The presence of the first data buffer 140 can alleviate this speed difference, allowing the first CPU core 100 to work more efficiently.

[0059] Specifically, by setting a first instruction cache 150 connected to the first core pipeline 110 in the first CPU core 100, the access speed of instructions can be effectively improved. Specifically, the first instruction cache 150 is used to cache the instructions to be executed sent to the first core pipeline 110. When the first CPU core 100 needs to execute an instruction, it will first search in the first instruction cache 150. If the required instructions are already in the first instruction cache 150, the first core pipeline 110 can quickly obtain these instructions and execute them, thereby avoiding the delay of reading instructions from a memory with a slower access speed.

[0060] In the disclosed embodiment, by setting a data cache and an instruction cache in the first CPU core 100, the number of times the first core pipeline 110 accesses the first core TCM 120 can be effectively reduced, the access speed of instructions can be effectively improved, and the working efficiency of the first CPU core 100 can be improved.

[0061] like Figure 3 As shown, the second CPU core 200 further includes: the second CPU core 200 further includes: a second data buffer 250 and a second instruction buffer 260. The second data buffer 250 and the second instruction buffer 260 are connected to the second core pipeline 210 respectively.

[0062] Specifically, by setting a second data buffer 250 connected to the second core pipeline 210 in the second CPU core 200, the number of times the second core pipeline 210 accesses the second core TCM 230 can be effectively reduced. Specifically, the access frequency of the second core pipeline 210 is relatively high, while the access speed of the second core TCM 230 is relatively slow. By setting a second data buffer 250 electrically connected to the second core pipeline 210 and storing frequently used data, the number of times the second core pipeline 210 directly accesses the second core TCM 230 can be significantly reduced, and the performance of the second CPU core 200 in processing data can be improved. In addition, since the operation speed of the second core pipeline 210 is much higher than the read and write speed of the second core TCM 230, this will cause the second core pipeline 210 to spend a long time waiting for data to arrive or writing data to the second core TCM 230. The presence of the second data buffer 250 can alleviate this speed difference, allowing the second CPU core 200 to work more efficiently.

[0063] Specifically, by setting a second instruction cache 260 connected to the second core pipeline 210 in the second CPU core 200, the access speed of the instruction can be effectively improved. Specifically, the second instruction cache 260 is used to cache the instructions to be executed sent to the second core pipeline 210. When the second CPU core 200 needs to execute an instruction, it will first search in the second instruction cache 260. If the required instructions are already in the second instruction cache 260, the second core pipeline 210 can quickly obtain these instructions and execute them, thereby avoiding the delay of reading instructions from the memory with a slower access speed.

[0064] In the disclosed embodiment, by setting a data cache and an instruction cache in the second CPU core 200, the number of times the second core pipeline 210 accesses the second core TCM 230 can be effectively reduced, the access speed of instructions can be effectively improved, and the working efficiency of the second CPU core 200 can be improved.

[0065] like Figure 4 As shown, the first core pipeline 110 and the second core pipeline 210 are respectively connected to the address bus.

[0066] in, Figure 4 The AMBA in it stands for address bus.

[0067] Specifically, by connecting the first core pipeline 110 and the second core pipeline 210 to the address bus respectively, the user can control which core TCM the first CPU core 100 and the second CPU core 200 use through the address bus.

[0068] In combination with the above-mentioned core TCM structure based on CPU multi-cores, the embodiment of the present disclosure provides a core TCM control method based on CPU multi-cores, and the core TCM control method is applied to a chip provided with the above-mentioned core TCM structure. Figure 5 As shown, the nuclear TCM control method includes:

[0069] S501, when the chip is configured in split-lock mode, the selector of the CPU core receives an external control signal.

[0070] Specifically, when the chip is configured in split-lock mode, the operating modes of the first CPU core and the second CPU core can be controlled respectively by inputting an external control signal to the selector of the CPU core. Therefore, if the chip is configured in split-lock mode, the selector of the CPU core needs to receive the external control signal.

[0071] S502 , according to whether the external control signal is pulled high or low, the selector selects the first core pipeline and the second core pipeline to control the first core TCM and the second core TCM respectively.

[0072] Specifically, when the CPU works in split mode, the first CPU core controls its own first core TCM through the first core pipeline, and the second CPU core controls its own second core TCM through the second core pipeline. When the CPU works in lock mode, the second core TCM will not be used by the second CPU core through the second core pipeline. At this time, the first CPU core can simultaneously control the first core TCM and the second core TCM through the first core pipeline. When the external control signal is in a high state, the CPU works in split mode. When the external control signal is in a low state, the CPU works in lock mode. Therefore, depending on whether the external control signal is pulled high or low, the selector can select the first core TCM and the second core TCM controlled by the first core pipeline and the second core pipeline respectively.

[0073] Optionally, when the external control signal is pulled high, the CPU operates in split mode, and the selector selects the second core pipeline as the control signal of the second CPU core; when the external control signal is pulled low, the CPU operates in lock mode, and the selector selects the first core pipeline as the control signal of the second CPU core.

[0074] Specifically, when the CPU is working in lock mode, the second core TCM in the second CPU core is in a static idle state. Therefore, if the external control signal is in a low state, when the CPU is working in lock mode, the selector can select the first core pipeline as the control signal of the second CPU core, doubling the TCM capacity that can be used by the first CPU core.

[0075] Optionally, the CPU operates in a lock mode, including: a clock of a second core TCM of the second CPU core is in an on state, so that the first CPU core normally uses the second core TCM of the second CPU core.

[0076] S503: The address bus connects the first core pipeline and the second core pipeline respectively, and accesses the first core TCM and the second core TCM through the TCM interface.

[0077] Specifically, since the address bus is connected to the first core pipeline and the second core pipeline respectively, the address bus can access the first core TCM and the second core TCM through the TCM interface.

[0078] Optionally, the CPU operates in lock mode, further comprising: when the address bus is a low-order address, the first CPU core uses a first-core TCM; when the address bus is a high-order address, the first CPU core uses a second-core TCM.

[0079] Specifically, if the address bus is a low-order address, it indicates that the user needs to access the first core TCM. Therefore, in this case, the first CPU core will use the first core TCM.

[0080] Specifically, if the address bus is a high-order address, it indicates that the user needs to access the second core TCM. Therefore, in this case, the first CPU core will use the second core TCM.

[0081] Optionally, when the address bus is a high-order address, a chip select signal of a first core TCM in the first CPU core is disabled.

[0082] Specifically, when the address bus is a high-order address, the user needs to access the second core TCM. At this time, if the chip select signal of the first core TCM is in a valid state, the first core pipeline may mistakenly access the first core TCM, resulting in conflicts and increased waiting time. Therefore, in this case, it is necessary to fail the chip select signal of the first core TCM.

[0083] In the embodiment of the present disclosure, when the chip is configured in split-lock mode, the first CPU core and the second CPU core can be operated in lock mode by inputting an external control signal in a low state to the selector of the CPU core, so that the selector can select the first core pipeline as the control signal of the second CPU core, and the TCM capacity that can be used by the first CPU core is doubled, so that the user can access the first core TCM and the second core TCM through the TCM interface based on the address bus connected to the first core pipeline and the second core pipeline respectively. In this way, when the second core TCM of the second CPU core is in a static idle state, the selector can enable the first core pipeline to access the second core TCM according to the external control signal. Therefore, the embodiment of the present disclosure can reduce the waste of CPU circuit resources and improve the resource utilization of the CPU.

[0084] like Figure 6 As shown, the chip 600 includes: a first CPU core 100 and a second CPU core 200. The core TCM structure 10 as described above is deployed in the first CPU core 100 and the second CPU core 200.

[0085] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0086] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0087] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0088] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0089] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A core TCM structure based on CPU multi-core, characterized in that: The core TCM structure is built into the CPU core. The CPU includes N CPU cores arranged in a first order, where N is an integer greater than 1. The N CPU cores include a first CPU core and a second CPU core. The first CPU core is the i-th CPU core among the N CPU cores, and the second CPU core is the i+1-th CPU core among the N CPU cores, where i=1, 2...N. The first core TCM is connected to the first core pipeline and is built into the first CPU core; The second core pipeline is connected to the selector input end, and the second core TCM is connected to the selector output end, and is built into the second CPU core; The first core pipeline accesses the second core TCM by connecting to the selector input in the second CPU core; The selector controls the split-lock working mode of the CPU by receiving the external control signal being pulled high or low, and selects the first core pipeline and the second core pipeline to control the first core TCM and the second core TCM respectively.

2. The core TCM structure according to claim 1, characterized in that: The first CPU core is provided with a first TCM interface, the first core TCM includes a plurality of first sub-core TCMs, the plurality of first sub-core TCMs are connected to the first TCM interface, and the first core pipeline is connected to the plurality of first sub-core TCMs through the first TCM interface.

3. The core TCM structure according to claim 2, characterized in that: The second CPU core is provided with a second TCM interface, the second core TCM includes a plurality of second sub-core TCMs, and the plurality of second sub-core TCMs are connected to the second TCM interface; The plurality of first sub-core TCMs correspond one to one with the plurality of second sub-core TCMs; The second core pipeline is connected to the plurality of second sub-core TCMs through a second TCM interface.

4. The core TCM structure according to any one of claims 1 to 3, characterized in that: The first CPU core also includes: a first data cache and a first instruction cache; The first data buffer and the first instruction buffer are respectively connected to the first core pipeline.

5. The core TCM structure according to any one of claims 1 to 3, characterized in that: The second CPU core also includes: a second data cache and a second instruction cache; The second data buffer and the second instruction buffer are respectively connected to the second core pipeline.

6. The core TCM structure according to any one of claims 1 to 3, characterized in that: The first core pipeline and the second core pipeline are connected to the address bus respectively.

7. A core TCM control method based on CPU multi-core, applied to a chip having a core TCM structure as described in any one of claims 1 to 6, characterized in that: Methods include: When the chip is configured in split-lock mode, the selector of the CPU core receives an external control signal; According to whether the external control signal is pulled high or low, the selector selects the first core pipeline and the second core pipeline to control the first core TCM and the second core TCM respectively; The address bus is connected to the first core pipeline and the second core pipeline respectively, and the first core TCM and the second core TCM are accessed through the TCM interface.

8. The control method according to claim 7, characterized in that: When the external control signal is pulled high, the CPU works in split mode, and the selector selects the second core pipeline as the control signal of the second CPU core; When the external control signal is pulled low, the CPU works in lock mode, and the selector selects the first core pipeline as the control signal of the second CPU core.

9. The control method according to claim 8, characterized in that: The CPU works in lock mode, including: The clock of the second core TCM of the second CPU core is in an on state, so that the first CPU core normally uses the second core TCM of the second CPU core.

10. The control method according to claim 9, characterized in that: The CPU works in lock mode, including: When the address bus is a low-order address, the first CPU core uses the first core TCM; When the address bus has a high address, the first CPU core uses the second core TCM.

11. The control method according to claim 10, characterized in that: In the case where the address bus is a high-order address, the chip selection signal of the first core TCM in the first CPU core is disabled.

12. A chip, characterized in that: include: A first CPU core and a second CPU core; The core TCM structure according to any one of claims 1 to 6 is deployed in the first CPU core and the second CPU core.

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