Memory, access control method thereof and electronic equipment

Abstract

A memory and an access control method thereof, and an electronic device, the memory comprising: at least one memory array and a plurality of sense amplifiers connected to the memory array, each of the memory arrays comprising a plurality of layers of stacked memory cell arrays; the plurality of common bit lines are connected with the bit lines in the plurality of layers of storage unit arrays, each common bit line is connected with one sensing amplifier, and a switch sub-circuit is arranged between each common bit line and the sensing amplifier correspondingly connected with the common bit line, the switch sub-circuit is configured as follows: in a signal sensing stage, the common bit line is communicated with the corresponding sensing amplifier; and in a signal amplification stage, the common bit line and the corresponding sensing amplifier are disconnected. According to the scheme provided by the embodiment, the common bit line and the sensing amplifier can be disconnected in the signal amplification stage, and the influence of capacitive coupling between the bit lines on data reading of the sensing amplifier can be reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design in the field of semiconductor technology, and in particular to a memory and an access control method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. There is coupling between device units, which may affect data readout. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present disclosure provides a memory, comprising: at least one memory array and a plurality of sense amplifiers connected to the memory array, each of the memory arrays comprising a multi-layer stacked memory cell array;

[0006] A plurality of common bit lines are connected to the bit lines in the multi-layer memory cell array, each of the common bit lines corresponds to one of the sense amplifiers, and a switch subcircuit is provided between each of the common bit lines and the sense amplifier corresponding to the common bit line, wherein:

[0007] The switch subcircuit is configured to: connect the common bit line with the corresponding sense amplifier in a signal sensing phase; and disconnect the common bit line with the corresponding sense amplifier in a signal amplification phase.

[0008] In some embodiments, the switch subcircuit is a switch transistor, a gate electrode of the switch transistor is connected to a gate control terminal, a first electrode of the switch transistor is connected to the common bit line, and a second electrode of the switch transistor is connected to an input terminal of the sense amplifier.

[0009] In some embodiments, the memory includes multiple memory arrays, and in two adjacent memory arrays, every two common bit lines belonging to different memory arrays are connected to the same sensing amplifier, and one of the common bit lines is connected to the first input terminal of the sensing amplifier through a first switching transistor, and the other common bit line is connected to the second input terminal of the sensing amplifier through a second switching transistor.

[0010] In some embodiments, the memory cell in the memory cell array includes an access transistor; the same layer of the memory cell array includes multiple bit lines, each bit line corresponds to a third switch transistor, and the multiple bit lines are respectively connected to one common bit line through the corresponding third switch transistors.

[0011] In some embodiments, the bit line is a read bit line;

[0012] The storage unit includes a read transistor and a write transistor, and the same layer of storage unit array includes multiple read bit lines connected to the read transistors; each read bit line corresponds to a third switch transistor, and multiple read bit lines are respectively connected to one common bit line through the corresponding third switch transistors.

[0013] In some embodiments, multiple switch sub-circuits connected to multiple common bit lines of the same storage array are connected to the same control line, the control line is connected to the gate control terminal, and the control line is configured to: simultaneously turn on or off the multiple switch sub-circuits.

[0014] In some embodiments, the memory further includes a plurality of voltage stabilizing sub-circuits corresponding one-to-one to the common bit lines, each of the voltage stabilizing sub-circuit being connected between the sensing amplifier and the switching sub-circuit connected to the corresponding common bit line, one end of the switching sub-circuit being connected to the sensing amplifier and the voltage stabilizing sub-circuit, and the other end being connected to the common bit line.

[0015] In some embodiments, the voltage stabilizing subcircuit is a capacitor, one end of the capacitor is connected to the switch subcircuit and the sensing amplifier, and the other end of the capacitor is connected to a fixed voltage terminal.

[0016] In some embodiments, the capacitor is a MOS capacitor.

[0017] The present disclosure provides a method for controlling access to a memory, including:

[0018] In a signal sensing phase of a memory cell, controlling a switch subcircuit connected to a common bit line of the memory cell to be turned on, so that the common bit line is electrically connected to the corresponding sense amplifier;

[0019] During the signal amplification phase, the switch subcircuit is controlled to be closed so that the common bit line is disconnected from the sense amplifier.

[0020] In some embodiments, the method further includes: in a data write-back phase, turning on the switch subcircuit so that the corresponding common bit line is electrically connected to the sense amplifier, wherein the storage unit includes a transistor and a capacitor.

[0021] In some embodiments, the method further includes: in a pre-charging phase before the signal sensing phase, turning on the switch sub-circuit so that the corresponding common bit line is electrically connected to the sense amplifier.

[0022] An embodiment of the present disclosure provides an electronic device, comprising the memory described in any of the above embodiments.

[0023] In some embodiments, the electronic device further includes a control circuit, and the control circuit is configured to perform access control on the memory according to the access control method described in any of the above embodiments.

[0024] The present application includes a memory and an access control method thereof, and an electronic device, wherein the memory includes: at least one memory array and a plurality of sense amplifiers connected to the memory array, each memory array includes a multi-layer stacked memory cell array, a plurality of common bit lines correspond one-to-one to the multi-layer memory cell array, each common bit line is connected to a sense amplifier, and a switch subcircuit is provided between each common bit line and the connected sense amplifier, wherein the switch subcircuit is configured to: connect the common bit line of the memory array with the sense amplifier in the signal sensing stage; and disconnect the common bit line from the sense amplifier in the signal amplification stage. The solution provided in this embodiment disconnects the storage data sensing end from the sense amplifier in the signal amplification stage, which can isolate the influence of the bit line coupling on the sense amplifier and avoid data readout errors.

[0025] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings.

[0026] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0028] Figure 1 A schematic diagram of a logic circuit of a memory provided by a technical solution;

[0029] Figure 2 A schematic diagram of a memory logic circuit provided for an exemplary embodiment;

[0030] Figure 3 A schematic diagram of a memory logic circuit provided for another exemplary embodiment;

[0031] Figure 4 A schematic diagram of a memory logic circuit provided for yet another exemplary embodiment;

[0032] Figure 5 A schematic diagram of a sense amplifier logic circuit provided for an exemplary embodiment;

[0033] Figure 6 A control timing diagram of a memory provided for an exemplary embodiment;

[0034] Figure 7 A schematic diagram of a sense amplifier logic circuit is provided for an exemplary embodiment. DETAILED DESCRIPTION

[0035] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0036] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0037] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show limited embodiments, and the embodiments of the present disclosure are not limited to the embodiments shown in the drawings.

[0038] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0039] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0040] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0041] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0042] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0043] In the present disclosure, "connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0044] The memory may include multiple memory cells in a memory array. There may be coupling capacitance between adjacent bit lines in multiple memory cells. Especially in the application scenario of 3D stacked memory cells, in this case, the strong capacitive coupling between the bit lines will affect the signal sensing and signal amplification process in the signal readout stage, and may cause malfunction.

[0045] Figure 1 A schematic diagram of a 3D stacked storage array provided by a technical solution. Figure 1 As shown, the memory includes a plurality of memory arrays 1 located in different areas of a substrate, the memory array 1 includes a multi-layer memory cell array 10 vertically stacked on the substrate and a plurality of word lines WL extending in a direction perpendicular to the substrate, each layer of the memory cell array 10 includes a plurality of rows and columns of memory cells 11 and a plurality of bit lines, each column or every two columns of memory cells 11 is connected to a bit line, and each layer of the memory cell array 10 corresponds to a common bit line (such as Figure 1The common bit line BLn corresponding to the n-th memory cell array, the common bit line BLn-1 corresponding to the n-1-th memory cell array, and the common bit line BLn+1 corresponding to the n+1-th memory cell array are shown in FIG. 1 . The bit lines of the memory cell array 10 of this layer are connected to the common bit lines corresponding to each layer of the memory cell array 10, and a switch transistor ( Figure 1 (not shown), when a common bit line is selected, one of the multiple switch transistors connected to the common bit line is turned on, and the corresponding bit line is connected to the common bit line, and the other switch transistors are turned off, so that the other bit lines are disconnected from the common bit line. Each time a signal of a storage unit is read, it needs to be electrically connected to a bit line through the corresponding common bit line. When reading the signal on the bit line, there is a large coupling capacitance between the bit lines or common bit lines of adjacent layers, and the coupling capacitance may affect the amplification and reading of the data. For example, suppose the data stored in the storage unit 11 connected to the common bit line BL n is "0", and the data stored in the storage unit 11 connected to the adjacent common bit lines BL n-1, BL n+1 is "1". When the WL of the memory cell 11 connected to the common bit line BL n is activated, during the charge sharing process of the common bit line BL n, although a sufficiently large negative ΔV is generated between BL n and the reference signal line BLB n connected to the two input terminals of a sense amplifier, the polarity of the amplified data may be reversed in the subsequent signal amplification due to the large capacitive coupling between the bit lines, resulting in reading of erroneous data, because the strong capacitive coupling between BLn and BL n-1, BL n and BL n+1, BLB n and BLB n-1, and BLB n and BLB n+1 may reverse the voltage between BL n and the reference signal line BLB n (e.g., from -3 V to +3 V). The reason is that when the corresponding sense amplifier generates a voltage (forward voltage) corresponding to the data "1" between BLn-1 and BLBn-1, BLn+1 and BLBn+1, the common bit line BLn-1 and the common bit line BLn+1 will increase the voltage of BLn respectively, and the common bit line BLBn-1 and the common bit line BLBn+1 will reduce the voltage of BLBn respectively due to capacitive coupling, thereby generating a forward voltage between BLn and BLBn, which is opposite to the actually required voltage (the voltage corresponding to the data "0"), resulting in data read errors.

[0046] In the disclosed embodiment, a switch subcircuit is added between each common bit line and the sensing amplifier connected thereto, and the switch subcircuit is used to control the connection and disconnection of the signal between the common bit line and the sensing amplifier, thereby preventing the capacitive coupling between the bit lines from affecting the amplification and accurate reading of data by the data sensing amplifier.

[0047] The present disclosure provides a memory, comprising: at least one memory array and a plurality of sense amplifiers connected to the memory array, each memory array comprising a multi-layer stacked memory cell array, a plurality of common bit lines connected to the bit lines in the multi-layer memory cell array, each of the common bit lines corresponding to one of the sense amplifiers, and a switch subcircuit arranged between each of the common bit lines and the corresponding sense amplifier, wherein:

[0048] The switch subcircuit is configured to: control the connection and disconnection between the common bit line of the storage array and the sense amplifier; connect the common bit line with the corresponding sense amplifier in the signal sensing stage; and disconnect the common bit line with the corresponding sense amplifier in the signal amplification stage.

[0049] The solution provided in this embodiment, by setting a switch subcircuit for controlling the connection and disconnection between the common bit line of the storage array and the sensing amplifier, can disconnect the common bit line and the sensing amplifier after the signal sensing stage, thereby isolating the influence of the bit line coupling capacitance on the data amplified by the sensing amplifier and avoiding data readout errors.

[0050] The sense amplifier is configured to determine the data stored in the storage unit according to the signal change of the common bit line during the signal amplification stage.

[0051] The memory cell may be a 1T1C structure including an access transistor and a capacitor, or a 2T0C structure including a read transistor and a write transistor, or a 2T1C structure including a read transistor, a write transistor and a capacitor. The common bit line may be connected to the bit line of the memory cell array 10; or, it may be connected to the read bit line of the memory cell array 10. For example, when the memory cell is a 1T1C structure, the common bit line may be connected to the bit line of the memory cell array; when the memory cell is a 2T0C structure and the read bit line and the write bit line are combined into one bit line, the common bit line may be connected to the bit line of the memory cell array; when the memory cell is a 2T0C structure or a 2T1C structure and the read bit line and the write bit line are independent, the common bit line may be connected to the read bit line of the memory cell array.

[0052] In some embodiments, the memory may include multiple memory arrays, and in two adjacent memory arrays, every two common bit lines belonging to different memory arrays are connected to the same sensing amplifier, and one of the common bit lines is connected to the first input terminal of the sensing amplifier through a first switching sub-circuit, and the other common bit line is connected to the second input terminal of the sensing amplifier through a second switching sub-circuit.

[0053] In some embodiments, the switch subcircuit may be a switch transistor. The first switch subcircuit may include a first switch transistor, and the second switch subcircuit may include a second switch transistor. In two adjacent storage arrays, every two common bit lines belonging to different storage arrays are connected to the same sense amplifier, and one of the common bit lines is connected to the first input terminal of the sense amplifier through the first switch transistor, and the other common bit line is connected to the second input terminal of the sense amplifier through the second switch transistor. In some embodiments, the storage cell includes an access transistor and a capacitor; the same layer of storage cell array includes multiple bit lines, each bit line corresponds to a third switch transistor, each bit line is connected to one of the common bit lines through the corresponding third switch transistor, and multiple bit lines are connected to one of the common bit lines through multiple third switch transistors.

[0054] In some embodiments, the memory cell includes a read transistor and a write transistor, and the same layer of memory cell array includes a plurality of read bit lines connected to the read transistors; each read bit line corresponds to a third switch transistor, and the plurality of read bit lines are connected to one common bit line through the corresponding third switch transistors. At this time, the same layer of memory cell array also includes a plurality of write bit lines connected to the write transistors, and the common bit lines may include a read common bit line and a write common bit line, and the plurality of read bit lines are connected to one read common bit line, and the plurality of write bit lines are connected to one write common bit line.

[0055] In some embodiments, the sense amplifier may include two input ports, such as Figure 2 The first input terminal S1 and the second input terminal S2 are shown. The first input terminal S1 can be connected to a common bit line corresponding to the first storage array through the first switch sub-circuit, and the second input terminal S2 can be connected to a common bit line corresponding to the second storage array through the second switch sub-circuit. The first storage array and the second storage array can be different storage arrays, or the first storage array and the second storage array can be the same storage array, and the first input terminal S1 and the second input terminal S2 are connected to different common bit lines corresponding to the same storage array, for example, respectively connected to a read common bit line and a write common bit line corresponding to the same storage array.

[0056] The present disclosure also provides a method for controlling access to a memory, including:

[0057] In a signal sensing phase of a memory cell, controlling a switch subcircuit connected to a common bit line of the memory cell to be turned on, so that the common bit line is electrically connected to the corresponding sense amplifier;

[0058] During the signal amplification phase, the switch subcircuit is controlled to be closed, so that the common bit line is disconnected from the sense amplifier signal.

[0059] The access control method provided by this embodiment connects the common bit line with the sense amplifier in the signal sensing stage to detect the voltage of the common bit line, and disconnects the common bit line from the sense amplifier in the signal amplification stage. Even if the voltage of the common bit line changes due to the influence of the adjacent common bit line, the change will not be transmitted to the sense amplifier, thereby avoiding the influence of the voltage change of the common bit line caused by coupling on the sense amplifier, so that the data can be read correctly. The subsequent sense amplifier has completed the sense amplification of the data, and even if the voltage of the common bit line changes due to the influence of coupling, it will not affect the accurate amplification and data output of the sense amplifier.

[0060] In some embodiments, the method may further include: in a data write-back phase after the signal amplification phase, turning on the switch subcircuit so that the corresponding common bit line and the sense amplifier are electrically connected, so that data can be written back to the storage unit. When the structure of the storage unit is different, the data write-back phase may be set or not. For example, a storage unit with a 1T1C structure needs to perform data write-back.

[0061] In some embodiments, for different bit lines of two storage arrays connected to the same sense amplifier, the method may further include: in a pre-charging stage before the signal sensing stage, turning on the switch sub-circuit so that the corresponding common bit line and the sense amplifier are electrically connected. In the pre-charging stage, the voltage of the first input terminal S1 and the second input terminal S2 of the sense amplifier may be pre-set so that there is a voltage difference between the two ends. Therefore, the common bit line is connected to the sense amplifier for pre-charging. The pre-charging voltage varies according to the different structures of the storage cells and the different structures of the sense amplifiers, and pre-charging can be performed as needed.

[0062] The following takes the storage units of 1T1C and 2T0C as examples for description.

[0063] Figure 2 FIG. 1 is a schematic diagram of a memory logic circuit provided by an exemplary embodiment. Figure 2 As shown, the memory provided in this embodiment includes a plurality of storage arrays 1, Figure 2 2 memory arrays 1 are shown in FIG. The memory array 1 includes a multi-layer memory cell array 10 vertically stacked on a substrate and a plurality of word lines WL extending in a direction perpendicular to the substrate. Each layer of the memory cell array 10 includes a plurality of rows and columns of memory cells 11 and a plurality of bit lines. Each column or every two columns of memory cells 11 is connected to a bit line. Each layer of the memory cell array 10 corresponds to a common bit line. The common bit line BL can be parallel to the substrate ( Figure 2BL n-1, BL n, BL n+1 corresponding to the three-layer memory cell array are shown in FIG. A word line WL connects a column of memory cells 11 stacked vertically on the substrate. Each memory cell 11 includes an access transistor T1 and a first capacitor C1, wherein the gate electrode of the access transistor T1 is connected to the word line WL, the first electrode of the access transistor T1 is connected to the common bit line BL, the second electrode of the access transistor is connected to one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to a reference end (the reference end is, for example, a ground end). There may be a first coupling capacitor C2 between the common bit lines BL, and there may be a second coupling capacitor C3 between the common bit line BL and other electrodes or leads (for example, between the common bit line BL and the word line WL). The memory may also include: a plurality of sense amplifiers SA and a plurality of switch subcircuits 20. In this embodiment, the sense amplifier SA can determine whether the data stored in the memory cell 11 is a logical value 1 or 0 by sensing the signal change of the common bit line BL before and after charge sharing. Each common bit line BL is connected to one end of a switch subcircuit 20, and the other end of the switch subcircuit 20 is connected to an input end of the sense amplifier SA. The switch subcircuit 20 can control the connection (electrical connection) and disconnection between the common bit line BL and the sense amplifier SA. The sense amplifier SA may include two input ports: a first input terminal S1 and a second input terminal S2. One of the first input terminal S1 and the second input terminal S2 may be used as a signal detection terminal, and the other may be used as a signal reference terminal. For example, Figure 2 In the storage array 1 on the left side, the second input terminal S2 can be used as a signal reference terminal; the first input terminal S1 is used as a signal detection terminal, which is connected to the common bit line BL to detect the signal change of the common bit line BL, thereby amplifying and reading the storage data of the storage unit connected to the first input terminal S1.

[0064] Or, for Figure 2 In the storage array 1 on the right side, the first input terminal S1 can be used as a signal reference terminal, and the second input terminal S2 can be used as a signal detection terminal to detect the signal change of the bit line, so as to realize the reading of the storage data of the storage unit connected to the second input terminal S2. If the common bit lines of two adjacent storage arrays share SA, the two input terminals are connected to the two common bit lines. When detecting the signal change of one of the common bit lines, the other common bit line is used as the signal reference terminal.

[0065] In some embodiments, Figure 3 As shown, the switch subcircuit 20 may include a switch transistor T2, a gate electrode of the switch transistor T2 is connected to a gate control terminal of the peripheral circuit through a control line, a first electrode is connected to the common bit line BL, and a second electrode is connected to an input terminal of the sense amplifier SA. The switch transistor T2 may be an N-type transistor, but the embodiments of the present disclosure are not limited thereto, and the switch transistor T2 may be a P-type transistor.

[0066] In some embodiments, the switch subcircuit 20 can be connected to the control line and turned on or off under the control of the control line. Multiple switch subcircuits 20 connected to multiple common bit lines of the same memory array are connected to the same control line, and the control line is configured to simultaneously turn on or off the multiple switch subcircuits 20 connected to the control line.

[0067] In some embodiments, the memory may include multiple memory arrays, and in two adjacent memory arrays, every two common bit lines belonging to different memory arrays are connected to the same sense amplifier SA, and one of the common bit lines is connected to the first input terminal S1 of the sense amplifier through a first switch transistor, and the other common bit line is connected to the second input terminal S2 of the sense amplifier through a second switch transistor. Figure 3 As shown, the memory may include a first memory array and a second memory array, a common bit line BLn-1 belonging to the first memory array and a common bit line BLBn-1 belonging to the second memory array are connected to the same SA, and the common bit line BLn-1 is connected to the first input terminal S1 of the sense amplifier through a first switch transistor T2_1, and the common bit line BLBn-1 is connected to the second input terminal S2 of the sense amplifier through a second switch transistor T2_2.

[0068] like Figure 2 As shown, the memory may include a first memory array and a second memory array, and a plurality of switch subcircuits respectively connected to a plurality of common bit lines of the first memory array may be connected to the same control line, for example, the first control line ISO, and a plurality of switch subcircuits respectively connected to a plurality of common bit lines of the second memory array may be connected to the same control line, for example, the second control line ISO*. Accordingly, when the switch subcircuits are switch transistors, the gate electrodes of a plurality of first switch transistors respectively connected to a plurality of common bit lines of the first memory array may be connected to the first control line ISO, and the gate electrodes of a plurality of second switch transistors respectively connected to a plurality of common bit lines of the second memory array may be connected to the second control line ISO*.

[0069] In some embodiments, Figure 3As shown, the memory may include a first switch subcircuit 21 and a second switch subcircuit 22 connected to the same SA, the first switch subcircuit 21 includes a first switch transistor T2_1, the gate electrode of the first switch transistor T2_1 is connected to the first control line ISO, the first electrode is connected to the common bit line BL n-1, and the second electrode is connected to the first input terminal S1 of the sense amplifier SA; the second switch subcircuit 22 includes a second switch transistor T2_2, the gate electrode of the second switch transistor T2_2 is connected to the second control line ISO*, the first electrode is connected to the common bit line BLB n-1, and the second electrode is connected to the second input terminal S2 of the sense amplifier SA.

[0070] In some embodiments, Figure 4 As shown, the memory may also include a plurality of voltage stabilizing subcircuits 30 corresponding to the common bit lines one by one, each of the voltage stabilizing subcircuits 30 being connected between the sensing amplifier SA and the switch subcircuit 20 connected to the corresponding common bit line, one end of the switch subcircuit 20 being connected to the sensing amplifier SA and the voltage stabilizing subcircuit 30, and the other end being connected to the common bit line. For example, the voltage stabilizing subcircuit 30 is connected between the connection terminal P between the switch subcircuit 20 and the sensing amplifier SA and a fixed voltage terminal. The voltage stabilizing electronic circuit 30 is configured to stabilize the voltage at the input terminal of the sensing amplifier SA. Both the first input terminal S1 and the second input terminal S2 of the sensing amplifier SA may be connected to the voltage stabilizing subcircuit 30. The fixed voltage terminal is, for example, a ground terminal.

[0071] In some embodiments, Figure 4 As shown, the voltage stabilizing subcircuit 30 may include a capacitor C4, a first end of the capacitor C4 may be connected to the switch subcircuit and the sense amplifier, and the other end of the capacitor C4 may be connected to the fixed voltage end.

[0072] In some embodiments, the capacitor C4 may be a MOS capacitor (MOSCAP). A MOS capacitor is prepared using a transistor, and the gate electrode of the transistor may be used as one electrode of the capacitor, and the source electrode, the drain electrode and the substrate of the transistor may be connected as another electrode of the capacitor, or the substrate of the transistor may be used as another electrode of the capacitor, and so on, and the gate insulating layer of the transistor may be used as a dielectric layer between the two electrodes. Compared with conventional capacitors including two metal electrodes, MOS capacitors can be prepared simultaneously when manufacturing the transistors of the storage unit, which can simplify the process, and the area of ​​MOS capacitors is smaller than the area of ​​capacitors with two metal electrodes, which can save area.

[0073] Figure 5 FIG. 1 is a circuit diagram of a sense amplifier SA provided by an exemplary embodiment. The sense amplifier SA may be applied in a memory including a 1T1C storage unit. Figure 5As shown, the sense amplifier SA may include a third transistor T3, a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6, the gate electrode of the third transistor T3 and the gate electrode of the fifth transistor T5 may be connected to the second input terminal S2, the first electrode of the third transistor T3 and the first electrode of the fourth transistor T4 are connected to the third control terminal SAP, the second electrode of the third transistor T3 is connected to the first electrode of the fifth transistor T5 and connected to the first input terminal S1, the gate electrode of the fourth transistor T4 and the gate electrode of the sixth transistor T6 are connected to the first input terminal S1, the second electrode of the fourth transistor T4 is connected to the first electrode of the sixth transistor T6 and connected to the second input terminal S2, the second electrode of the fifth transistor T5 is connected to the second electrode of the sixth transistor T6 and connected to the fourth control terminal SAN. The first input terminal S1 may be connected to the bit line BL through the first switch sub-circuit 21, and the second input terminal S2 may be connected to the bit line BLB through the second switch sub-circuit 22. In some embodiments, the third transistor T3 and the fourth transistor T4 may be P-type transistors, and the fifth transistor T5 and the sixth transistor T6 may be N-type transistors.

[0074] The following is an example to illustrate the working process of the memory. Figure 3 As shown, the sense amplifier is Figure 5 shown. Figure 6 This is a working timing diagram of the memory provided in this embodiment. Figure 6 As shown, in this embodiment, the access process to a certain storage unit of the memory includes a pre-charging stage t1, a charge sharing stage t2, a signal amplification stage t3 and a data write-back stage t4, wherein:

[0075] The transistors mentioned below are all described by taking n-type transistors as examples.

[0076] Precharge stage t1: a reference voltage Vref is loaded on a common bit line BL connected to an SA and a common bit line BLB used as a signal reference terminal, for example, Vref=VDD / 2; VDD can be a voltage corresponding to data "1"; a low-level signal is loaded on the word line WL to turn off the access transistor T1; a high-level signal is loaded on the first control line ISO and the second control line ISO* to turn on the first switch transistor T2_1 and the second switch transistor T2_2, connect the common bit line BL and the first input terminal S1, and connect the common bit line BLB and the second input terminal S2, the voltage on the common bit line BL is loaded on the first input terminal S1 of the sense amplifier SA, and the voltage on the common bit line BLB is loaded on the second input terminal S2 of the sense amplifier SA;

[0077] Charge sharing stage t2: i.e., signal sensing stage, a high-level signal is loaded on the word line WL to turn on the access transistor T1, so that the common bit line BL and the first capacitor C1 share charge. When the data stored in the first capacitor C1 is "1", the voltage on the common bit line BL is increased to be greater than Vref through charge sharing with the first capacitor C1, a high-level signal is loaded on the first control line ISO and the second control line ISO*, the first switch transistor T2_1 and the second switch transistor T2_2 are kept turned on, and the first switch transistor T2_1 connects the common bit line BL and the first input terminal S1, that is, the voltage of the first input terminal S1 is increased to be greater than Vref; when the data stored in the first capacitor C1 is "0", the voltage on the common bit line BL is reduced to be less than Vref through charge sharing with the first capacitor C1, a high-level signal is loaded on the first control line ISO and the second control line ISO*, the first switch transistor T2_1 and the second switch transistor T2_2 are kept turned on, and the transistor T2_1 is connected to the common bit line BL and the first input terminal S1, that is, the voltage of the first input terminal S1 is increased to be greater than Vref; when the data stored in the first capacitor C1 is "0", the voltage on the common bit line BL is reduced to be less than Vref through charge sharing with the first capacitor C1, the first control line ISO and the second control line ISO* are loaded with a high-level signal, the first switch transistor T2_1 and the second switch transistor T2_2 are kept turned on, and the transistor T T2_1 connects the common bit line BL and the first input terminal S1, that is, when the data stored in the first capacitor C1 is "1", the voltage of the first input terminal S1 increases to be greater than Vref; when the data stored in the first capacitor C1 is "0", the voltage of the first input terminal S1 decreases to be less than Vref;

[0078] Signal amplification stage t3: A high-level signal is loaded on the word line WL to maintain the access transistor T1 turned on. A low-level signal is loaded on the first control line ISO and the second control line ISO* to turn off the first switch transistor T2_1 and the second switch transistor T2_2, disconnect the common bit line BL and the first input terminal S1, and disconnect the common bit line BLB and the second input terminal S2. A voltage corresponding to data "1" is loaded on the third control terminal SAP, and a voltage corresponding to data "0" is loaded on the fourth control terminal SAN. Taking the data "1" stored in the first capacitor C1 as an example, at this time, the fifth transistor T5 and the sixth transistor T6 will be turned on to different degrees. Since the voltage of the first input terminal S1 is larger, the conduction degree of the sixth transistor T6 is slightly larger. The fourth control terminal SAN gradually pulls the voltage of the second input terminal S2 to the voltage corresponding to the data "0" through the sixth transistor T6, and the fifth transistor T5 is turned off due to the gradual decrease of the voltage of the second input terminal S2; in the process of the gradual decrease of the voltage of the second input terminal S2, the third transistor T3 is gradually turned on, and the third control terminal SAP pulls the voltage of the first input terminal S1 to the voltage corresponding to the data "1" through the third transistor T3, that is, the voltage of the first input terminal S1 is pulled up to the voltage corresponding to the data "1", such as VDD, and the second input terminal S2 is pulled down to the voltage corresponding to the data "0", such as the ground voltage. When the data stored in the first capacitor C1 is "0", that is, the voltage of the first input terminal S1 is pulled down to the voltage corresponding to the data "0", and the second input terminal S2 is pulled up to the voltage corresponding to the data "1".

[0079] In this stage, the common bit line BL and the first input terminal S1 are disconnected. Even if the common bit line BL is affected by the adjacent common bit line and causes a voltage change, the voltage change will not be transmitted to the first input terminal S1. The first input terminal S1 can correctly output the corresponding voltage according to the change of the common bit line BL in the charge sharing stage.

[0080] In the data write-back phase t4, a high-level signal is loaded on the word line WL to maintain the access transistor T1 turned on. A high-level signal is loaded on the first control line ISO and the second control line ISO* to connect the common bit line BL and the first input terminal S1, and to connect the common bit line BLB and the second input terminal S2. Taking the read data as "1" as an example, at this time, the voltage of the first input terminal S1 is the voltage corresponding to the data "1", and the voltage of the first input terminal S1 is loaded to the common bit line BL, and the common bit line BL shares charge with the first capacitor C1. The voltage of the first capacitor C1 is increased to the voltage corresponding to the data "1", and the data is written back. Taking the read data as "0" as an example, at this time, the voltage W of the first input terminal S1 is the voltage corresponding to the data "0", and the voltage of the first input terminal S1 is loaded to the common bit line BL, and the common bit line BL shares charge with the first capacitor C1. The voltage of the first capacitor C1 is reduced to the voltage corresponding to the data "0", and the data is written back.

[0081] Figure 7 FIG. 1 is a circuit diagram of a memory provided by another exemplary embodiment. In this embodiment, the memory cell is a 2T0C structure. Figure 7 As shown, the memory may include a memory cell 11, a sense amplifier SA, a first switch sub-circuit 21, a second switch sub-circuit 22, and a first control circuit 50. The memory cell 11 includes a write transistor Tw and a read transistor Tr, wherein the gate electrode of the write transistor Tw is connected to a write word line WWL, the first electrode is connected to a write common bit line WBL, and the second electrode is connected to the gate electrode of the read transistor Tr, the first electrode of the read transistor Tr is connected to a read word line RWL, and the second electrode is connected to a read common bit line RBL, the read common bit line RBL is connected to a first input terminal S1 of the sense amplifier SA through the first switch sub-circuit 21, and the write common bit line WBL is connected to a second input terminal S2 of the sense amplifier SA through the second switch sub-circuit.

[0082] The first control circuit 50 is configured to load a voltage of 2 / 3VDD or a voltage of VDD to the read word line RWL under the control of the first control signal N_RE and the third control signal RE. The first control circuit 50 may include an eleventh transistor T11 and a twelfth transistor T12, wherein the gate electrode of the eleventh transistor T11 is connected to the third control signal RE, the first electrode is connected to the read word line RWL, and the second electrode is connected to a voltage terminal providing a voltage of 2 / 3VDD, and the gate electrode of the twelfth transistor T12 is connected to the first control signal N_RE, the first electrode is connected to the read word line RWL, and the second electrode is connected to a voltage terminal providing a voltage of VDD; the eleventh transistor T11 and the twelfth transistor T12 may be, for example, P-type transistors, but are not limited thereto, and may be N-type transistors.

[0083] The sense amplifier SA may include a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16 and a seventeenth transistor T17, an inverter 60, wherein:

[0084] The seventh transistor T7 to the tenth transistor T10 constitute a sensing amplifier subcircuit 70, which senses and amplifies the signal read through the first input terminal S1 and outputs a voltage corresponding to the data of the storage unit. The gate electrode of the seventh transistor T7 is connected to the second electrode of the eighth transistor T8 and the first electrode of the tenth transistor T10, the first electrode of the seventh transistor T7 and the second electrode of the eighth transistor T8 are connected to the voltage terminal VDD (providing the VDD voltage), the second electrode of the seventh transistor T7 is connected to the first electrode of the ninth transistor T9 and the gate electrode of the eighth transistor T8, the gate electrode of the ninth transistor T9 is connected to the first input terminal S1, the second electrode of the ninth transistor T9 is connected to the second electrode of the tenth transistor T10 and the first electrode of the fifteenth transistor T15, the gate electrode of the tenth transistor T10 is connected to the first electrode of the seventeenth transistor T17; the gate electrode of the eighth transistor T8 is connected to one end of the inverter 60; in some embodiments, the seventh transistor T7 and the eighth transistor T8 may be P-type transistors, and the ninth transistor T9 and the tenth transistor T10 may be N-type transistors, which are only examples.

[0085] The thirteenth transistor T13 and the fourteenth transistor T14 form a second control circuit, which is configured to load the voltage of VDD or the voltage of 3 / 2VDD to the first input terminal S1 under the control of the first control signal N_RE and the second control signal PRE. The gate electrode of the thirteenth transistor T13 is connected to the first control signal N_RE, the first electrode is connected to the first input terminal S1, and the second electrode is connected to the voltage terminal providing the VDD voltage. The gate electrode of the fourteenth transistor T14 is connected to the second control signal PRE, the first electrode is connected to the first input terminal S1, and the second electrode is connected to the voltage terminal providing the 3 / 2VDD voltage. The thirteenth transistor T13 and the fourteenth transistor T14 can be, for example, P-type transistors, but are not limited thereto, and can be N-type transistors.

[0086] The fifteenth transistor T15 forms a switch circuit to control whether the sensing amplifier sub-circuit 70 formed by the seventh transistor T7 to the tenth transistor T10 is turned on. The gate electrode of the fifteenth transistor T15 is connected to the sensing control signal SEN, and the second electrode is connected to the ground terminal GND. After the fifteenth transistor T15 is turned on, the voltage of the ground terminal GND is loaded to the second electrodes of the ninth transistor T9 and the tenth transistor T10. The fifteenth transistor T15 is, for example, an N-type transistor, but is not limited thereto.

[0087] The sixteenth transistor T16 constitutes a data write-back control circuit to control data write-back. After the sixteenth transistor T16 is turned on, the data can be written back to the storage unit 11. The gate electrode of the sixteenth transistor T16 is connected to the fourth control signal RE_W, the first electrode is connected to the second input terminal S2, the second electrode is connected to one end of the inverter 60, that is, the VOUT end, and the other end of the inverter 60 is connected to the gate electrode of the eighth transistor T8; the sixteenth transistor T16 is, for example, an N-type transistor, but is not limited thereto.

[0088] The seventeenth transistor T17 constitutes a reference voltage control circuit, and provides a reference voltage VREF to the sense amplifier sub-circuit 70 under the control of the second control signal PRE. The gate electrode of the seventeenth transistor T17 is connected to the second control signal PRE, the first electrode is connected to the gate electrode of the tenth transistor T10, and the second electrode is connected to the reference voltage terminal VREF, and the voltage of the reference voltage terminal VREF can be VDD. The seventeenth transistor T17 can be, for example, a P-type transistor, but is not limited thereto, and the reference voltage control circuit can be implemented using an N-type transistor.

[0089] The following is an example to illustrate Figure 7 The working process of the memory shown. In this embodiment, the working phase of the memory may include a pre-processing phase, a pre-charging phase, a signal sensing phase, a signal amplification phase and a data write-back phase, wherein:

[0090] In the pre-processing stage, the first control signal N_RE is at a low level, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, and the voltage VDD is loaded to the read word line RWL and the read common bit line RBL. If the data stored in the storage node SN is "1", the gate-source voltage Vgs of the read transistor Tr is 0 at this time. Since the threshold voltage Vth of the read transistor Tr is greater than zero, Vgs < Vth, the read transistor Tr is turned off; if the data stored in the storage node SN is "0", the gate-source voltage Vgs of the read transistor Tr is less than 0 at this time, Vgs < Vth, and the read transistor Tr is turned off. That is, regardless of whether the data stored in the storage cell 11 is "1" or "0", the read transistor Tr in the storage cell 11 is turned off, and the subsequent read operation will not cause interference.

[0091] In the pre-charging stage, a high-level signal is loaded on the first control line ISO and the second control line ISO*, the first switch circuit 21 and the second switch sub-circuit 22 are turned on, the second control signal PRE is at a low level, the fourteenth transistor T14 is turned on, and the voltage of 3 / 2VDD is loaded to the first input terminal S1. The first input terminal S1 pre-charges the read common bit line RBL. In this stage, since the read transistor Tr is turned off, the voltage of the read common bit line RBL after pre-charging will remain at 3 / 2VDD.

[0092] In the signal sensing stage, a high-level signal is loaded on the first control line ISO and the second control line ISO* to maintain the first switch circuit 21 and the second switch sub-circuit 22 turned on. The third control signal RE is at a low level, the eleventh transistor T11 is turned on, and the voltage of 2 / 3VDD is loaded to the read word line RWL. The second control signal PRE is at a high level, and the fourteenth transistor T14 is turned off. If the data stored in the storage node SN is "1", the read transistor Tr is turned on, and the voltage on the read common bit line RBL will change, that is, the voltage on the read common bit line RBL will change to the read word line RWL. WL is discharged, and the voltage on the read common bit line RBL is reduced to less than VDD; if the data stored in the storage node SN is "0", the read transistor Tr cannot be turned on, and the read common bit line RBL is in a floating state, and the voltage on it does not change and remains 3 / 2VDD. The voltage of the read common bit line RBL is loaded to the first input terminal S1, that is, when the data stored in the storage node SN is "1", the voltage of the first input terminal S1 is less than VDD, and when the data stored in the storage node SN is "0", the voltage of the first input terminal S1 is 3 / 2VDD.

[0093] In the signal amplification stage, a low-level signal is loaded on the first control line ISO and the second control line ISO*, the first switch circuit 21 and the second switch sub-circuit 22 are turned off, and after a preset time interval T after the output voltage 2 / 3VDD, the sensing control signal SEN is set to a high level, and the sense amplifier SA performs sensing amplification, and outputs the data stored in the storage unit 11 through VOUT according to the comparison result of the voltage of the first input terminal S1 and the reference voltage (VDD in this embodiment). In this stage, the voltage of the read common bit line RBL will not affect the voltage of the first input terminal S1, so that the data of the storage unit 11 can be correctly read.

[0094] In the data write-back phase, a low-level signal is loaded on the first control line ISO and the second control line ISO*, the first switch circuit 21 and the second switch sub-circuit 22 are turned on, connecting the first input terminal S1 and the read common bit line RBL, and the second input terminal S2 and the write common bit line WBL, the fourth control signal RE_W is at a high level, the sixteenth transistor T16 is turned on, the write word line WWL is at a high level, the write transistor Tw is turned on, and the data read out from the output terminal VOUT is written back to the corresponding storage unit 11 through the write common bit line WBL.

[0095] In another embodiment, the first switch subcircuit 21 may be connected between the first electrode of the third transistor T14 and the gate electrode of the ninth transistor T9 , that is, the second control circuit is directly connected to the common bit line RBL without being connected through the first switch subcircuit 21 .

[0096] The sense amplifier SA circuit shown in the embodiments of the present disclosure is only an example, and the present disclosure does not limit the sense amplifier SA circuit.

[0097] The present disclosure also provides an electronic device, including the memory described in the above embodiment. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0098] In some embodiments, the electronic device may further include a control circuit, the control circuit being configured to perform access control on the memory according to any of the access control methods described above. The control circuit may include a circuit and a control line that can generate a control signal to control the switch subcircuit, thereby implementing access control on the memory. The control circuit, together with the SA, etc., implements access to the memory.

[0099] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A memory, characterized in that: include: at least one memory array and a plurality of sense amplifiers connected to the memory array, each of the memory arrays comprising a multi-layer stacked memory cell array; A plurality of common bit lines are connected to the bit lines in the multi-layer memory cell array, each of the common bit lines corresponds to one of the sense amplifiers, and a switch subcircuit is provided between each of the common bit lines and the sense amplifier corresponding to the common bit line, wherein: The switch subcircuit is configured to: connect the common bit line with the corresponding sense amplifier in a signal sensing phase; and disconnect the common bit line with the corresponding sense amplifier in a signal amplification phase.

2. The memory according to claim 1, characterized in that: The switch subcircuit is a switch transistor, a gate electrode of the switch transistor is connected to a gate control terminal, a first electrode of the switch transistor is connected to the common bit line, and a second electrode of the switch transistor is connected to an input terminal of the sense amplifier.

3. The memory according to claim 2, characterized in that: The memory includes multiple memory arrays. In two adjacent memory arrays, every two common bit lines belonging to different memory arrays are connected to the same sensing amplifier, and one of the common bit lines is connected to the first input terminal of the sensing amplifier through a first switching transistor, and the other common bit line is connected to the second input terminal of the sensing amplifier through a second switching transistor.

4. The memory according to claim 3, characterized in that: The memory cell in the memory cell array includes an access transistor; the same layer of the memory cell array includes a plurality of the bit lines, each bit line corresponds to a third switch transistor, and the plurality of the bit lines are respectively connected to a common bit line through the corresponding third switch transistors.

5. The memory according to claim 3, characterized in that: The bit line is a read bit line; The memory cell comprises a read transistor and a write transistor, and the same layer of the memory cell array comprises a plurality of read bit lines connected to the read transistor; Each read bit line corresponds to a third switch transistor, and a plurality of the read bit lines are connected to one common bit line through the corresponding third switch transistors respectively.

6. The memory according to claim 2, characterized in that: The plurality of switch sub-circuits connected to the plurality of common bit lines of the same storage array are connected to the same control line, the control line is connected to the gate control terminal, and the control line is configured to simultaneously turn on or off the plurality of switch sub-circuits.

7. The memory according to any one of claims 1 to 6, characterized in that: The memory also includes a plurality of voltage stabilizing sub-circuits corresponding one-to-one to the common bit lines, each of the voltage stabilizing sub-circuits being connected between the sensing amplifier and the switch sub-circuit connected to the corresponding common bit line, one end of the switch sub-circuit being connected to the sensing amplifier and the voltage stabilizing sub-circuit, and the other end being connected to the common bit line.

8. The memory according to claim 7, characterized in that: The voltage stabilizing subcircuit is a capacitor, one end of which is connected to the switch subcircuit and the sensing amplifier, and the other end of which is connected to a fixed voltage terminal.

9. The memory according to claim 8, characterized in that: The capacitor is a MOS capacitor.

10. A method for controlling access to a memory as claimed in any one of claims 1 to 9, characterized in that: include: In a signal sensing phase of a memory cell, controlling a switch subcircuit connected to a common bit line of the memory cell to be turned on, so that the common bit line is electrically connected to the corresponding sense amplifier; During the signal amplification phase, the switch subcircuit is controlled to be closed so that the common bit line is disconnected from the sense amplifier.

11. The memory access control method according to claim 10, characterized in that: The method further includes: in a data write-back phase, turning on the switch subcircuit so that the corresponding common bit line is electrically connected to the sense amplifier, wherein the storage unit includes a transistor and a capacitor.

12. The memory access control method according to claim 10 or 11, characterized in that: The method further includes: in a pre-charging phase before the signal sensing phase, turning on the switch sub-circuit so that the corresponding common bit line is electrically connected to the sense amplifier.

13. An electronic device, characterized in that: Comprising the memory as claimed in any one of claims 1 to 9.

14. The electronic device according to claim 13, characterized in that: The electronic device further comprises a control circuit, wherein the control circuit is configured to perform access control on the memory according to the access control method according to any one of claims 10 to 12.

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